wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1 | # Porting U-Boot onto RPXlite board |
| 2 | # Written by Yoo. Jonghoon |
| 3 | # E-Mail : yooth@ipone.co.kr |
| 4 | # IP ONE Inc. |
| 5 | |
| 6 | # Since 2001. 1. 29 |
| 7 | |
| 8 | # Shell : bash |
| 9 | # Cross-compile tools : Montavista Hardhat |
| 10 | # Debugging tools : Windriver VisionProbe (PowerPC BDM) |
| 11 | # ppcboot ver. : ppcboot-0.8.1 |
| 12 | |
| 13 | ############################################################### |
| 14 | # 1. Hardware setting |
| 15 | ############################################################### |
| 16 | |
| 17 | 1.1. Board, BDM settings |
| 18 | Install board, BDM, connect each other |
| 19 | |
| 20 | 1.2. Save Register value |
| 21 | Boot with board-on monitor program and save the |
| 22 | register values with BDM. |
| 23 | |
| 24 | 1.3. Configure flash programmer |
| 25 | Check flash memory area in the memory map. |
| 26 | 0xFFC00000 - 0xFFFFFFFF |
| 27 | |
| 28 | Boot monitor program is at |
| 29 | 0xFFF00000 |
| 30 | |
| 31 | You can program on-board flash memory with VisionClick |
| 32 | flash programmer. Set the target flash device as: |
| 33 | |
| 34 | 29DL800B |
| 35 | |
| 36 | (?) The flash memory device in the board *is* 29LV800B, |
| 37 | but I cannot program it with '29LV800B' option. |
| 38 | (in VisionClick flash programming tools) |
| 39 | I don't know why... |
| 40 | |
| 41 | 1.4. Save boot monitor program *IMPORTANT* |
| 42 | Upload boot monitor program from board to file. |
| 43 | boot monitor program starts at 0xFFF00000 |
| 44 | |
| 45 | 1.5. Test flash memory programming |
| 46 | Try to erase boot program in the flash memory, |
| 47 | and re-write them. |
| 48 | *WARNING* YOU MUST SAVE BOOT PROGRAM TO FILE |
| 49 | BEFORE ERASING FLASH |
| 50 | |
| 51 | ############################################################### |
| 52 | # 2. U-Boot setting |
| 53 | ############################################################### |
| 54 | |
| 55 | 2.1. Download U-Boot tarball at |
| 56 | ftp://ftp.denx.de |
| 57 | (The latest version is ppcboot-0.8.1.tar.bz2) |
| 58 | |
| 59 | To extract the archive use the following syntax : |
| 60 | > bzip2 -cd ppcboot-0.8.1.tar.bz2 | tar xf - |
| 61 | |
| 62 | 2.2. Add the following lines in '.profile' |
| 63 | export PATH=$PATH:/opt/hardhat/devkit/ppc/8xx/bin |
| 64 | |
| 65 | 2.3. Make board specific config, for example: |
| 66 | > cd ppcboot-0.8.1 |
| 67 | > make TQM860L_config |
| 68 | |
| 69 | Now we can build ppcboot bin files. |
| 70 | After make all, you must see these files in your |
| 71 | ppcboot root directory. |
| 72 | |
| 73 | ppcboot |
| 74 | ppcboot.bin |
| 75 | ppcboot.srec |
| 76 | ppcboot.map |
| 77 | |
| 78 | 2.4. Make your own board directory into the |
| 79 | ppcboot-0.8.1/board |
| 80 | and make your board-specific files here. |
| 81 | |
| 82 | For exmanple, tqm8xx files are composed of |
| 83 | .depend : Nothing |
| 84 | Makefile : To make config file |
| 85 | config.mk : Sets base address |
| 86 | flash.c : Flash memory control files |
| 87 | ppcboot.lds : linker(ld) script? (I don't know this yet) |
| 88 | tqm8xx.c : DRAM control and board check routines |
| 89 | |
| 90 | And, add your board config lines in the |
| 91 | ppcboot-0.8.1/Makefile |
| 92 | |
| 93 | Finally, add config_(your board).h file in the |
| 94 | ppcboot-0.8.1/include/ |
| 95 | |
| 96 | I've made board/rpxlite directory, and just copied |
| 97 | tqm8xx settings for now. |
| 98 | |
| 99 | Rebuild ppcboot for rpxlite board: |
| 100 | > make rpxlite_config |
| 101 | > make |
| 102 | |
| 103 | ############################################################### |
| 104 | # 3. U-Boot porting |
| 105 | ############################################################### |
| 106 | |
| 107 | 3.1. My RPXlite files are based on tqm8xx board files. |
| 108 | > cd board |
| 109 | > cp -r tqm8xx RPXLITE |
| 110 | > cd RPXLITE |
| 111 | > mv tqm8xx.c RPXLITE.c |
| 112 | > cd ../../include |
| 113 | > cp config_tqm8xx.h config_RPXLITE.h |
| 114 | |
| 115 | 3.2. Modified files are: |
| 116 | board/RPXLITE/RPXLITE.c /* DRAM-related routines */ |
| 117 | board/RPXLITE/flash.c /* flash-related routines */ |
| 118 | board/RPXLITE/config.mk /* set text base address */ |
| 119 | cpu/mpc8xx/serial.c /* board specific register setting */ |
| 120 | include/config_RPXLITE.h /* board specific registers */ |
| 121 | |
| 122 | See 'reg_config.txt' for register values in detail. |
| 123 | |
| 124 | ############################################################### |
| 125 | # 4. Running Linux |
| 126 | ############################################################### |
| 127 | |
| 128 | |
| 129 | |
| 130 | |
| 131 | |
| 132 | |
| 133 | |
| 134 | |
| 135 | |
| 136 | ############################################################### |
| 137 | # Misc Information |
| 138 | ############################################################### |
| 139 | |
| 140 | mem_config.txt: |
| 141 | =============== |
| 142 | |
| 143 | Flash memory device : AM29LV800BB (1Mx8Bit) x 4 device |
| 144 | manufacturer id : 01 (AMD) |
| 145 | device id : 5B (AM29LV800B) |
| 146 | size : 4Mbyte |
| 147 | sector # : 19 |
| 148 | |
| 149 | Sector information : |
| 150 | |
| 151 | number start addr. size |
| 152 | 00 FFC0_0000 64 |
| 153 | 01 FFC1_0000 32 |
| 154 | 02 FFC1_8000 32 |
| 155 | 03 FFC2_0000 128 |
| 156 | 04 FFC4_0000 256 |
| 157 | 05 FFC8_0000 256 |
| 158 | 06 FFCC_0000 256 |
| 159 | 07 FFD0_0000 256 |
| 160 | 08 FFD4_0000 256 |
| 161 | 09 FFD8_0000 256 |
| 162 | 10 FFDC_0000 256 |
| 163 | 11 FFE0_0000 256 |
| 164 | 12 FFE4_0000 256 |
| 165 | 13 FFE8_0000 256 |
| 166 | 14 FFEC_0000 256 |
| 167 | 15 FFF0_0000 256 |
| 168 | 16 FFF4_0000 256 |
| 169 | 17 FFF8_0000 256 |
| 170 | 18 FFFC_0000 256 |
| 171 | |
| 172 | |
| 173 | reg_config.txt: |
| 174 | =============== |
| 175 | |
| 176 | |
| 177 | /*------------------------------------------------------------------- */ |
| 178 | /*------------------------------------------------------------------- */ |
| 179 | /* SIU (System Interface Unit) */ |
| 180 | /* */ |
| 181 | /*------------------------------------------------------------------- */ |
| 182 | /*------------------------------------------------------------------- */ |
| 183 | |
| 184 | |
| 185 | /*### IMMR */ |
| 186 | /*### Internal Memory Map Register */ |
| 187 | /*### Chap. 11.4.1 */ |
| 188 | |
| 189 | ISB = 0xFA20 /* Set the Immap base = 0xFA20 0000 */ |
| 190 | PARTNUM = 0x21 |
| 191 | MASKNUM = 0x00 |
| 192 | |
| 193 | => 0xFA20 2100 |
| 194 | |
| 195 | --------------------------------------------------------------------- |
| 196 | |
| 197 | /*### SIUMCR */ |
| 198 | /*### SIU Module Configuration Register */ |
| 199 | /*### Chap. 11.4.2 */ |
| 200 | /*### Offset : 0x0000 0000 */ |
| 201 | |
| 202 | EARB = 0 |
| 203 | EARP = 0 |
| 204 | DSHW = 0 |
| 205 | DBGC = 0 |
| 206 | DBPC = 0 |
| 207 | FRC = 0 |
| 208 | DLK = 0 |
| 209 | OPAR = 0 |
| 210 | PNCS = 0 |
| 211 | DPC = 0 |
| 212 | MPRE = 0 |
| 213 | MLRC = 10 /* ~KR/~RETRY/~IRQ4/SPKROUT functions as ~KR/~TRTRY */ |
| 214 | AEME = 0 |
| 215 | SEME = 0 |
| 216 | BSC = 0 |
| 217 | GB5E = 0 |
| 218 | B2DD = 0 |
| 219 | B3DD = 0 |
| 220 | |
| 221 | => 0x0000 0800 |
| 222 | |
| 223 | --------------------------------------------------------------------- |
| 224 | |
| 225 | /*### SYPCR */ |
| 226 | /*### System Protection Control Register */ |
| 227 | /*### Chap. 11.4.3 */ |
| 228 | /*### Offset : 0x0000 0004 */ |
| 229 | |
| 230 | SWTC = 0xFFFF /* SW watchdog timer count = 0xFFFF */ |
| 231 | BMT = 0x06 /* BUS monitoring timing */ |
| 232 | BME = 1 /* BUS monitor enable */ |
| 233 | SWF = 1 |
| 234 | SWE = 0 /* SW watchdog disable */ |
| 235 | SWRI = 0 |
| 236 | SWP = 1 |
| 237 | |
| 238 | => 0xFFFF 0689 |
| 239 | |
| 240 | --------------------------------------------------------------------- |
| 241 | |
| 242 | /*### TESR */ |
| 243 | /*### Transfer Error Status Register */ |
| 244 | /*### Chap. 11.4.4 */ |
| 245 | /*### Offset : 0x0000 0020 */ |
| 246 | |
| 247 | IEXT = 0 |
| 248 | ITMT = 0 |
| 249 | IPB = 0000 |
| 250 | DEXT = 0 |
| 251 | DTMT = 0 |
| 252 | DPB = 0000 |
| 253 | |
| 254 | => 0x0000 0000 |
| 255 | |
| 256 | --------------------------------------------------------------------- |
| 257 | |
| 258 | /*### SIPEND */ |
| 259 | /*### SIU Interrupt Pending Register */ |
| 260 | /*### Chap. 11.5.4.1 */ |
| 261 | /*### Offset : 0x0000 0010 */ |
| 262 | |
| 263 | IRQ0~IRQ7 = 0 |
| 264 | LVL0~LVL7 = 0 |
| 265 | |
| 266 | => 0x0000 0000 |
| 267 | |
| 268 | --------------------------------------------------------------------- |
| 269 | |
| 270 | /*### SIMASK */ |
| 271 | /*### SIU Interrupt Mask Register */ |
| 272 | /*### Chap. 11.5.4.2 */ |
| 273 | /*### Offset : 0x0000 0014 */ |
| 274 | |
| 275 | IRM0~IRM7 = 0 /* Mask all interrupts */ |
| 276 | LVL0~LVL7 = 0 |
| 277 | |
| 278 | => 0x0000 0000 |
| 279 | |
| 280 | --------------------------------------------------------------------- |
| 281 | |
| 282 | /*### SIEL */ |
| 283 | /*### SIU Interrupt Edge/Level Register */ |
| 284 | /*### Chap. 11.5.4.3 */ |
| 285 | /*### Offset : 0x0000 0018 */ |
| 286 | |
| 287 | ED0~ED7 = 0 /* Low level triggered */ |
| 288 | WMn0~WMn7 = 0 /* Not allowed to exit from low-power mode */ |
| 289 | |
| 290 | => 0x0000 0000 |
| 291 | |
| 292 | --------------------------------------------------------------------- |
| 293 | |
| 294 | /*### SIVEC */ |
| 295 | /*### SIU Interrupt Vector Register */ |
| 296 | /*### Chap. 11.5.4.4 */ |
| 297 | /*### Offset : 0x0000 001C */ |
| 298 | |
| 299 | INTC = 3C /* The lowest interrupt is pending..(?) */ |
| 300 | |
| 301 | => 0x3C00 0000 |
| 302 | |
| 303 | --------------------------------------------------------------------- |
| 304 | |
| 305 | /*### SWSR */ |
| 306 | /*### Software Service Register */ |
| 307 | /*### Chap. 11.7.1 */ |
| 308 | /*### Offset : 0x0000 001E */ |
| 309 | |
| 310 | SEQ = 0 |
| 311 | |
| 312 | => 0x0000 |
| 313 | |
| 314 | --------------------------------------------------------------------- |
| 315 | |
| 316 | /*### SDCR */ |
| 317 | /*### SDMA Configuration Register */ |
| 318 | /*### Chap. 20.2.1 */ |
| 319 | /*### Offset : 0x0000 0032 */ |
| 320 | |
| 321 | FRZ = 0 |
| 322 | RAID = 01 /* Priority level 5 (BR5) (normal operation) */ |
| 323 | |
| 324 | => 0x0000 0001 |
| 325 | |
| 326 | |
| 327 | /*------------------------------------------------------------------- */ |
| 328 | /*------------------------------------------------------------------- */ |
| 329 | /* UPMA (User Programmable Machine A) */ |
| 330 | /* */ |
| 331 | /*------------------------------------------------------------------- */ |
| 332 | /*------------------------------------------------------------------- */ |
| 333 | |
| 334 | /*### Chap. 16.6.4.1 */ |
| 335 | /*### Offset = 0x0000 017c */ |
| 336 | |
| 337 | T0 = CFFF CC24 /* Single Read */ |
| 338 | T1 = 0FFF CC04 |
| 339 | T2 = 0CAF CC04 |
| 340 | T3 = 03AF CC08 |
| 341 | T4 = 3FBF CC27 /* last */ |
| 342 | T5 = FFFF CC25 |
| 343 | T6 = FFFF CC25 |
| 344 | T7 = FFFF CC25 |
| 345 | T8 = CFFF CC24 /* Burst Read */ |
| 346 | T9 = 0FFF CC04 |
| 347 | T10 = 0CAF CC84 |
| 348 | T11 = 03AF CC88 |
| 349 | T12 = 3FBF CC27 /* last */ |
| 350 | T13 = FFFF CC25 |
| 351 | T14 = FFFF CC25 |
| 352 | T15 = FFFF CC25 |
| 353 | T16 = FFFF CC25 |
| 354 | T17 = FFFF CC25 |
| 355 | T18 = FFFF CC25 |
| 356 | T19 = FFFF CC25 |
| 357 | T20 = FFFF CC25 |
| 358 | T21 = FFFF CC25 |
| 359 | T22 = FFFF CC25 |
| 360 | T23 = FFFF CC25 |
| 361 | T24 = CFFF CC24 /* Single Write */ |
| 362 | T25 = 0FFF CC04 |
| 363 | T26 = 0CFF CC04 |
| 364 | T27 = 03FF CC00 |
| 365 | T28 = 3FFF CC27 /* last */ |
| 366 | T29 = FFFF CC25 |
| 367 | T30 = FFFF CC25 |
| 368 | T31 = FFFF CC25 |
| 369 | T32 = CFFF CC24 /* Burst Write */ |
| 370 | T33 = 0FFF CC04 |
| 371 | T34 = 0CFF CC80 |
| 372 | T35 = 03FF CC8C |
| 373 | T36 = 0CFF CC00 |
| 374 | T37 = 33FF CC27 /* last */ |
| 375 | T38 = FFFF CC25 |
| 376 | T39 = FFFF CC25 |
| 377 | T40 = FFFF CC25 |
| 378 | T41 = FFFF CC25 |
| 379 | T42 = FFFF CC25 |
| 380 | T43 = FFFF CC25 |
| 381 | T44 = FFFF CC25 |
| 382 | T45 = FFFF CC25 |
| 383 | T46 = FFFF CC25 |
| 384 | T47 = FFFF CC25 |
| 385 | T48 = C0FF CC24 /* Refresh */ |
| 386 | T49 = 03FF CC24 |
| 387 | T50 = 0FFF CC24 |
| 388 | T51 = 0FFF CC24 |
| 389 | T52 = 3FFF CC27 /* last */ |
| 390 | T53 = FFFF CC25 |
| 391 | T54 = FFFF CC25 |
| 392 | T55 = FFFF CC25 |
| 393 | T56 = FFFF CC25 |
| 394 | T57 = FFFF CC25 |
| 395 | T58 = FFFF CC25 |
| 396 | T59 = FFFF CC25 |
| 397 | T60 = FFFF CC25 /* Exception */ |
| 398 | T61 = FFFF CC25 |
| 399 | T62 = FFFF CC25 |
| 400 | T63 = FFFF CC25 |
| 401 | |
| 402 | |
| 403 | /*------------------------------------------------------------------- */ |
| 404 | /*------------------------------------------------------------------- */ |
| 405 | /* UPMB */ |
| 406 | /* */ |
| 407 | /*------------------------------------------------------------------- */ |
| 408 | /*------------------------------------------------------------------- */ |
| 409 | --------------------------------------------------------------------- |
| 410 | |
| 411 | /*### Chap. 16.6.4.1 */ |
| 412 | |
| 413 | |
| 414 | /*------------------------------------------------------------------- */ |
| 415 | /*------------------------------------------------------------------- */ |
| 416 | /* MEMC */ |
| 417 | /* */ |
| 418 | /*------------------------------------------------------------------- */ |
| 419 | /*------------------------------------------------------------------- */ |
| 420 | --------------------------------------------------------------------- |
| 421 | |
| 422 | /*### BR0 & OR0 */ |
| 423 | /*### Base Registers & Option Registers */ |
| 424 | /*### Chap. 16.4.1 & 16.4.2 */ |
| 425 | /*### Offset : BR0(0x0000 0100) & OR0(0x0000 0104) */ |
| 426 | /*### Flash memory */ |
| 427 | |
| 428 | BA = 1111 1110 0000 0000 0 /* Base addr = 0xFE00 0000 */ |
| 429 | AT = 000 |
| 430 | PS = 00 |
| 431 | PARE = 0 |
| 432 | WP = 0 |
| 433 | MS = 0 /* GPCM */ |
| 434 | V = 1 /* Valid */ |
| 435 | |
| 436 | => 0xFE00 0001 |
| 437 | |
| 438 | AM = 1111 1110 0000 0000 0 /* 32MBytes */ |
| 439 | ATM = 000 |
| 440 | CSNT/SAM = 0 |
| 441 | ACS/G5LA,G5LS = 00 |
| 442 | BIH = 1 /* Burst inhibited */ |
| 443 | SCY = 0100 /* cycle length = 4 */ |
| 444 | SETA = 0 |
| 445 | TRLX = 0 |
| 446 | EHTR = 0 |
| 447 | |
| 448 | => 0xFE00 0140 |
| 449 | |
| 450 | /*### BR1 & OR1 */ |
| 451 | /*### Base Registers & Option Registers */ |
| 452 | /*### Chap. 16.4.1 & 16.4.2 */ |
| 453 | /*### Offset : BR1(0x0000 0108) & OR1(0x0000 010C) */ |
| 454 | /*### SDRAM */ |
| 455 | |
| 456 | BA = 0000 0000 0000 0000 0 /* Base addr = 0x0000 0000 */ |
| 457 | AT = 000 |
| 458 | PS = 00 |
| 459 | PARE = 0 |
| 460 | WP = 0 |
| 461 | MS = 1 /* UPMA */ |
| 462 | V = 1 /* Valid */ |
| 463 | |
| 464 | => 0x0000 0081 |
| 465 | |
| 466 | AM = 1111 1110 0000 0000 /* 32MBytes */ |
| 467 | ATM = 000 |
| 468 | CSNT/SAM = 1 |
| 469 | ACS/G5LA,G5LS = 11 |
| 470 | BIH = 0 |
| 471 | SCY = 0000 /* cycle length = 0 */ |
| 472 | SETA = 0 |
| 473 | TRLX = 0 |
| 474 | EHTR = 0 |
| 475 | |
| 476 | => 0xFE00 0E00 |
| 477 | |
| 478 | /*### BR2 & OR2 */ |
| 479 | /*### Base Registers & Option Registers */ |
| 480 | /*### Chap. 16.4.1 & 16.4.2 */ |
| 481 | /*### Offset : BR2(0x0000 0110) & OR2(0x0000 0114) */ |
| 482 | |
| 483 | BR2 & OR2 = 0x0000 0000 /* Not used */ |
| 484 | |
| 485 | /*### BR3 & OR3 */ |
| 486 | /*### Base Registers & Option Registers */ |
| 487 | /*### Chap. 16.4.1 & 16.4.2 */ |
| 488 | /*### Offset : BR3(0x0000 0118) & OR3(0x0000 011C) */ |
| 489 | /*### BCSR */ |
| 490 | |
| 491 | BA = 1111 1010 0100 0000 0 /* Base addr = 0xFA40 0000 */ |
| 492 | AT = 000 |
| 493 | PS = 00 |
| 494 | PARE = 0 |
| 495 | WP = 0 |
| 496 | MS = 0 /* GPCM */ |
| 497 | V = 1 /* Valid */ |
| 498 | |
| 499 | => 0xFA40 0001 |
| 500 | |
| 501 | AM = 1111 1111 0111 1111 1 /* (?) */ |
| 502 | ATM = 000 |
| 503 | CSNT/SAM = 1 |
| 504 | ACS/G5LA,G5LS = 00 |
| 505 | BIH = 1 /* Burst inhibited */ |
| 506 | SCY = 0001 /* cycle length = 1 */ |
| 507 | SETA = 0 |
| 508 | TRLX = 0 |
| 509 | |
| 510 | => 0xFF7F 8910 |
| 511 | |
| 512 | /*### BR4 & OR4 */ |
| 513 | /*### Base Registers & Option Registers */ |
| 514 | /*### Chap. 16.4.1 & 16.4.2 */ |
| 515 | /*### Offset : BR4(0x0000 0120) & OR4(0x0000 0124) */ |
| 516 | /*### NVRAM & SRAM */ |
| 517 | |
| 518 | BA = 1111 1010 0000 0000 0 /* Base addr = 0xFA00 0000 */ |
| 519 | AT = 000 |
| 520 | PS = 01 |
| 521 | PARE = 0 |
| 522 | WP = 0 |
| 523 | MS = 0 /* GPCM */ |
| 524 | V = 1 /* Valid */ |
| 525 | |
| 526 | => 0xFA00 0401 |
| 527 | |
| 528 | AM = 1111 1111 1111 1000 0 /* 8MByte */ |
| 529 | ATM = 000 |
| 530 | CSNT/SAM = 1 |
| 531 | ACS/G5LA,G5LS = 00 |
| 532 | BIH = 1 /* Burst inhibited */ |
| 533 | SCY = 0111 /* cycle length = 7 */ |
| 534 | SETA = 0 |
| 535 | TRLX = 0 |
| 536 | |
| 537 | => 0xFFF8 0970 |
| 538 | |
| 539 | /*### BR5 & OR5 */ |
| 540 | /*### Base Registers & Option Registers */ |
| 541 | /*### Chap. 16.4.1 & 16.4.2 */ |
| 542 | /*### Offset : BR2(0x0000 0128) & OR2(0x0000 012C) */ |
| 543 | |
| 544 | BR5 & OR5 = 0x0000 0000 /* Not used */ |
| 545 | |
| 546 | /*### BR6 & OR6 */ |
| 547 | /*### Base Registers & Option Registers */ |
| 548 | /*### Chap. 16.4.1 & 16.4.2 */ |
| 549 | /*### Offset : BR2(0x0000 0130) & OR2(0x0000 0134) */ |
| 550 | |
| 551 | BR6 & OR6 = 0x0000 0000 /* Not used */ |
| 552 | |
| 553 | /*### BR7 & OR7 */ |
| 554 | /*### Base Registers & Option Registers */ |
| 555 | /*### Chap. 16.4.1 & 16.4.2 */ |
| 556 | /*### Offset : BR7(0x0000 0138) & OR7(0x0000 013C) */ |
| 557 | |
| 558 | BR7 & OR7 = 0x0000 0000 /* Not used */ |
| 559 | |
| 560 | /*### MAR */ |
| 561 | /*### Memory Address Register */ |
| 562 | /*### Chap. 16.4.7 */ |
| 563 | /*### Offset : 0x0000 0164 */ |
| 564 | |
| 565 | MA = External memory address |
| 566 | |
| 567 | /*### MCR */ |
| 568 | /*### Memory Command Register */ |
| 569 | /*### Chap. 16.4.5 */ |
| 570 | /*### Offset : 0x0000 0168 */ |
| 571 | |
| 572 | OP = xx /* Command op code */ |
| 573 | UM = 1 /* Select UPMA */ |
| 574 | MB = 001 /* Select CS1 */ |
| 575 | MCLF = xxxx /* Loop times */ |
| 576 | MAD = xx xxxx /* Memory array index */ |
| 577 | |
| 578 | /*### MAMR */ |
| 579 | /*### Machine A Mode Register */ |
| 580 | /*### Chap. 16.4.4 */ |
| 581 | /*### Offset : 0x0000 0170 */ |
| 582 | |
| 583 | PTA = 0101 1000 |
| 584 | PTAE = 1 /* Periodic timer A enabled */ |
| 585 | AMA = 010 |
| 586 | DSA = 00 |
| 587 | G0CLA = 000 |
| 588 | GPLA4DIS = 1 |
| 589 | RLFA = 0100 |
| 590 | WLFA = 0011 |
| 591 | TLFA = 0000 |
| 592 | |
| 593 | => 0x58A0 1430 |
| 594 | |
| 595 | /*### MBMR */ |
| 596 | /*### Machine B Mode Register */ |
| 597 | /*### Chap. 16.4.4 */ |
| 598 | /*### Offset : 0x0000 0174 */ |
| 599 | |
| 600 | PTA = 0100 1110 |
| 601 | PTAE = 0 /* Periodic timer B disabled */ |
| 602 | AMA = 000 |
| 603 | DSA = 00 |
| 604 | G0CLA = 000 |
| 605 | GPLA4DIS = 1 |
| 606 | RLFA = 0000 |
| 607 | WLFA = 0000 |
| 608 | TLFA = 0000 |
| 609 | |
| 610 | => 0x4E00 1000 |
| 611 | |
| 612 | /*### MSTAT */ |
| 613 | /*### Memory Status Register */ |
| 614 | /*### Chap. 16.4.3 */ |
| 615 | /*### Offset : 0x0000 0178 */ |
| 616 | |
| 617 | PER0~PER7 = Parity error |
| 618 | WPER = Write protection error |
| 619 | |
| 620 | => 0x0000 |
| 621 | |
| 622 | /*### MPTPR */ |
| 623 | /*### Memory Periodic Timer Prescaler Register */ |
| 624 | /*### Chap. 16.4.8 */ |
| 625 | /*### Offset : 0x0000 017A */ |
| 626 | |
| 627 | PTP = 0000 1000 /* Divide by 8 */ |
| 628 | |
| 629 | => 0x0800 |
| 630 | |
| 631 | /*### MDR */ |
| 632 | /*### Memory Data Register */ |
| 633 | /*### Chap. 16.4.6 */ |
| 634 | /*### Offset : 0x0000 017C */ |
| 635 | |
| 636 | MD = Memory data contains the RAM array word |
| 637 | |
| 638 | |
| 639 | /*------------------------------------------------------------------- */ |
| 640 | /*------------------------------------------------------------------- */ |
| 641 | /* TIMERS */ |
| 642 | /* */ |
| 643 | /*------------------------------------------------------------------- */ |
| 644 | /*------------------------------------------------------------------- */ |
| 645 | --------------------------------------------------------------------- |
| 646 | |
| 647 | /*### TBREFx */ |
| 648 | /*### Timebase Reference Registers */ |
| 649 | /*### Chap. 11.9.2 */ |
| 650 | /*### Offset : TBREFF0(0x0000 0204)/TBREFF1(0x0000 0208) */ |
| 651 | /*### (Locked) */ |
| 652 | |
| 653 | TBREFF0 = 0xFFFF FFFF |
| 654 | TBREFF1 = 0xFFFF FFFF |
| 655 | |
| 656 | --------------------------------------------------------------------- |
| 657 | |
| 658 | /*### TBSCR */ |
| 659 | /*### Timebase Status and Control Registers */ |
| 660 | /*### Chap. 11.9.3 */ |
| 661 | /*### Offset : 0x0000 0200 */ |
| 662 | /*### (Locked) */ |
| 663 | |
| 664 | TBIRQ = 00000000 |
| 665 | REF0 = 0 |
| 666 | REF1 = 0 |
| 667 | REFE0 = 0 /* Reference interrupt disable */ |
| 668 | REFE1 = 0 |
| 669 | TBF = 1 |
| 670 | TBE = 1 /* Timebase enable */ |
| 671 | |
| 672 | => 0x0003 |
| 673 | |
| 674 | --------------------------------------------------------------------- |
| 675 | |
| 676 | /*### RTCSC */ |
| 677 | /*### Real-Time Clock Status and Control Registers */ |
| 678 | /*### Chap. 11.10.1 */ |
| 679 | /*### Offset : 0x0000 0220 */ |
| 680 | /*### (Locked) */ |
| 681 | |
| 682 | RTCIRQ = 00000000 |
| 683 | SEC = 1 |
| 684 | ALR = 0 |
| 685 | 38K = 0 /* PITRTCLK is driven by 32.768KHz */ |
| 686 | SIE = 0 |
| 687 | ALE = 0 |
| 688 | RTF = 0 |
| 689 | RTE = 1 /* Real-Time clock enabled */ |
| 690 | |
| 691 | => 0x0081 |
| 692 | |
| 693 | --------------------------------------------------------------------- |
| 694 | |
| 695 | /*### RTC */ |
| 696 | /*### Real-Time Clock Registers */ |
| 697 | /*### Chap. 11.10.2 */ |
| 698 | /*### Offset : 0x0000 0224 */ |
| 699 | /*### (Locked) */ |
| 700 | |
| 701 | RTC = Real time clock measured in second |
| 702 | |
| 703 | --------------------------------------------------------------------- |
| 704 | |
| 705 | /*### RTCAL */ |
| 706 | /*### Real-Time Clock Alarm Registers */ |
| 707 | /*### Chap. 11.10.3 */ |
| 708 | /*### Offset : 0x0000 022C */ |
| 709 | /*### (Locked) */ |
| 710 | |
| 711 | ALARM = 0xFFFF FFFF |
| 712 | |
| 713 | --------------------------------------------------------------------- |
| 714 | |
| 715 | /*### RTSEC */ |
| 716 | /*### Real-Time Clock Alarm Second Registers */ |
| 717 | /*### Chap. 11.10.4 */ |
| 718 | /*### Offset : 0x0000 0228 */ |
| 719 | /*### (Locked) */ |
| 720 | |
| 721 | COUNTER = Counter bits(fraction of a second) |
| 722 | |
| 723 | --------------------------------------------------------------------- |
| 724 | |
| 725 | /*### PISCR */ |
| 726 | /*### Periodic Interrupt Status and Control Register */ |
| 727 | /*### Chap. 11.11.1 */ |
| 728 | /*### Offset : 0x0000 0240 */ |
| 729 | /*### (Locked) */ |
| 730 | |
| 731 | PIRQ = 0 |
| 732 | PS = 0 /* Write 1 to clear */ |
| 733 | PIE = 0 |
| 734 | PITF = 1 |
| 735 | PTE = 0 /* PIT disabled */ |
| 736 | |
| 737 | --------------------------------------------------------------------- |
| 738 | |
| 739 | /*### PITC */ |
| 740 | /*### PIT Count Register */ |
| 741 | /*### Chap. 11.11.2 */ |
| 742 | /*### Offset : 0x0000 0244 */ |
| 743 | /*### (Locked) */ |
| 744 | |
| 745 | PITC = PIT count |
| 746 | |
| 747 | --------------------------------------------------------------------- |
| 748 | |
| 749 | /*### PITR */ |
| 750 | /*### PIT Register */ |
| 751 | /*### Chap. 11.11.3 */ |
| 752 | /*### Offset : 0x0000 0248 */ |
| 753 | /*### (Locked) */ |
| 754 | |
| 755 | PIT = PIT count /* Read only */ |
| 756 | |
| 757 | |
| 758 | |
| 759 | /*------------------------------------------------------------------- */ |
| 760 | /*------------------------------------------------------------------- */ |
| 761 | /* CLOCKS */ |
| 762 | /* */ |
| 763 | /*------------------------------------------------------------------- */ |
| 764 | /*------------------------------------------------------------------- */ |
| 765 | --------------------------------------------------------------------- |
| 766 | |
| 767 | |
| 768 | --------------------------------------------------------------------- |
| 769 | |
| 770 | /*### SCCR */ |
| 771 | /*### System Clock and Reset Control Register */ |
| 772 | /*### Chap. 15.6.1 */ |
| 773 | /*### Offset : 0x0000 0280 */ |
| 774 | /*### (Locked) */ |
| 775 | |
| 776 | COM = 11 /* Clock output disabled */ |
| 777 | TBS = 1 /* Timebase frequency source is GCLK2 divided by 16 */ |
| 778 | RTDIV = 0 /* The clock is divided by 4 */ |
| 779 | RTSEL = 0 /* OSCM(Crystal oscillator) is selected */ |
| 780 | CRQEN = 0 |
| 781 | PRQEN = 0 |
| 782 | EBDF = 00 /* CLKOUT is GCLK2 divided by 1 */ |
| 783 | DFSYNC = 00 /* Divided by 1 (normal operation) */ |
| 784 | DFBRG = 00 /* Divided by 1 (normal operation) */ |
| 785 | DFNL = 000 |
| 786 | DFNH = 000 |
| 787 | |
| 788 | => 0x6200 0000 |
| 789 | |
| 790 | --------------------------------------------------------------------- |
| 791 | |
| 792 | /*### PLPRCR */ |
| 793 | /*### PLL, Low-Power, and Reset Control Register */ |
| 794 | /*### Chap. 15.6.2 */ |
| 795 | /*### Offset : 0x0000 0284 */ |
| 796 | /*### (Locked) */ |
| 797 | |
| 798 | MF = 0x005 /* 48MHz (?) ( = 8MHz * (MF+1) ) */ |
| 799 | SPLSS = 0 |
| 800 | TEXPS = 0 |
| 801 | TMIST = 0 |
| 802 | CSRC = 0 /* The general system clock is generated by the DFNH field */ |
| 803 | LPM = 00 /* Normal high/normal low mode */ |
| 804 | CSR = 0 |
| 805 | LOLRE = 0 |
| 806 | FIOPD = 0 |
| 807 | |
| 808 | => 0x0050 0000 |
| 809 | |
| 810 | --------------------------------------------------------------------- |
| 811 | |
| 812 | /*### RSR */ |
| 813 | /*### Reset Status Register */ |
| 814 | /*### Chap. 12.2 */ |
| 815 | /*### Offset : 0x0000 0288 */ |
| 816 | /*### (Locked) */ |
| 817 | |
| 818 | EHRS = External hard reset |
| 819 | ESRS = External soft reset |
| 820 | LLRS = Loss-of-lock reset |
| 821 | SWRS = Software watchdog reset |
| 822 | CSRS = Check stop reset |
| 823 | DBHRS = Debug port hard reset |
| 824 | DBSRS = Debug port soft reset |
| 825 | JTRS = JTAG reset |
| 826 | |
| 827 | |
| 828 | |
| 829 | /*------------------------------------------------------------------- */ |
| 830 | /*------------------------------------------------------------------- */ |
| 831 | /* DMA */ |
| 832 | /* */ |
| 833 | /*------------------------------------------------------------------- */ |
| 834 | /*------------------------------------------------------------------- */ |
| 835 | --------------------------------------------------------------------- |
| 836 | |
| 837 | /*### SDSR */ |
| 838 | /*### SDMA Status Register */ |
| 839 | /*### Chap. 20.2.2 */ |
| 840 | /*### Offset : 0x0000 0908 */ |
| 841 | |
| 842 | SBER = 0 /* SDMA channel bus error */ |
| 843 | DSP2 = 0 /* DSP chain2 (Tx) interrupt */ |
| 844 | DSP1 = 0 /* DSP chain1 (Rx) interrupt */ |
| 845 | |
| 846 | => 0x00 |
| 847 | |
| 848 | /*### SDMR */ |
| 849 | /*### SDMA Mask Register */ |
| 850 | /*### Chap. 20.2.3 */ |
| 851 | /*### Offset : 0x0000 090C */ |
| 852 | |
| 853 | SBER = 0 |
| 854 | DSP2 = 0 |
| 855 | DSP1 = 0 /* All interrupts are masked */ |
| 856 | |
| 857 | => 0x00 |
| 858 | |
| 859 | /*### SDAR */ |
| 860 | /*### SDMA Address Register */ |
| 861 | /*### Chap. 20.2.4 */ |
| 862 | /*### Offset : 0x0000 0904 */ |
| 863 | |
| 864 | AR = 0xxxxx xxxx /* current system address */ |
| 865 | |
| 866 | => 0xFA20 23AC |
| 867 | |
| 868 | /*### IDSRx */ |
| 869 | /*### IDMA Status Register */ |
| 870 | /*### Chap. 20.3.3.2 */ |
| 871 | /*### Offset : IDSR1(0x0000 0910) & IDSR2(0x0000 0918) */ |
| 872 | |
| 873 | AD = 0 |
| 874 | DONE = 0 |
| 875 | OB = 0 |
| 876 | |
| 877 | => 0x00 |
| 878 | |
| 879 | /*### IDMRx */ |
| 880 | /*### IDMA Mask Register */ |
| 881 | /*### Chap. 20.3.3.3 */ |
| 882 | /*### Offset : IDMR1(0x0000 0914) & IDMR2(0x0000 091C) */ |
| 883 | |
| 884 | AD = 0 |
| 885 | DONE = 0 |
| 886 | OB = 0 |
| 887 | |