blob: 85b61f1f4bbe5e2d284f7876656ab7d91382d7c7 [file] [log] [blame]
Dirk Eibacha605ea72010-10-21 10:50:05 +02001/*
2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <command.h>
26#include <asm/processor.h>
27#include <asm/io.h>
28#include <asm/ppc4xx-gpio.h>
29
Dirk Eibachb19bf832012-04-26 03:54:23 +000030#include <dtt.h>
Dirk Eibacha605ea72010-10-21 10:50:05 +020031#include <miiphy.h>
32
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000033#include "405ep.h"
Dirk Eibach2da0fc02011-01-21 09:31:21 +010034#include <gdsys_fpga.h>
Dirk Eibacha605ea72010-10-21 10:50:05 +020035
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000036#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
37#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
38#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
39
Dirk Eibacha605ea72010-10-21 10:50:05 +020040#define PHYREG_CONTROL 0
41#define PHYREG_PAGE_ADDRESS 22
42#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
43#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
44
45enum {
Dirk Eibacha605ea72010-10-21 10:50:05 +020046 UNITTYPE_CCD_SWITCH = 1,
47};
48
49enum {
50 HWVER_100 = 0,
51 HWVER_110 = 1,
52 HWVER_121 = 2,
53 HWVER_122 = 3,
54};
55
Dirk Eibachb19bf832012-04-26 03:54:23 +000056int misc_init_r(void)
57{
58 /* startup fans */
59 dtt_init();
60
61 return 0;
62}
63
Dirk Eibacha605ea72010-10-21 10:50:05 +020064int configure_gbit_phy(unsigned char addr)
65{
66 unsigned short value;
67
68 /* select page 2 */
69 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
70 PHYREG_PAGE_ADDRESS, 0x0002))
71 goto err_out;
72 /* disable SGMII autonegotiation */
73 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
74 PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
75 goto err_out;
76 /* select page 0 */
77 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
78 PHYREG_PAGE_ADDRESS, 0x0000))
79 goto err_out;
80 /* switch from powerdown to normal operation */
81 if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
82 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
83 goto err_out;
84 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
85 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
86 goto err_out;
87 /* reset phy so settings take effect */
88 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
89 PHYREG_CONTROL, 0x9140))
90 goto err_out;
91
92 return 0;
93
94err_out:
95 printf("Error writing to the PHY addr=%02x\n", addr);
96 return -1;
97}
98
99/*
100 * Check Board Identity:
101 */
102int checkboard(void)
103{
Dirk Eibachb19bf832012-04-26 03:54:23 +0000104 char *s = getenv("serial#");
105
106 puts("Board: CATCenter Io");
107
108 if (s != NULL) {
109 puts(", serial# ");
110 puts(s);
111 }
112
113 puts("\n");
114
115 return 0;
116}
117
118static void print_fpga_info(void)
119{
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100120 ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100121 u16 versions = in_le16(&fpga->versions);
122 u16 fpga_version = in_le16(&fpga->fpga_version);
123 u16 fpga_features = in_le16(&fpga->fpga_features);
Dirk Eibacha605ea72010-10-21 10:50:05 +0200124 unsigned unit_type;
125 unsigned hardware_version;
126 unsigned feature_channels;
127 unsigned feature_expansion;
128
129 unit_type = (versions & 0xf000) >> 12;
130 hardware_version = versions & 0x000f;
131 feature_channels = fpga_features & 0x007f;
132 feature_expansion = fpga_features & (1<<15);
133
Dirk Eibachb19bf832012-04-26 03:54:23 +0000134 puts("FPGA: ");
Dirk Eibacha605ea72010-10-21 10:50:05 +0200135
136 switch (unit_type) {
137 case UNITTYPE_CCD_SWITCH:
138 printf("CCD-Switch");
139 break;
140
141 default:
142 printf("UnitType %d(not supported)", unit_type);
143 break;
144 }
145
146 switch (hardware_version) {
147 case HWVER_100:
148 printf(" HW-Ver 1.00\n");
149 break;
150
151 case HWVER_110:
152 printf(" HW-Ver 1.10\n");
153 break;
154
155 case HWVER_121:
156 printf(" HW-Ver 1.21\n");
157 break;
158
159 case HWVER_122:
160 printf(" HW-Ver 1.22\n");
161 break;
162
163 default:
164 printf(" HW-Ver %d(not supported)\n",
165 hardware_version);
166 break;
167 }
168
169 printf(" FPGA V %d.%02d, features:",
170 fpga_version / 100, fpga_version % 100);
171
172 printf(" %d channel(s)", feature_channels);
173
174 printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
Dirk Eibacha605ea72010-10-21 10:50:05 +0200175}
176
177/*
178 * setup Gbit PHYs
179 */
180int last_stage_init(void)
181{
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100182 ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
Dirk Eibacha605ea72010-10-21 10:50:05 +0200183 unsigned int k;
184
Dirk Eibachb19bf832012-04-26 03:54:23 +0000185 print_fpga_info();
186
Dirk Eibacha605ea72010-10-21 10:50:05 +0200187 miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
188 bb_miiphy_read, bb_miiphy_write);
189
190 for (k = 0; k < 32; ++k)
191 configure_gbit_phy(k);
192
193 /* take fpga serdes blocks out of reset */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100194 out_le16(&fpga->quad_serdes_reset, 0);
Dirk Eibacha605ea72010-10-21 10:50:05 +0200195
196 return 0;
197}
Dirk Eibach6e9e6c32012-04-26 03:54:22 +0000198
199void gd405ep_init(void)
200{
201}
202
203void gd405ep_set_fpga_reset(unsigned state)
204{
205 if (state) {
206 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
207 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
208 } else {
209 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
210 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
211 }
212}
213
214void gd405ep_setup_hw(void)
215{
216 /*
217 * set "startup-finished"-gpios
218 */
219 gpio_write_bit(21, 0);
220 gpio_write_bit(22, 1);
221}
222
223int gd405ep_get_fpga_done(unsigned fpga)
224{
225 return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
226}