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Kuo-Jung Suc4775472013-05-07 14:33:31 +08001/*
2 * Faraday 10/100Mbps Ethernet Controller
3 *
4 * (C) Copyright 2010 Faraday Technology
5 * Dante Su <dantesu@faraday-tech.com>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Kuo-Jung Suc4775472013-05-07 14:33:31 +08008 */
9
10#ifndef _FTMAC110_H
11#define _FTMAC110_H
12
13struct ftmac110_regs {
14 uint32_t isr; /* 0x00: Interrups Status Register */
15 uint32_t imr; /* 0x04: Interrupt Mask Register */
16 uint32_t mac[2]; /* 0x08: MAC Address */
17 uint32_t mht[2]; /* 0x10: Multicast Hash Table Register */
18 uint32_t txpd; /* 0x18: Tx Poll Demand Register */
19 uint32_t rxpd; /* 0x1c: Rx Poll Demand Register */
20 uint32_t txba; /* 0x20: Tx Ring Base Address Register */
21 uint32_t rxba; /* 0x24: Rx Ring Base Address Register */
22 uint32_t itc; /* 0x28: Interrupt Timer Control Register */
23 uint32_t aptc; /* 0x2C: Automatic Polling Timer Control Register */
24 uint32_t dblac; /* 0x30: DMA Burst Length&Arbitration Control */
25 uint32_t revr; /* 0x34: Revision Register */
26 uint32_t fear; /* 0x38: Feature Register */
27 uint32_t rsvd[19];
28 uint32_t maccr; /* 0x88: MAC Control Register */
29 uint32_t macsr; /* 0x8C: MAC Status Register */
30 uint32_t phycr; /* 0x90: PHY Control Register */
31 uint32_t phydr; /* 0x94: PHY Data Register */
32 uint32_t fcr; /* 0x98: Flow Control Register */
33 uint32_t bpr; /* 0x9C: Back Pressure Register */
34};
35
36/*
37 * Interrupt status/mask register(ISR/IMR) bits
38 */
39#define ISR_ALL 0x3ff
40#define ISR_PHYSTCHG (1 << 9) /* phy status change */
41#define ISR_AHBERR (1 << 8) /* bus error */
42#define ISR_RXLOST (1 << 7) /* rx lost */
43#define ISR_RXFIFO (1 << 6) /* rx to fifo */
44#define ISR_TXLOST (1 << 5) /* tx lost */
45#define ISR_TXOK (1 << 4) /* tx to ethernet */
46#define ISR_NOTXBUF (1 << 3) /* out of tx buffer */
47#define ISR_TXFIFO (1 << 2) /* tx to fifo */
48#define ISR_NORXBUF (1 << 1) /* out of rx buffer */
49#define ISR_RXOK (1 << 0) /* rx to buffer */
50
51/*
52 * MACCR control bits
53 */
54#define MACCR_100M (1 << 18) /* 100Mbps mode */
55#define MACCR_RXBCST (1 << 17) /* rx broadcast packet */
56#define MACCR_RXMCST (1 << 16) /* rx multicast packet */
57#define MACCR_FD (1 << 15) /* full duplex */
58#define MACCR_CRCAPD (1 << 14) /* tx crc append */
59#define MACCR_RXALL (1 << 12) /* rx all packets */
60#define MACCR_RXFTL (1 << 11) /* rx packet even it's > 1518 byte */
61#define MACCR_RXRUNT (1 << 10) /* rx packet even it's < 64 byte */
62#define MACCR_RXMCSTHT (1 << 9) /* rx multicast hash table */
63#define MACCR_RXEN (1 << 8) /* rx enable */
64#define MACCR_RXINHDTX (1 << 6) /* rx in half duplex tx */
65#define MACCR_TXEN (1 << 5) /* tx enable */
66#define MACCR_CRCDIS (1 << 4) /* tx packet even it's crc error */
67#define MACCR_LOOPBACK (1 << 3) /* loop-back */
68#define MACCR_RESET (1 << 2) /* reset */
69#define MACCR_RXDMAEN (1 << 1) /* rx dma enable */
70#define MACCR_TXDMAEN (1 << 0) /* tx dma enable */
71
72/*
73 * PHYCR control bits
74 */
75#define PHYCR_READ (1 << 26)
76#define PHYCR_WRITE (1 << 27)
77#define PHYCR_REG_SHIFT 21
78#define PHYCR_ADDR_SHIFT 16
79
80/*
81 * ITC control bits
82 */
83
84/* Tx Cycle Length */
85#define ITC_TX_CYCLONG (1 << 15) /* 100Mbps=81.92us; 10Mbps=819.2us */
86#define ITC_TX_CYCNORM (0 << 15) /* 100Mbps=5.12us; 10Mbps=51.2us */
87/* Tx Threshold: Aggregate n interrupts as 1 interrupt */
88#define ITC_TX_THR(n) (((n) & 0x7) << 12)
89/* Tx Interrupt Timeout = n * Tx Cycle */
90#define ITC_TX_ITMO(n) (((n) & 0xf) << 8)
91/* Rx Cycle Length */
92#define ITC_RX_CYCLONG (1 << 7) /* 100Mbps=81.92us; 10Mbps=819.2us */
93#define ITC_RX_CYCNORM (0 << 7) /* 100Mbps=5.12us; 10Mbps=51.2us */
94/* Rx Threshold: Aggregate n interrupts as 1 interrupt */
95#define ITC_RX_THR(n) (((n) & 0x7) << 4)
96/* Rx Interrupt Timeout = n * Rx Cycle */
97#define ITC_RX_ITMO(n) (((n) & 0xf) << 0)
98
99#define ITC_DEFAULT \
100 (ITC_TX_THR(1) | ITC_TX_ITMO(0) | ITC_RX_THR(1) | ITC_RX_ITMO(0))
101
102/*
103 * APTC contrl bits
104 */
105
106/* Tx Cycle Length */
107#define APTC_TX_CYCLONG (1 << 12) /* 100Mbps=81.92us; 10Mbps=819.2us */
108#define APTC_TX_CYCNORM (0 << 12) /* 100Mbps=5.12us; 10Mbps=51.2us */
109/* Tx Poll Timeout = n * Tx Cycle, 0=No auto polling */
110#define APTC_TX_PTMO(n) (((n) & 0xf) << 8)
111/* Rx Cycle Length */
112#define APTC_RX_CYCLONG (1 << 4) /* 100Mbps=81.92us; 10Mbps=819.2us */
113#define APTC_RX_CYCNORM (0 << 4) /* 100Mbps=5.12us; 10Mbps=51.2us */
114/* Rx Poll Timeout = n * Rx Cycle, 0=No auto polling */
115#define APTC_RX_PTMO(n) (((n) & 0xf) << 0)
116
117#define APTC_DEFAULT (APTC_TX_PTMO(0) | APTC_RX_PTMO(1))
118
119/*
120 * DBLAC contrl bits
121 */
122#define DBLAC_BURST_MAX_ANY (0 << 14) /* un-limited */
123#define DBLAC_BURST_MAX_32X4 (2 << 14) /* max = 32 x 4 bytes */
124#define DBLAC_BURST_MAX_64X4 (3 << 14) /* max = 64 x 4 bytes */
125#define DBLAC_RXTHR_EN (1 << 9) /* enable rx threshold arbitration */
126#define DBLAC_RXTHR_HIGH(n) (((n) & 0x7) << 6) /* upper bound = n/8 fifo */
127#define DBLAC_RXTHR_LOW(n) (((n) & 0x7) << 3) /* lower bound = n/8 fifo */
128#define DBLAC_BURST_CAP16 (1 << 2) /* support burst 16 */
129#define DBLAC_BURST_CAP8 (1 << 1) /* support burst 8 */
130#define DBLAC_BURST_CAP4 (1 << 0) /* support burst 4 */
131
132#define DBLAC_DEFAULT \
133 (DBLAC_RXTHR_EN | DBLAC_RXTHR_HIGH(6) | DBLAC_RXTHR_LOW(2))
134
135/*
136 * descriptor structure
137 */
138struct ftmac110_rxd {
139 uint32_t ct[2];
140 uint32_t buf;
141 void *vbuf; /* reserved */
142};
143
144#define FTMAC110_RXCT0_OWNER BIT_MASK(31) /* owner: 1=HW, 0=SW */
145#define FTMAC110_RXCT0_FRS BIT_MASK(29) /* first pkt desc */
146#define FTMAC110_RXCT0_LRS BIT_MASK(28) /* last pkt desc */
147#define FTMAC110_RXCT0_ODDNB BIT_MASK(22) /* odd nibble */
148#define FTMAC110_RXCT0_RUNT BIT_MASK(21) /* runt pkt */
149#define FTMAC110_RXCT0_FTL BIT_MASK(20) /* frame too long */
150#define FTMAC110_RXCT0_CRC BIT_MASK(19) /* pkt crc error */
151#define FTMAC110_RXCT0_ERR BIT_MASK(18) /* bus error */
152#define FTMAC110_RXCT0_ERRMASK (0x1f << 18) /* all errors */
153#define FTMAC110_RXCT0_BCST BIT_MASK(17) /* Bcst pkt */
154#define FTMAC110_RXCT0_MCST BIT_MASK(16) /* Mcst pkt */
155#define FTMAC110_RXCT0_LEN(x) ((x) & 0x7ff)
156
157#define FTMAC110_RXCT1_END BIT_MASK(31)
158#define FTMAC110_RXCT1_BUFSZ(x) ((x) & 0x7ff)
159
160struct ftmac110_txd {
161 uint32_t ct[2];
162 uint32_t buf;
163 void *vbuf; /* reserved */
164};
165
166#define FTMAC110_TXCT0_OWNER BIT_MASK(31) /* owner: 1=HW, 0=SW */
167#define FTMAC110_TXCT0_COL 0x00000003 /* collision */
168
169#define FTMAC110_TXCT1_END BIT_MASK(31) /* end of ring */
170#define FTMAC110_TXCT1_TXIC BIT_MASK(30) /* tx done interrupt */
171#define FTMAC110_TXCT1_TX2FIC BIT_MASK(29) /* tx fifo interrupt */
172#define FTMAC110_TXCT1_FTS BIT_MASK(28) /* first pkt desc */
173#define FTMAC110_TXCT1_LTS BIT_MASK(27) /* last pkt desc */
174#define FTMAC110_TXCT1_LEN(x) ((x) & 0x7ff)
175
176#endif /* FTMAC110_H */