Luka Kovacic | 22bb913 | 2019-05-07 19:35:55 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2015 Stefan Roese <sr@denx.de> |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <i2c.h> |
Simon Glass | 691d719 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 8 | #include <init.h> |
Simon Glass | 401d1c4 | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 9 | #include <asm/global_data.h> |
Luka Kovacic | 22bb913 | 2019-05-07 19:35:55 +0200 | [diff] [blame] | 10 | #include <asm/gpio.h> |
Simon Glass | cd93d62 | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 11 | #include <linux/bitops.h> |
Luka Kovacic | 22bb913 | 2019-05-07 19:35:55 +0200 | [diff] [blame] | 12 | #include <linux/mbus.h> |
| 13 | #include <linux/io.h> |
| 14 | #include <asm/arch/cpu.h> |
| 15 | #include <asm/arch/soc.h> |
| 16 | |
| 17 | DECLARE_GLOBAL_DATA_PTR; |
| 18 | |
| 19 | /* |
| 20 | * These values and defines are taken from the Marvell U-Boot version |
| 21 | * "u-boot-2013.01-2016_T1.0.eng_drop_v6" |
| 22 | */ |
| 23 | #define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) | BIT(4) \ |
| 24 | | BIT(6) | BIT(12) | BIT(13) \ |
| 25 | | BIT(16) | BIT(17) | BIT(20) \ |
| 26 | | BIT(29) | BIT(30))) |
| 27 | #define DB_DX_AC3_GPP_OUT_ENA_MID (~(0)) |
| 28 | #define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4) \ |
| 29 | | BIT(6) | BIT(12) | BIT(13) \ |
| 30 | | BIT(16) | BIT(17) | BIT(20) \ |
| 31 | | BIT(29) | BIT(30)) |
| 32 | #define DB_DX_AC3_GPP_OUT_VAL_MID 0x0 |
| 33 | #define DB_DX_AC3_GPP_POL_LOW 0x0 |
| 34 | #define DB_DX_AC3_GPP_POL_MID 0x0 |
| 35 | |
| 36 | int board_early_init_f(void) |
| 37 | { |
| 38 | /* Configure MPP */ |
| 39 | writel(0x00142222, MVEBU_MPP_BASE + 0x00); |
| 40 | writel(0x11122000, MVEBU_MPP_BASE + 0x04); |
| 41 | writel(0x44444004, MVEBU_MPP_BASE + 0x08); |
| 42 | writel(0x14444444, MVEBU_MPP_BASE + 0x0c); |
| 43 | writel(0x00000001, MVEBU_MPP_BASE + 0x10); |
| 44 | |
| 45 | /* |
| 46 | * MVEBU_GPIO0_BASE is the User LED |
| 47 | * MVEBU_GPIO1_BASE is the Reset Button (currently not used) |
| 48 | */ |
| 49 | |
| 50 | /* Set GPP Out value */ |
| 51 | writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); |
| 52 | /* writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); */ |
| 53 | |
| 54 | /* Set GPP Polarity */ |
| 55 | writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); |
| 56 | /* writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); */ |
| 57 | |
| 58 | /* Set GPP Out Enable */ |
| 59 | writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); |
| 60 | /* writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); */ |
| 61 | |
| 62 | return 0; |
| 63 | } |
| 64 | |
| 65 | int board_init(void) |
| 66 | { |
| 67 | /* address of boot parameters */ |
| 68 | gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; |
| 69 | |
| 70 | return 0; |
| 71 | } |
| 72 | |
| 73 | int checkboard(void) |
| 74 | { |
| 75 | puts("Board: " CONFIG_SYS_BOARD "\n"); |
| 76 | |
| 77 | return 0; |
| 78 | } |