blob: 0274027096fda0951ddfe38599baecee089a0d35 [file] [log] [blame]
wdenk3d3befa2004-03-14 15:06:13 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8 *
9 * (C) Copyright 2003
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
12 *
13 * (C) Copyright 2004
14 * ARM Ltd.
15 * Philippe Robin, <philippe.robin@arm.com>
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35
36#include <common.h>
37
38void flash__init (void);
39void ether__init (void);
40void peripheral_power_enable (void);
41
42#if defined(CONFIG_SHOW_BOOT_PROGRESS)
43void show_boot_progress(int progress)
44{
45 printf("Boot reached stage %d\n", progress);
46}
47#endif
48
49#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
50
51static inline void delay (unsigned long loops)
52{
53 __asm__ volatile ("1:\n"
54 "subs %0, %1, #1\n"
55 "bne 1b":"=r" (loops):"0" (loops));
56}
57
58/*
59 * Miscellaneous platform dependent initialisations
60 */
61
62int board_init (void)
63{
64 DECLARE_GLOBAL_DATA_PTR;
65
66
67 /*
68 * set clock frequency:
69 * VERSATILE_REFCLK is 32KHz
70 * VERSATILE_TIMCLK is 1MHz
71 */
72 *(volatile unsigned int *)(VERSATILE_SCTL_BASE) |=
73 ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
74 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel));
75
76 /* arch number of Versatile Board */
wdenk731215e2004-10-10 18:41:04 +000077 gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB;
wdenk3d3befa2004-03-14 15:06:13 +000078
79 /* adress of boot parameters */
80 gd->bd->bi_boot_params = 0x00000100;
81
wdenkbc54f302004-07-11 18:10:30 +000082 gd->flags = 0;
83
wdenk3d3befa2004-03-14 15:06:13 +000084 icache_enable ();
85
86 flash__init ();
87 ether__init ();
88 return 0;
89}
90
91
92int misc_init_r (void)
93{
94 setenv("verify", "n");
95 return (0);
96}
97
98/******************************
99 Routine:
100 Description:
101******************************/
102void flash__init (void)
103{
104}
105/*************************************************************
106 Routine:ether__init
107 Description: take the Ethernet controller out of reset and wait
108 for the EEPROM load to complete.
109*************************************************************/
110void ether__init (void)
111{
112}
113
114/******************************
115 Routine:
116 Description:
117******************************/
118int dram_init (void)
119{
120 return 0;
121}