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wdenk5da627a2003-10-09 20:09:04 +00001/*
2 * (C) Copyright 2003
3 * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
4 *
5 * (C) Copyright 2002
6 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 *
26 */
27
28#include <common.h> /* core U-Boot definitions */
29#include <ACEX1K.h> /* ACEX device family */
30
31#if (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K))
32
33/* Define FPGA_DEBUG to get debug printf's */
wdenk5da627a2003-10-09 20:09:04 +000034#ifdef FPGA_DEBUG
35#define PRINTF(fmt,args...) printf (fmt ,##args)
36#else
37#define PRINTF(fmt,args...)
38#endif
39
wdenk5da627a2003-10-09 20:09:04 +000040/* Note: The assumption is that we cannot possibly run fast enough to
41 * overrun the device (the Slave Parallel mode can free run at 50MHz).
42 * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
43 * the board config file to slow things down.
44 */
45#ifndef CONFIG_FPGA_DELAY
46#define CONFIG_FPGA_DELAY()
47#endif
48
49#ifndef CFG_FPGA_WAIT
wdenk11dadd52004-02-27 00:07:27 +000050#define CFG_FPGA_WAIT CFG_HZ/10 /* 100 ms */
wdenk5da627a2003-10-09 20:09:04 +000051#endif
52
53static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize );
54static int ACEX1K_ps_dump( Altera_desc *desc, void *buf, size_t bsize );
55/* static int ACEX1K_ps_info( Altera_desc *desc ); */
56static int ACEX1K_ps_reloc( Altera_desc *desc, ulong reloc_offset );
57
58/* ------------------------------------------------------------------------- */
59/* ACEX1K Generic Implementation */
60int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize)
61{
62 int ret_val = FPGA_FAIL;
63
64 switch (desc->iface) {
65 case passive_serial:
66 PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__);
67 ret_val = ACEX1K_ps_load (desc, buf, bsize);
68 break;
69
70 /* Add new interface types here */
71
72 default:
73 printf ("%s: Unsupported interface type, %d\n",
74 __FUNCTION__, desc->iface);
75 }
76
77 return ret_val;
78}
79
80int ACEX1K_dump (Altera_desc * desc, void *buf, size_t bsize)
81{
82 int ret_val = FPGA_FAIL;
83
84 switch (desc->iface) {
85 case passive_serial:
86 PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__);
87 ret_val = ACEX1K_ps_dump (desc, buf, bsize);
88 break;
89
90 /* Add new interface types here */
91
92 default:
93 printf ("%s: Unsupported interface type, %d\n",
94 __FUNCTION__, desc->iface);
95 }
96
97 return ret_val;
98}
99
100int ACEX1K_info( Altera_desc *desc )
101{
102 return FPGA_SUCCESS;
103}
104
105
106int ACEX1K_reloc (Altera_desc * desc, ulong reloc_offset)
107{
108 int ret_val = FPGA_FAIL; /* assume a failure */
109
110 if (desc->family != Altera_ACEX1K) {
111 printf ("%s: Unsupported family type, %d\n",
112 __FUNCTION__, desc->family);
113 return FPGA_FAIL;
114 } else
115 switch (desc->iface) {
116 case passive_serial:
117 ret_val = ACEX1K_ps_reloc (desc, reloc_offset);
118 break;
119
120 /* Add new interface types here */
121
122 default:
123 printf ("%s: Unsupported interface type, %d\n",
124 __FUNCTION__, desc->iface);
125 }
126
127 return ret_val;
128}
129
130
131/* ------------------------------------------------------------------------- */
132/* ACEX1K Passive Serial Generic Implementation */
133
134static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize)
135{
136 int ret_val = FPGA_FAIL; /* assume the worst */
137 Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns;
138 int i;
139
140 PRINTF ("%s: start with interface functions @ 0x%p\n",
141 __FUNCTION__, fn);
142
143 if (fn) {
144 size_t bytecount = 0;
145 unsigned char *data = (unsigned char *) buf;
146 int cookie = desc->cookie; /* make a local copy */
147 unsigned long ts; /* timestamp */
148
149 PRINTF ("%s: Function Table:\n"
150 "ptr:\t0x%p\n"
151 "struct: 0x%p\n"
152 "config:\t0x%p\n"
153 "status:\t0x%p\n"
154 "clk:\t0x%p\n"
155 "data:\t0x%p\n"
156 "done:\t0x%p\n\n",
157 __FUNCTION__, &fn, fn, fn->config, fn->status,
158 fn->clk, fn->data, fn->done);
159#ifdef CFG_FPGA_PROG_FEEDBACK
wdenk11dadd52004-02-27 00:07:27 +0000160 printf ("Loading FPGA Device %d...", cookie);
wdenk5da627a2003-10-09 20:09:04 +0000161#endif
162
163 /*
164 * Run the pre configuration function if there is one.
165 */
166 if (*fn->pre) {
167 (*fn->pre) (cookie);
168 }
169
170 /* Establish the initial state */
171 (*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */
172
173 udelay(2); /* T_cfg > 2us */
174
175 /* nSTATUS should be asserted now */
176 (*fn->done) (cookie);
177 if ( !(*fn->status) (cookie) ) {
178 puts ("** nSTATUS is not asserted.\n");
179 (*fn->abort) (cookie);
180 return FPGA_FAIL;
181 }
182
183 (*fn->config) (FALSE, TRUE, cookie); /* Deassert nCONFIG */
184 udelay(2); /* T_cf2st1 < 4us */
185
186 /* Wait for nSTATUS to be released (i.e. deasserted) */
187 ts = get_timer (0); /* get current time */
188 do {
189 CONFIG_FPGA_DELAY ();
190 if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
191 puts ("** Timeout waiting for STATUS to go high.\n");
192 (*fn->abort) (cookie);
193 return FPGA_FAIL;
194 }
195 (*fn->done) (cookie);
196 } while ((*fn->status) (cookie));
197
198 /* Get ready for the burn */
199 CONFIG_FPGA_DELAY ();
200
201 /* Load the data */
202 while (bytecount < bsize) {
203 unsigned char val=0;
204#ifdef CFG_FPGA_CHECK_CTRLC
205 if (ctrlc ()) {
206 (*fn->abort) (cookie);
207 return FPGA_FAIL;
208 }
209#endif
210 /* Altera detects an error if INIT goes low (active)
211 while DONE is low (inactive) */
212#if 0 /* not yet implemented */
213 if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
214 puts ("** CRC error during FPGA load.\n");
215 (*fn->abort) (cookie);
216 return (FPGA_FAIL);
217 }
218#endif
219 val = data [bytecount ++ ];
220 i = 8;
221 do {
222 /* Deassert the clock */
223 (*fn->clk) (FALSE, TRUE, cookie);
224 CONFIG_FPGA_DELAY ();
225 /* Write data */
226 (*fn->data) ( (val & 0x01), TRUE, cookie);
227 CONFIG_FPGA_DELAY ();
228 /* Assert the clock */
229 (*fn->clk) (TRUE, TRUE, cookie);
230 CONFIG_FPGA_DELAY ();
231 val >>= 1;
232 i --;
233 } while (i > 0);
234
235#ifdef CFG_FPGA_PROG_FEEDBACK
236 if (bytecount % (bsize / 40) == 0)
237 putc ('.'); /* let them know we are alive */
238#endif
239 }
240
241 CONFIG_FPGA_DELAY ();
242
243#ifdef CFG_FPGA_PROG_FEEDBACK
wdenk11dadd52004-02-27 00:07:27 +0000244 putc (' '); /* terminate the dotted line */
wdenk5da627a2003-10-09 20:09:04 +0000245#endif
246
247 /*
248 * Checking FPGA's CONF_DONE signal - correctly booted ?
249 */
250
251 if ( ! (*fn->done) (cookie) ) {
252 puts ("** Booting failed! CONF_DONE is still deasserted.\n");
253 (*fn->abort) (cookie);
254 return (FPGA_FAIL);
255 }
256
257 /*
258 * "DCLK must be clocked an additional 10 times fpr ACEX 1K..."
259 */
260
261 for (i = 0; i < 12; i++) {
262 CONFIG_FPGA_DELAY ();
263 (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
264 CONFIG_FPGA_DELAY ();
265 (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
266 }
267
268 ret_val = FPGA_SUCCESS;
269
270#ifdef CFG_FPGA_PROG_FEEDBACK
271 if (ret_val == FPGA_SUCCESS) {
272 puts ("Done.\n");
273 }
274 else {
275 puts ("Fail.\n");
276 }
277#endif
278 (*fn->post) (cookie);
279
280 } else {
281 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
282 }
283
284 return ret_val;
285}
286
287static int ACEX1K_ps_dump (Altera_desc * desc, void *buf, size_t bsize)
288{
289 /* Readback is only available through the Slave Parallel and */
290 /* boundary-scan interfaces. */
291 printf ("%s: Passive Serial Dumping is unavailable\n",
292 __FUNCTION__);
293 return FPGA_FAIL;
294}
295
296static int ACEX1K_ps_reloc (Altera_desc * desc, ulong reloc_offset)
297{
298 int ret_val = FPGA_FAIL; /* assume the worst */
299 Altera_ACEX1K_Passive_Serial_fns *fn_r, *fn =
300 (Altera_ACEX1K_Passive_Serial_fns *) (desc->iface_fns);
301
302 if (fn) {
303 ulong addr;
304
305 /* Get the relocated table address */
306 addr = (ulong) fn + reloc_offset;
307 fn_r = (Altera_ACEX1K_Passive_Serial_fns *) addr;
308
309 if (!fn_r->relocated) {
310
311 if (memcmp (fn_r, fn,
312 sizeof (Altera_ACEX1K_Passive_Serial_fns))
313 == 0) {
314 /* good copy of the table, fix the descriptor pointer */
315 desc->iface_fns = fn_r;
316 } else {
317 PRINTF ("%s: Invalid function table at 0x%p\n",
318 __FUNCTION__, fn_r);
319 return FPGA_FAIL;
320 }
321
322 PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
323 desc);
324
325 addr = (ulong) (fn->pre) + reloc_offset;
326 fn_r->pre = (Altera_pre_fn) addr;
327
328 addr = (ulong) (fn->config) + reloc_offset;
329 fn_r->config = (Altera_config_fn) addr;
330
331 addr = (ulong) (fn->status) + reloc_offset;
332 fn_r->status = (Altera_status_fn) addr;
333
334 addr = (ulong) (fn->done) + reloc_offset;
335 fn_r->done = (Altera_done_fn) addr;
336
337 addr = (ulong) (fn->clk) + reloc_offset;
338 fn_r->clk = (Altera_clk_fn) addr;
339
340 addr = (ulong) (fn->data) + reloc_offset;
341 fn_r->data = (Altera_data_fn) addr;
342
343 addr = (ulong) (fn->abort) + reloc_offset;
344 fn_r->abort = (Altera_abort_fn) addr;
345
346 addr = (ulong) (fn->post) + reloc_offset;
347 fn_r->post = (Altera_post_fn) addr;
348
349 fn_r->relocated = TRUE;
350
351 } else {
352 /* this table has already been moved */
353 /* XXX - should check to see if the descriptor is correct */
354 desc->iface_fns = fn_r;
355 }
356
357 ret_val = FPGA_SUCCESS;
358 } else {
359 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
360 }
361
362 return ret_val;
363
364}
365
366#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K)) */