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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2002
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
25#include <common.h> /* core U-Boot definitions */
26#include <spartan2.h> /* Spartan-II device family */
27
28#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN2))
29
30/* Define FPGA_DEBUG to get debug printf's */
31#ifdef FPGA_DEBUG
32#define PRINTF(fmt,args...) printf (fmt ,##args)
33#else
34#define PRINTF(fmt,args...)
35#endif
36
37#undef CFG_FPGA_CHECK_BUSY
wdenk7f6c2cb2002-11-10 22:06:23 +000038#undef CFG_FPGA_PROG_FEEDBACK
wdenke2211742002-11-02 23:30:20 +000039
40/* Note: The assumption is that we cannot possibly run fast enough to
41 * overrun the device (the Slave Parallel mode can free run at 50MHz).
42 * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
43 * the board config file to slow things down.
44 */
45#ifndef CONFIG_FPGA_DELAY
46#define CONFIG_FPGA_DELAY()
47#endif
48
49#ifndef CFG_FPGA_WAIT
50#define CFG_FPGA_WAIT 10
51#endif
52
53static int Spartan2_sp_load( Xilinx_desc *desc, void *buf, size_t bsize );
54static int Spartan2_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize );
55/* static int Spartan2_sp_info( Xilinx_desc *desc ); */
56static int Spartan2_sp_reloc( Xilinx_desc *desc, ulong reloc_offset );
57
58static int Spartan2_ss_load( Xilinx_desc *desc, void *buf, size_t bsize );
59static int Spartan2_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize );
60/* static int Spartan2_ss_info( Xilinx_desc *desc ); */
61static int Spartan2_ss_reloc( Xilinx_desc *desc, ulong reloc_offset );
62
63/* ------------------------------------------------------------------------- */
64/* Spartan-II Generic Implementation */
65int Spartan2_load (Xilinx_desc * desc, void *buf, size_t bsize)
66{
67 int ret_val = FPGA_FAIL;
68
69 switch (desc->iface) {
70 case slave_serial:
71 PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
72 ret_val = Spartan2_ss_load (desc, buf, bsize);
73 break;
74
75 case slave_parallel:
76 PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
77 ret_val = Spartan2_sp_load (desc, buf, bsize);
78 break;
79
80 default:
81 printf ("%s: Unsupported interface type, %d\n",
82 __FUNCTION__, desc->iface);
83 }
84
85 return ret_val;
86}
87
88int Spartan2_dump (Xilinx_desc * desc, void *buf, size_t bsize)
89{
90 int ret_val = FPGA_FAIL;
91
92 switch (desc->iface) {
93 case slave_serial:
94 PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
95 ret_val = Spartan2_ss_dump (desc, buf, bsize);
96 break;
97
98 case slave_parallel:
99 PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
100 ret_val = Spartan2_sp_dump (desc, buf, bsize);
101 break;
102
103 default:
104 printf ("%s: Unsupported interface type, %d\n",
105 __FUNCTION__, desc->iface);
106 }
107
108 return ret_val;
109}
110
111int Spartan2_info( Xilinx_desc *desc )
112{
113 return FPGA_SUCCESS;
114}
115
116
117int Spartan2_reloc (Xilinx_desc * desc, ulong reloc_offset)
118{
119 int ret_val = FPGA_FAIL; /* assume a failure */
120
121 if (desc->family != Xilinx_Spartan2) {
122 printf ("%s: Unsupported family type, %d\n",
123 __FUNCTION__, desc->family);
124 return FPGA_FAIL;
125 } else
126 switch (desc->iface) {
127 case slave_serial:
128 ret_val = Spartan2_ss_reloc (desc, reloc_offset);
129 break;
130
131 case slave_parallel:
132 ret_val = Spartan2_sp_reloc (desc, reloc_offset);
133 break;
134
135 default:
136 printf ("%s: Unsupported interface type, %d\n",
137 __FUNCTION__, desc->iface);
138 }
139
140 return ret_val;
141}
142
143
144/* ------------------------------------------------------------------------- */
145/* Spartan-II Slave Parallel Generic Implementation */
146
147static int Spartan2_sp_load (Xilinx_desc * desc, void *buf, size_t bsize)
148{
149 int ret_val = FPGA_FAIL; /* assume the worst */
150 Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns;
151
152 PRINTF ("%s: start with interface functions @ 0x%p\n",
153 __FUNCTION__, fn);
154
155 if (fn) {
156 size_t bytecount = 0;
157 unsigned char *data = (unsigned char *) buf;
158 int cookie = desc->cookie; /* make a local copy */
159 unsigned long ts; /* timestamp */
160
161 PRINTF ("%s: Function Table:\n"
162 "ptr:\t0x%p\n"
163 "struct: 0x%p\n"
164 "pre: 0x%p\n"
165 "pgm:\t0x%p\n"
166 "init:\t0x%p\n"
167 "err:\t0x%p\n"
168 "clk:\t0x%p\n"
169 "cs:\t0x%p\n"
170 "wr:\t0x%p\n"
171 "read data:\t0x%p\n"
172 "write data:\t0x%p\n"
173 "busy:\t0x%p\n"
174 "abort:\t0x%p\n",
175 "post:\t0x%p\n\n",
176 __FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
177 fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
178 fn->abort, fn->post);
179
180 /*
181 * This code is designed to emulate the "Express Style"
182 * Continuous Data Loading in Slave Parallel Mode for
183 * the Spartan-II Family.
184 */
185#ifdef CFG_FPGA_PROG_FEEDBACK
186 printf ("Loading FPGA Device %d...\n", cookie);
187#endif
188 /*
189 * Run the pre configuration function if there is one.
190 */
191 if (*fn->pre) {
192 (*fn->pre) (cookie);
193 }
194
195 /* Establish the initial state */
196 (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
197
198 /* Get ready for the burn */
199 CONFIG_FPGA_DELAY ();
200 (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
201
202 ts = get_timer (0); /* get current time */
203 /* Now wait for INIT and BUSY to go high */
204 do {
205 CONFIG_FPGA_DELAY ();
206 if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
207 puts ("** Timeout waiting for INIT to clear.\n");
208 (*fn->abort) (cookie); /* abort the burn */
209 return FPGA_FAIL;
210 }
211 } while ((*fn->init) (cookie) && (*fn->busy) (cookie));
212
213 (*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */
214 (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
215 (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
216
217 /* Load the data */
218 while (bytecount < bsize) {
219 /* XXX - do we check for an Ctrl-C press in here ??? */
220 /* XXX - Check the error bit? */
221
222 (*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */
223 CONFIG_FPGA_DELAY ();
224 (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
225 CONFIG_FPGA_DELAY ();
226 (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
227
228#ifdef CFG_FPGA_CHECK_BUSY
229 ts = get_timer (0); /* get current time */
230 while ((*fn->busy) (cookie)) {
231 /* XXX - we should have a check in here somewhere to
232 * make sure we aren't busy forever... */
233
234 CONFIG_FPGA_DELAY ();
235 (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
236 CONFIG_FPGA_DELAY ();
237 (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
238
239 if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
240 puts ("** Timeout waiting for BUSY to clear.\n");
241 (*fn->abort) (cookie); /* abort the burn */
242 return FPGA_FAIL;
243 }
244 }
245#endif
246
247#ifdef CFG_FPGA_PROG_FEEDBACK
248 if (bytecount % (bsize / 40) == 0)
249 putc ('.'); /* let them know we are alive */
250#endif
251 }
252
253 CONFIG_FPGA_DELAY ();
254 (*fn->cs) (FALSE, TRUE, cookie); /* Deassert the chip select */
255 (*fn->wr) (FALSE, TRUE, cookie); /* Deassert the write pin */
256
257#ifdef CFG_FPGA_PROG_FEEDBACK
258 putc ('\n'); /* terminate the dotted line */
259#endif
260
261 /* now check for done signal */
262 ts = get_timer (0); /* get current time */
263 ret_val = FPGA_SUCCESS;
264 while ((*fn->done) (cookie) == FPGA_FAIL) {
265 /* XXX - we should have a check in here somewhere to
266 * make sure we aren't busy forever... */
267
268 CONFIG_FPGA_DELAY ();
269 (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
270 CONFIG_FPGA_DELAY ();
271 (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
272
273 if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
274 puts ("** Timeout waiting for DONE to clear.\n");
275 (*fn->abort) (cookie); /* abort the burn */
276 ret_val = FPGA_FAIL;
277 break;
278 }
279 }
280
281 if (ret_val == FPGA_SUCCESS) {
282#ifdef CFG_FPGA_PROG_FEEDBACK
283 puts ("Done.\n");
284#endif
285 }
286 /*
287 * Run the post configuration function if there is one.
288 */
289 if (*fn->post) {
290 (*fn->post) (cookie);
291 }
292
293 else {
294#ifdef CFG_FPGA_PROG_FEEDBACK
295 puts ("Fail.\n");
296#endif
297 }
298
299 } else {
300 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
301 }
302
303 return ret_val;
304}
305
306static int Spartan2_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize)
307{
308 int ret_val = FPGA_FAIL; /* assume the worst */
309 Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns;
310
311 if (fn) {
312 unsigned char *data = (unsigned char *) buf;
313 size_t bytecount = 0;
314 int cookie = desc->cookie; /* make a local copy */
315
316 printf ("Starting Dump of FPGA Device %d...\n", cookie);
317
318 (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
319 (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
320
321 /* dump the data */
322 while (bytecount < bsize) {
323 /* XXX - do we check for an Ctrl-C press in here ??? */
324
325 (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
326 (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
327 (*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */
328#ifdef CFG_FPGA_PROG_FEEDBACK
329 if (bytecount % (bsize / 40) == 0)
330 putc ('.'); /* let them know we are alive */
331#endif
332 }
333
334 (*fn->cs) (FALSE, FALSE, cookie); /* Deassert the chip select */
335 (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
336 (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
337
338#ifdef CFG_FPGA_PROG_FEEDBACK
339 putc ('\n'); /* terminate the dotted line */
340#endif
341 puts ("Done.\n");
342
343 /* XXX - checksum the data? */
344 } else {
345 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
346 }
347
348 return ret_val;
349}
350
351
352static int Spartan2_sp_reloc (Xilinx_desc * desc, ulong reloc_offset)
353{
354 int ret_val = FPGA_FAIL; /* assume the worst */
355 Xilinx_Spartan2_Slave_Parallel_fns *fn_r, *fn =
356 (Xilinx_Spartan2_Slave_Parallel_fns *) (desc->iface_fns);
357
358 if (fn) {
359 ulong addr;
360
361 /* Get the relocated table address */
362 addr = (ulong) fn + reloc_offset;
363 fn_r = (Xilinx_Spartan2_Slave_Parallel_fns *) addr;
364
365 if (!fn_r->relocated) {
366
367 if (memcmp (fn_r, fn,
368 sizeof (Xilinx_Spartan2_Slave_Parallel_fns))
369 == 0) {
370 /* good copy of the table, fix the descriptor pointer */
371 desc->iface_fns = fn_r;
372 } else {
373 PRINTF ("%s: Invalid function table at 0x%p\n",
374 __FUNCTION__, fn_r);
375 return FPGA_FAIL;
376 }
377
378 PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
379 desc);
380
381 addr = (ulong) (fn->pre) + reloc_offset;
382 fn_r->pre = (Xilinx_pre_fn) addr;
383
384 addr = (ulong) (fn->pgm) + reloc_offset;
385 fn_r->pgm = (Xilinx_pgm_fn) addr;
386
387 addr = (ulong) (fn->init) + reloc_offset;
388 fn_r->init = (Xilinx_init_fn) addr;
389
390 addr = (ulong) (fn->done) + reloc_offset;
391 fn_r->done = (Xilinx_done_fn) addr;
392
393 addr = (ulong) (fn->clk) + reloc_offset;
394 fn_r->clk = (Xilinx_clk_fn) addr;
395
396 addr = (ulong) (fn->err) + reloc_offset;
397 fn_r->err = (Xilinx_err_fn) addr;
398
399 addr = (ulong) (fn->cs) + reloc_offset;
400 fn_r->cs = (Xilinx_cs_fn) addr;
401
402 addr = (ulong) (fn->wr) + reloc_offset;
403 fn_r->wr = (Xilinx_wr_fn) addr;
404
405 addr = (ulong) (fn->rdata) + reloc_offset;
406 fn_r->rdata = (Xilinx_rdata_fn) addr;
407
408 addr = (ulong) (fn->wdata) + reloc_offset;
409 fn_r->wdata = (Xilinx_wdata_fn) addr;
410
411 addr = (ulong) (fn->busy) + reloc_offset;
412 fn_r->busy = (Xilinx_busy_fn) addr;
413
414 addr = (ulong) (fn->abort) + reloc_offset;
415 fn_r->abort = (Xilinx_abort_fn) addr;
416
417 addr = (ulong) (fn->post) + reloc_offset;
418 fn_r->post = (Xilinx_post_fn) addr;
419
420 fn_r->relocated = TRUE;
421
422 } else {
423 /* this table has already been moved */
424 /* XXX - should check to see if the descriptor is correct */
425 desc->iface_fns = fn_r;
426 }
427
428 ret_val = FPGA_SUCCESS;
429 } else {
430 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
431 }
432
433 return ret_val;
434
435}
436
437/* ------------------------------------------------------------------------- */
438
439static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
440{
wdenk8bde7f72003-06-27 21:31:46 +0000441 int ret_val = FPGA_FAIL; /* assume the worst */
wdenk7f6c2cb2002-11-10 22:06:23 +0000442 Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns;
wdenk8bde7f72003-06-27 21:31:46 +0000443 int i;
444 char val;
445
wdenk7f6c2cb2002-11-10 22:06:23 +0000446 PRINTF ("%s: start with interface functions @ 0x%p\n",
447 __FUNCTION__, fn);
448
449 if (fn) {
450 size_t bytecount = 0;
451 unsigned char *data = (unsigned char *) buf;
452 int cookie = desc->cookie; /* make a local copy */
453 unsigned long ts; /* timestamp */
454
455 PRINTF ("%s: Function Table:\n"
456 "ptr:\t0x%p\n"
457 "struct: 0x%p\n"
458 "pgm:\t0x%p\n"
459 "init:\t0x%p\n"
460 "clk:\t0x%p\n"
461 "wr:\t0x%p\n"
462 "done:\t0x%p\n\n",
wdenk8bde7f72003-06-27 21:31:46 +0000463 __FUNCTION__, &fn, fn, fn->pgm, fn->init,
464 fn->clk, fn->wr, fn->done);
wdenk7f6c2cb2002-11-10 22:06:23 +0000465#ifdef CFG_FPGA_PROG_FEEDBACK
466 printf ("Loading FPGA Device %d...\n", cookie);
467#endif
468
469 /*
470 * Run the pre configuration function if there is one.
471 */
472 if (*fn->pre) {
473 (*fn->pre) (cookie);
474 }
475
476 /* Establish the initial state */
477 (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
478
wdenk8bde7f72003-06-27 21:31:46 +0000479 /* Wait for INIT state (init low) */
wdenk7f6c2cb2002-11-10 22:06:23 +0000480 ts = get_timer (0); /* get current time */
481 do {
482 CONFIG_FPGA_DELAY ();
483 if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
484 puts ("** Timeout waiting for INIT to start.\n");
485 return FPGA_FAIL;
486 }
487 } while (!(*fn->init) (cookie));
wdenk8bde7f72003-06-27 21:31:46 +0000488
wdenk7f6c2cb2002-11-10 22:06:23 +0000489 /* Get ready for the burn */
490 CONFIG_FPGA_DELAY ();
491 (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
492
493 ts = get_timer (0); /* get current time */
494 /* Now wait for INIT to go high */
495 do {
496 CONFIG_FPGA_DELAY ();
497 if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
498 puts ("** Timeout waiting for INIT to clear.\n");
499 return FPGA_FAIL;
500 }
501 } while ((*fn->init) (cookie));
502
503 /* Load the data */
504 while (bytecount < bsize) {
wdenk8bde7f72003-06-27 21:31:46 +0000505
506 /* Xilinx detects an error if INIT goes low (active)
507 while DONE is low (inactive) */
508 if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
509 puts ("** CRC error during FPGA load.\n");
510 return (FPGA_FAIL);
511 }
512 val = data [bytecount ++];
513 i = 8;
514 do {
515 /* Deassert the clock */
516 (*fn->clk) (FALSE, TRUE, cookie);
517 CONFIG_FPGA_DELAY ();
518 /* Write data */
519 (*fn->wr) ((val < 0), TRUE, cookie);
520 CONFIG_FPGA_DELAY ();
521 /* Assert the clock */
522 (*fn->clk) (TRUE, TRUE, cookie);
523 CONFIG_FPGA_DELAY ();
524 val <<= 1;
525 i --;
526 } while (i > 0);
527
wdenk7f6c2cb2002-11-10 22:06:23 +0000528#ifdef CFG_FPGA_PROG_FEEDBACK
529 if (bytecount % (bsize / 40) == 0)
530 putc ('.'); /* let them know we are alive */
531#endif
532 }
533
534 CONFIG_FPGA_DELAY ();
535
536#ifdef CFG_FPGA_PROG_FEEDBACK
537 putc ('\n'); /* terminate the dotted line */
538#endif
539
540 /* now check for done signal */
541 ts = get_timer (0); /* get current time */
542 ret_val = FPGA_SUCCESS;
wdenk8bde7f72003-06-27 21:31:46 +0000543 (*fn->wr) (TRUE, TRUE, cookie);
wdenk7f6c2cb2002-11-10 22:06:23 +0000544
545 while (! (*fn->done) (cookie)) {
546 /* XXX - we should have a check in here somewhere to
547 * make sure we aren't busy forever... */
548
549 CONFIG_FPGA_DELAY ();
550 (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
551 CONFIG_FPGA_DELAY ();
552 (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
553
wdenk8bde7f72003-06-27 21:31:46 +0000554 putc ('*');
555
wdenk7f6c2cb2002-11-10 22:06:23 +0000556 if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
557 puts ("** Timeout waiting for DONE to clear.\n");
558 ret_val = FPGA_FAIL;
559 break;
560 }
561 }
562 putc ('\n'); /* terminate the dotted line */
563
564#ifdef CFG_FPGA_PROG_FEEDBACK
565 if (ret_val == FPGA_SUCCESS) {
566 puts ("Done.\n");
567 }
568 else {
569 puts ("Fail.\n");
570 }
571#endif
572
573 } else {
574 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
575 }
576
577 return ret_val;
wdenke2211742002-11-02 23:30:20 +0000578}
579
580static int Spartan2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
581{
wdenk8bde7f72003-06-27 21:31:46 +0000582 /* Readback is only available through the Slave Parallel and */
583 /* boundary-scan interfaces. */
wdenk7f6c2cb2002-11-10 22:06:23 +0000584 printf ("%s: Slave Serial Dumping is unavailable\n",
wdenke2211742002-11-02 23:30:20 +0000585 __FUNCTION__);
586 return FPGA_FAIL;
587}
588
589static int Spartan2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
590{
591 int ret_val = FPGA_FAIL; /* assume the worst */
wdenk7f6c2cb2002-11-10 22:06:23 +0000592 Xilinx_Spartan2_Slave_Serial_fns *fn_r, *fn =
wdenke2211742002-11-02 23:30:20 +0000593 (Xilinx_Spartan2_Slave_Serial_fns *) (desc->iface_fns);
594
595 if (fn) {
wdenk7f6c2cb2002-11-10 22:06:23 +0000596 ulong addr;
597
598 /* Get the relocated table address */
599 addr = (ulong) fn + reloc_offset;
600 fn_r = (Xilinx_Spartan2_Slave_Serial_fns *) addr;
601
602 if (!fn_r->relocated) {
603
604 if (memcmp (fn_r, fn,
605 sizeof (Xilinx_Spartan2_Slave_Serial_fns))
606 == 0) {
607 /* good copy of the table, fix the descriptor pointer */
608 desc->iface_fns = fn_r;
609 } else {
610 PRINTF ("%s: Invalid function table at 0x%p\n",
611 __FUNCTION__, fn_r);
612 return FPGA_FAIL;
613 }
614
615 PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
616 desc);
617
618 addr = (ulong) (fn->pre) + reloc_offset;
619 fn_r->pre = (Xilinx_pre_fn) addr;
620
621 addr = (ulong) (fn->pgm) + reloc_offset;
622 fn_r->pgm = (Xilinx_pgm_fn) addr;
623
624 addr = (ulong) (fn->init) + reloc_offset;
625 fn_r->init = (Xilinx_init_fn) addr;
626
627 addr = (ulong) (fn->done) + reloc_offset;
628 fn_r->done = (Xilinx_done_fn) addr;
629
630 addr = (ulong) (fn->clk) + reloc_offset;
631 fn_r->clk = (Xilinx_clk_fn) addr;
632
633 addr = (ulong) (fn->wr) + reloc_offset;
634 fn_r->wr = (Xilinx_wr_fn) addr;
635
636 fn_r->relocated = TRUE;
637
638 } else {
639 /* this table has already been moved */
640 /* XXX - should check to see if the descriptor is correct */
641 desc->iface_fns = fn_r;
642 }
643
644 ret_val = FPGA_SUCCESS;
wdenke2211742002-11-02 23:30:20 +0000645 } else {
646 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
647 }
648
649 return ret_val;
650
651}
652
653#endif