| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame^] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/pci/toshiba,visconti-pcie.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Toshiba Visconti5 SoC PCIe Host Controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> |
| 11 | |
| 12 | description: |
| 13 | Toshiba Visconti5 SoC PCIe host controller is based on the Synopsys DesignWare PCIe IP. |
| 14 | |
| 15 | allOf: |
| 16 | - $ref: /schemas/pci/snps,dw-pcie.yaml# |
| 17 | |
| 18 | properties: |
| 19 | compatible: |
| 20 | const: toshiba,visconti-pcie |
| 21 | |
| 22 | reg: |
| 23 | items: |
| 24 | - description: Data Bus Interface (DBI) registers. |
| 25 | - description: PCIe configuration space region. |
| 26 | - description: Visconti specific additional registers. |
| 27 | - description: Visconti specific SMU registers |
| 28 | - description: Visconti specific memory protection unit registers (MPU) |
| 29 | |
| 30 | reg-names: |
| 31 | items: |
| 32 | - const: dbi |
| 33 | - const: config |
| 34 | - const: ulreg |
| 35 | - const: smu |
| 36 | - const: mpu |
| 37 | |
| 38 | interrupts: |
| 39 | maxItems: 2 |
| 40 | |
| 41 | clocks: |
| 42 | items: |
| 43 | - description: PCIe reference clock |
| 44 | - description: PCIe system clock |
| 45 | - description: Auxiliary clock |
| 46 | |
| 47 | clock-names: |
| 48 | items: |
| 49 | - const: ref |
| 50 | - const: core |
| 51 | - const: aux |
| 52 | |
| 53 | num-lanes: |
| 54 | const: 2 |
| 55 | |
| 56 | required: |
| 57 | - reg |
| 58 | - reg-names |
| 59 | - interrupts |
| 60 | - "#interrupt-cells" |
| 61 | - interrupt-map |
| 62 | - interrupt-map-mask |
| 63 | - num-lanes |
| 64 | - clocks |
| 65 | - clock-names |
| 66 | - max-link-speed |
| 67 | |
| 68 | unevaluatedProperties: false |
| 69 | |
| 70 | examples: |
| 71 | - | |
| 72 | #include <dt-bindings/interrupt-controller/irq.h> |
| 73 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 74 | |
| 75 | soc { |
| 76 | #address-cells = <2>; |
| 77 | #size-cells = <2>; |
| 78 | |
| 79 | pcie: pcie@28400000 { |
| 80 | compatible = "toshiba,visconti-pcie"; |
| 81 | reg = <0x0 0x28400000 0x0 0x00400000>, |
| 82 | <0x0 0x70000000 0x0 0x10000000>, |
| 83 | <0x0 0x28050000 0x0 0x00010000>, |
| 84 | <0x0 0x24200000 0x0 0x00002000>, |
| 85 | <0x0 0x24162000 0x0 0x00001000>; |
| 86 | reg-names = "dbi", "config", "ulreg", "smu", "mpu"; |
| 87 | device_type = "pci"; |
| 88 | bus-range = <0x00 0xff>; |
| 89 | num-lanes = <2>; |
| 90 | num-viewport = <8>; |
| 91 | |
| 92 | #address-cells = <3>; |
| 93 | #size-cells = <2>; |
| 94 | #interrupt-cells = <1>; |
| 95 | ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000>, |
| 96 | <0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>; |
| 97 | interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, |
| 98 | <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; |
| 99 | interrupt-names = "msi", "intr"; |
| 100 | interrupt-map-mask = <0 0 0 7>; |
| 101 | interrupt-map = |
| 102 | <0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH |
| 103 | 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH |
| 104 | 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH |
| 105 | 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; |
| 106 | clocks = <&extclk100mhz>, <&clk600mhz>, <&clk25mhz>; |
| 107 | clock-names = "ref", "core", "aux"; |
| 108 | max-link-speed = <2>; |
| 109 | }; |
| 110 | }; |
| 111 | ... |