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wdenk2abbe072003-06-16 23:50:08 +00001/*
2 * (C) Copyright 2003
3 * Author : Hamid Ikdoumi (Atmel)
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <at91rm9200_net.h>
25#include <net.h>
Marian Balakowicz63ff0042005-10-28 22:30:33 +020026#include <miiphy.h>
wdenk2abbe072003-06-16 23:50:08 +000027
28/* ----- Ethernet Buffer definitions ----- */
29
30typedef struct {
31 unsigned long addr, size;
32} rbf_t;
33
34#define RBF_ADDR 0xfffffffc
35#define RBF_OWNER (1<<0)
36#define RBF_WRAP (1<<1)
37#define RBF_BROADCAST (1<<31)
38#define RBF_MULTICAST (1<<30)
39#define RBF_UNICAST (1<<29)
40#define RBF_EXTERNAL (1<<28)
41#define RBF_UNKOWN (1<<27)
42#define RBF_SIZE 0x07ff
43#define RBF_LOCAL4 (1<<26)
44#define RBF_LOCAL3 (1<<25)
45#define RBF_LOCAL2 (1<<24)
46#define RBF_LOCAL1 (1<<23)
47
Wolfgang Denk95f9dda2005-10-09 00:33:37 +020048#define RBF_FRAMEMAX 64
wdenk2abbe072003-06-16 23:50:08 +000049#define RBF_FRAMELEN 0x600
50
wdenk2abbe072003-06-16 23:50:08 +000051#ifdef CONFIG_DRIVER_ETHER
52
Jon Loeliger3a1ed1e2007-07-09 18:57:22 -050053#if defined(CONFIG_CMD_NET)
wdenk2abbe072003-06-16 23:50:08 +000054
Wolfgang Denk95f9dda2005-10-09 00:33:37 +020055/* alignment as per Errata #11 (64 bytes) is insufficient! */
56rbf_t rbfdt[RBF_FRAMEMAX] __attribute((aligned(512)));
57rbf_t *rbfp;
58
59unsigned char rbf_framebuf[RBF_FRAMEMAX][RBF_FRAMELEN] __attribute((aligned(4)));
60
wdenk2abbe072003-06-16 23:50:08 +000061/* structure to interface the PHY */
wdenk429168e2004-08-02 23:39:03 +000062AT91S_PhyOps PhyOps;
wdenk2abbe072003-06-16 23:50:08 +000063
64AT91PS_EMAC p_mac;
65
wdenk2abbe072003-06-16 23:50:08 +000066/*********** EMAC Phy layer Management functions *************************/
67/*
wdenk8bde7f72003-06-27 21:31:46 +000068 * Name:
wdenk2abbe072003-06-16 23:50:08 +000069 * at91rm9200_EmacEnableMDIO
wdenk8bde7f72003-06-27 21:31:46 +000070 * Description:
wdenk2abbe072003-06-16 23:50:08 +000071 * Enables the MDIO bit in MAC control register
wdenk8bde7f72003-06-27 21:31:46 +000072 * Arguments:
wdenk2abbe072003-06-16 23:50:08 +000073 * p_mac - pointer to struct AT91S_EMAC
wdenk8bde7f72003-06-27 21:31:46 +000074 * Return value:
wdenk2abbe072003-06-16 23:50:08 +000075 * none
76 */
wdenk429168e2004-08-02 23:39:03 +000077void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
wdenk2abbe072003-06-16 23:50:08 +000078{
79 /* Mac CTRL reg set for MDIO enable */
80 p_mac->EMAC_CTL |= AT91C_EMAC_MPE; /* Management port enable */
81}
82
83/*
wdenk8bde7f72003-06-27 21:31:46 +000084 * Name:
wdenk2abbe072003-06-16 23:50:08 +000085 * at91rm9200_EmacDisableMDIO
wdenk8bde7f72003-06-27 21:31:46 +000086 * Description:
wdenk2abbe072003-06-16 23:50:08 +000087 * Disables the MDIO bit in MAC control register
wdenk8bde7f72003-06-27 21:31:46 +000088 * Arguments:
wdenk2abbe072003-06-16 23:50:08 +000089 * p_mac - pointer to struct AT91S_EMAC
wdenk8bde7f72003-06-27 21:31:46 +000090 * Return value:
wdenk2abbe072003-06-16 23:50:08 +000091 * none
92 */
wdenk429168e2004-08-02 23:39:03 +000093void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
wdenk2abbe072003-06-16 23:50:08 +000094{
95 /* Mac CTRL reg set for MDIO disable */
96 p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE; /* Management port disable */
97}
98
99
100/*
wdenk8bde7f72003-06-27 21:31:46 +0000101 * Name:
wdenk2abbe072003-06-16 23:50:08 +0000102 * at91rm9200_EmacReadPhy
wdenk8bde7f72003-06-27 21:31:46 +0000103 * Description:
wdenk2abbe072003-06-16 23:50:08 +0000104 * Reads data from the PHY register
wdenk8bde7f72003-06-27 21:31:46 +0000105 * Arguments:
wdenk2abbe072003-06-16 23:50:08 +0000106 * dev - pointer to struct net_device
107 * RegisterAddress - unsigned char
wdenk8bde7f72003-06-27 21:31:46 +0000108 * pInput - pointer to value read from register
109 * Return value:
wdenk2abbe072003-06-16 23:50:08 +0000110 * TRUE - if data read successfully
111 */
wdenk429168e2004-08-02 23:39:03 +0000112UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
wdenk2abbe072003-06-16 23:50:08 +0000113 unsigned char RegisterAddress,
114 unsigned short *pInput)
115{
116 p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
wdenk074cff02004-02-24 00:16:43 +0000117 (AT91C_EMAC_RW_R) |
118 (RegisterAddress << 18) |
119 (AT91C_EMAC_CODE_802_3);
wdenk2abbe072003-06-16 23:50:08 +0000120
121 udelay (10000);
122
123 *pInput = (unsigned short) p_mac->EMAC_MAN;
124
125 return TRUE;
126}
127
128
129/*
wdenk8bde7f72003-06-27 21:31:46 +0000130 * Name:
wdenk2abbe072003-06-16 23:50:08 +0000131 * at91rm9200_EmacWritePhy
wdenk8bde7f72003-06-27 21:31:46 +0000132 * Description:
wdenk2abbe072003-06-16 23:50:08 +0000133 * Writes data to the PHY register
wdenk8bde7f72003-06-27 21:31:46 +0000134 * Arguments:
wdenk2abbe072003-06-16 23:50:08 +0000135 * dev - pointer to struct net_device
136 * RegisterAddress - unsigned char
wdenk8bde7f72003-06-27 21:31:46 +0000137 * pOutput - pointer to value to be written in the register
138 * Return value:
wdenk2abbe072003-06-16 23:50:08 +0000139 * TRUE - if data read successfully
140 */
wdenk429168e2004-08-02 23:39:03 +0000141UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
wdenka3ad8e22003-10-19 23:22:11 +0000142 unsigned char RegisterAddress,
143 unsigned short *pOutput)
wdenk2abbe072003-06-16 23:50:08 +0000144{
145 p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
146 AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W |
wdenka3ad8e22003-10-19 23:22:11 +0000147 (RegisterAddress << 18) | *pOutput;
wdenk2abbe072003-06-16 23:50:08 +0000148
149 udelay (10000);
150
151 return TRUE;
152}
153
wdenk2abbe072003-06-16 23:50:08 +0000154int eth_init (bd_t * bd)
155{
156 int ret;
157 int i;
158
159 p_mac = AT91C_BASE_EMAC;
160
wdenk0b8fa032004-04-25 14:37:29 +0000161 /* PIO Disable Register */
162 *AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER |
163 AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV |
164 AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN |
165 AT91C_PA7_ETXCK_EREFCK;
wdenk2abbe072003-06-16 23:50:08 +0000166
wdenkea287de2005-04-01 00:25:43 +0000167#ifdef CONFIG_AT91C_USE_RMII
168 *AT91C_PIOB_PDR = AT91C_PB19_ERXCK;
169 *AT91C_PIOB_BSR = AT91C_PB19_ERXCK;
170#else
171 *AT91C_PIOB_PDR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
wdenk0b8fa032004-04-25 14:37:29 +0000172 AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
173 AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
wdenk2abbe072003-06-16 23:50:08 +0000174
wdenk0b8fa032004-04-25 14:37:29 +0000175 /* Select B Register */
wdenkea287de2005-04-01 00:25:43 +0000176 *AT91C_PIOB_BSR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL |
wdenk0b8fa032004-04-25 14:37:29 +0000177 AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 |
178 AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
wdenk9d5028c2004-11-21 00:06:33 +0000179#endif
wdenk2abbe072003-06-16 23:50:08 +0000180
181 *AT91C_PMC_PCER = 1 << AT91C_ID_EMAC; /* Peripheral Clock Enable Register */
182
183 p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */
184
185 /* Init Ehternet buffers */
wdenk2abbe072003-06-16 23:50:08 +0000186 for (i = 0; i < RBF_FRAMEMAX; i++) {
Wolfgang Denkf57f70a2005-10-13 01:45:54 +0200187 rbfdt[i].addr = (unsigned long)rbf_framebuf[i];
wdenk2abbe072003-06-16 23:50:08 +0000188 rbfdt[i].size = 0;
189 }
190 rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
191 rbfp = &rbfdt[0];
192
wdenk0b8fa032004-04-25 14:37:29 +0000193 p_mac->EMAC_SA2L = (bd->bi_enetaddr[3] << 24) | (bd->bi_enetaddr[2] << 16)
194 | (bd->bi_enetaddr[1] << 8) | (bd->bi_enetaddr[0]);
195 p_mac->EMAC_SA2H = (bd->bi_enetaddr[5] << 8) | (bd->bi_enetaddr[4]);
196
197 p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
198 p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
199
200 p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC)
201 & ~AT91C_EMAC_CLK;
202
203#ifdef CONFIG_AT91C_USE_RMII
204 p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
205#endif
206
wdenkba83a302005-04-04 12:23:03 +0000207#if (AT91C_MASTER_CLOCK > 40000000)
208 /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
209 p_mac->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64;
210#endif
211
wdenk0b8fa032004-04-25 14:37:29 +0000212 p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
213
Wolfgang Denk080bdb72005-10-05 01:51:29 +0200214 at91rm9200_GetPhyInterface (& PhyOps);
wdenk2abbe072003-06-16 23:50:08 +0000215
wdenk429168e2004-08-02 23:39:03 +0000216 if (!PhyOps.IsPhyConnected (p_mac))
wdenk2abbe072003-06-16 23:50:08 +0000217 printf ("PHY not connected!!\n\r");
218
219 /* MII management start from here */
220 if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) {
wdenk429168e2004-08-02 23:39:03 +0000221 if (!(ret = PhyOps.Init (p_mac))) {
wdenk2abbe072003-06-16 23:50:08 +0000222 printf ("MAC: error during MII initialization\n");
223 return 0;
224 }
225 } else {
226 printf ("No link\n\r");
227 return 0;
228 }
229
wdenk2abbe072003-06-16 23:50:08 +0000230 return 0;
231}
232
233int eth_send (volatile void *packet, int length)
234{
235 while (!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ));
236 p_mac->EMAC_TAR = (long) packet;
237 p_mac->EMAC_TCR = length;
238 while (p_mac->EMAC_TCR & 0x7ff);
239 p_mac->EMAC_TSR |= AT91C_EMAC_COMP;
240 return 0;
241}
242
243int eth_rx (void)
244{
245 int size;
246
247 if (!(rbfp->addr & RBF_OWNER))
248 return 0;
249
250 size = rbfp->size & RBF_SIZE;
251 NetReceive ((volatile uchar *) (rbfp->addr & RBF_ADDR), size);
252
253 rbfp->addr &= ~RBF_OWNER;
254 if (rbfp->addr & RBF_WRAP)
255 rbfp = &rbfdt[0];
256 else
257 rbfp++;
258
259 p_mac->EMAC_RSR |= AT91C_EMAC_REC;
260
261 return size;
262}
263
264void eth_halt (void)
265{
266};
wdenk074cff02004-02-24 00:16:43 +0000267
Jon Loeliger3a1ed1e2007-07-09 18:57:22 -0500268#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200269int at91rm9200_miiphy_read(char *devname, unsigned char addr,
270 unsigned char reg, unsigned short * value)
wdenk074cff02004-02-24 00:16:43 +0000271{
272 at91rm9200_EmacEnableMDIO (p_mac);
273 at91rm9200_EmacReadPhy (p_mac, reg, value);
274 at91rm9200_EmacDisableMDIO (p_mac);
275 return 0;
276}
277
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200278int at91rm9200_miiphy_write(char *devname, unsigned char addr,
279 unsigned char reg, unsigned short value)
wdenk074cff02004-02-24 00:16:43 +0000280{
281 at91rm9200_EmacEnableMDIO (p_mac);
282 at91rm9200_EmacWritePhy (p_mac, reg, &value);
283 at91rm9200_EmacDisableMDIO (p_mac);
284 return 0;
285}
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200286
Jon Loeliger3a1ed1e2007-07-09 18:57:22 -0500287#endif
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200288
289int at91rm9200_miiphy_initialize(bd_t *bis)
290{
Jon Loeliger3a1ed1e2007-07-09 18:57:22 -0500291#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200292 miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write);
293#endif
294 return 0;
295}
wdenk074cff02004-02-24 00:16:43 +0000296
Jon Loeliger3a1ed1e2007-07-09 18:57:22 -0500297#endif
wdenk074cff02004-02-24 00:16:43 +0000298
wdenk2abbe072003-06-16 23:50:08 +0000299#endif /* CONFIG_DRIVER_ETHER */