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Wolfgang Denkb20d0032005-08-05 12:19:30 +02001/*
2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2003,Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27
28#include <common.h>
29#include <pci.h>
30#include <asm/processor.h>
31#include <asm/immap_85xx.h>
32#include <ioports.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060033#include <spd_sdram.h>
Wolfgang Denkb20d0032005-08-05 12:19:30 +020034#include <miiphy.h>
35
36#if defined(CONFIG_DDR_ECC)
37extern void ddr_enable_ecc(unsigned int dram_size);
38#endif
39
Wolfgang Denkb20d0032005-08-05 12:19:30 +020040void local_bus_init(void);
41long int fixed_sdram(void);
42
43/*
44 * I/O Port configuration table
45 *
46 * if conf is 1, then that port pin will be configured at boot time
47 * according to the five values podr/pdir/ppar/psor/pdat for that entry
48 */
49
50const iop_conf_t iop_conf_tab[4][32] = {
51
52 /* Port A configuration */
53 { /* conf ppar psor pdir podr pdat */
54 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
55 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
56 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
57 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
58 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
59 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
60 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
61 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
62 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
63 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
64 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
65 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
66 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
67 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
68 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
69 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
70 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
71 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
72 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
73 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
74 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
75 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
76 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
77 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
78 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
79 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
80 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
81 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
82 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
83 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
84 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */
85 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
86 },
87
88 /* Port B configuration */
89 { /* conf ppar psor pdir podr pdat */
90 /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
91 /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
92 /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
93 /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
94 /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
95 /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
96 /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
97 /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
98 /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
99 /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
100 /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
101 /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
102 /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
103 /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
104 /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
105 /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
106 /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
107 /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
108 /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */
109 /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
110 /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
111 /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
112 /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
113 /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
114 /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
115 /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
116 /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
117 /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
118 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
119 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
120 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
121 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
122 },
123
124 /* Port C */
125 { /* conf ppar psor pdir podr pdat */
126 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
127 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
128 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
129 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
130 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
131 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
132 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
133 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
134 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
135 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
136 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
137 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
138 /* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
139 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
140 /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */
141 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
142 /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
143 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
144 /* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */
145 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
146 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
147 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
148 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
149 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
150 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
151 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
152 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
153 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
154 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
155 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
156 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
157 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
158 },
159
160 /* Port D */
161 { /* conf ppar psor pdir podr pdat */
162 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
163 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
164 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
165 /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */
166 /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */
167 /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */
168 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
169 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
170 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
171 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
172 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
173 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
174 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
175 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
176 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
177 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
178 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
179 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
180 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
181 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
182 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
183 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
184 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
185 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
186 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
187 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
188 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
189 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
190 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
191 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
192 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
193 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
194 }
195};
196
197
198int board_early_init_f (void)
199{
200 return 0;
201}
202
203void reset_phy (void)
204{
205}
206
207
208int checkboard (void)
209{
210 puts("Board: MicroSys PM856\n");
211
212#ifdef CONFIG_PCI
213 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
214 CONFIG_SYS_CLK_FREQ / 1000000);
215#else
216 printf(" PCI1: disabled\n");
217#endif
218
219 /*
220 * Initialize local bus.
221 */
222 local_bus_init();
223
224 return 0;
225}
226
227
228long int
229initdram(int board_type)
230{
231 long dram_size = 0;
Jon Loeligera30a5492008-03-04 10:03:03 -0600232
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200233
234 puts("Initializing\n");
235
236#if defined(CONFIG_DDR_DLL)
237 {
Kumar Galaf59b55a2007-11-27 23:25:02 -0600238 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200239 int i,x;
240
241 x = 10;
242
243 /*
244 * Work around to stabilize DDR DLL
245 */
246 gur->ddrdllcr = 0x81000000;
247 asm("sync;isync;msync");
248 udelay (200);
249 while (gur->ddrdllcr != 0x81000100)
250 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200251 gur->devdisr = gur->devdisr | 0x00010000;
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200252 asm("sync;isync;msync");
253 for (i=0; i<x; i++)
254 ;
255 gur->devdisr = gur->devdisr & 0xfff7ffff;
256 asm("sync;isync;msync");
257 x++;
258 }
259 }
260#endif
261
262#if defined(CONFIG_SPD_EEPROM)
263 dram_size = spd_sdram ();
264#else
265 dram_size = fixed_sdram ();
266#endif
267
268#if defined(CONFIG_DDR_ECC)
269 /*
270 * Initialize and enable DDR ECC.
271 */
272 ddr_enable_ecc(dram_size);
273#endif
274
275 puts(" DDR: ");
276 return dram_size;
277}
278
279
280/*
281 * Initialize Local Bus
282 */
283
284void
285local_bus_init(void)
286{
Kumar Galaf59b55a2007-11-27 23:25:02 -0600287 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
Kumar Gala04db4002007-11-29 02:10:09 -0600288 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200289
290 uint clkdiv;
291 uint lbc_hz;
292 sys_info_t sysinfo;
293
294 /*
295 * Errata LBC11.
296 * Fix Local Bus clock glitch when DLL is enabled.
297 *
298 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
299 * If localbus freq is > 133Mhz, DLL can be safely enabled.
300 * Between 66 and 133, the DLL is enabled with an override workaround.
301 */
302
303 get_sys_info(&sysinfo);
304 clkdiv = lbc->lcrr & 0x0f;
305 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
306
307 if (lbc_hz < 66) {
308 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
309
310 } else if (lbc_hz >= 133) {
311 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
312
313 } else {
314 /*
315 * On REV1 boards, need to change CLKDIV before enable DLL.
316 * Default CLKDIV is 8, change it to 4 temporarily.
317 */
318 uint pvr = get_pvr();
319 uint temp_lbcdll = 0;
320
321 if (pvr == PVR_85xx_REV1) {
322 /* FIXME: Justify the high bit here. */
323 lbc->lcrr = 0x10000004;
324 }
325
326 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
327 udelay(200);
328
329 /*
330 * Sample LBC DLL ctrl reg, upshift it to set the
331 * override bits.
332 */
333 temp_lbcdll = gur->lbcdllcr;
334 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
335 asm("sync;isync;msync");
336 }
337}
338
339#if defined(CFG_DRAM_TEST)
340int testdram (void)
341{
342 uint *pstart = (uint *) CFG_MEMTEST_START;
343 uint *pend = (uint *) CFG_MEMTEST_END;
344 uint *p;
345
346 printf("SDRAM test phase 1:\n");
347 for (p = pstart; p < pend; p++)
348 *p = 0xaaaaaaaa;
349
350 for (p = pstart; p < pend; p++) {
351 if (*p != 0xaaaaaaaa) {
352 printf ("SDRAM test fails at: %08x\n", (uint) p);
353 return 1;
354 }
355 }
356
357 printf("SDRAM test phase 2:\n");
358 for (p = pstart; p < pend; p++)
359 *p = 0x55555555;
360
361 for (p = pstart; p < pend; p++) {
362 if (*p != 0x55555555) {
363 printf ("SDRAM test fails at: %08x\n", (uint) p);
364 return 1;
365 }
366 }
367
368 printf("SDRAM test passed.\n");
369 return 0;
370}
371#endif
372
373
374#if !defined(CONFIG_SPD_EEPROM)
375/*************************************************************************
376 * fixed sdram init -- doesn't use serial presence detect.
377 ************************************************************************/
378long int fixed_sdram (void)
379{
380 #ifndef CFG_RAMBOOT
Kumar Gala04db4002007-11-29 02:10:09 -0600381 volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200382
383 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
384 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
385 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
386 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
387 ddr->sdram_mode = CFG_DDR_MODE;
388 ddr->sdram_interval = CFG_DDR_INTERVAL;
389 #if defined (CONFIG_DDR_ECC)
390 ddr->err_disable = 0x0000000D;
391 ddr->err_sbe = 0x00ff0000;
392 #endif
393 asm("sync;isync;msync");
394 udelay(500);
395 #if defined (CONFIG_DDR_ECC)
396 /* Enable ECC checking */
397 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
398 #else
399 ddr->sdram_cfg = CFG_DDR_CONTROL;
400 #endif
401 asm("sync; isync; msync");
402 udelay(500);
403 #endif
404 return CFG_SDRAM_SIZE * 1024 * 1024;
405}
406#endif /* !defined(CONFIG_SPD_EEPROM) */
407
408
409#if defined(CONFIG_PCI)
410/*
411 * Initialize PCI Devices, report devices found.
412 */
413
414#ifndef CONFIG_PCI_PNP
415static struct pci_config_table pci_mpc85xxads_config_table[] = {
416 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
417 PCI_IDSEL_NUMBER, PCI_ANY_ID,
418 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
419 PCI_ENET0_MEMADDR,
420 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
421 } },
422 { }
423};
424#endif
425
426
427static struct pci_controller hose = {
428#ifndef CONFIG_PCI_PNP
429 config_table: pci_mpc85xxads_config_table,
430#endif
431};
432
433#endif /* CONFIG_PCI */
434
435
436void
437pci_init_board(void)
438{
439#ifdef CONFIG_PCI
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200440 pci_mpc85xx_init(&hose);
441#endif /* CONFIG_PCI */
442}