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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2000, 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37#define CONFIG_RRVISION 1 /* ...on a RRvision board */
38
39#define CONFIG_8xx_GCLK_FREQ 64000000
40
41#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
42#undef CONFIG_8xx_CONS_SMC2
43#undef CONFIG_8xx_CONS_NONE
44#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
45#if 0
46#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
47#else
48#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
49#endif
50
51#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
52
53#define CONFIG_PREBOOT "setenv stdout serial"
54
55#undef CONFIG_BOOTARGS
56#define CONFIG_ETHADDR 00:50:C2:00:E0:70
57#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
58#define CONFIG_IPADDR 10.0.0.5
59#define CONFIG_SERVERIP 10.0.0.2
60#define CONFIG_NETMASK 255.0.0.0
61#define CONFIG_ROOTPATH /opt/eldk/ppc_8xx
62#define CONFIG_BOOTCOMMAND "run flash_self"
63
64#define CONFIG_EXTRA_ENV_SETTINGS \
65 "netdev=eth0\0" \
66 "ramargs=setenv bootargs root=/dev/ram rw\0" \
67 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010068 "nfsroot=${serverip}:${rootpath}\0" \
69 "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}" \
70 ":${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
71 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
wdenke2211742002-11-02 23:30:20 +000072 "load=tftp 100000 /tftpboot/u-boot.bin\0" \
73 "update=protect off 1:0-8;era 1:0-8;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010074 "cp.b 100000 40000000 ${filesize};" \
wdenke2211742002-11-02 23:30:20 +000075 "setenv filesize;saveenv\0" \
76 "kernel_addr=40040000\0" \
77 "ramdisk_addr=40100000\0" \
wdenk3bac3512003-03-12 10:41:04 +000078 "kernel_img=/tftpboot/uImage\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010079 "kernel_load=tftp 200000 ${kernel_img}\0" \
wdenke2211742002-11-02 23:30:20 +000080 "net_nfs=run kernel_load nfsargs addip addtty;bootm\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010081 "flash_nfs=run nfsargs addip addtty;bootm ${kernel_addr}\0" \
wdenke2211742002-11-02 23:30:20 +000082 "flash_self=run ramargs addip addtty;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010083 "bootm ${kernel_addr} ${ramdisk_addr}\0"
wdenke2211742002-11-02 23:30:20 +000084
85
86#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
87#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
88
89#undef CONFIG_WATCHDOG /* watchdog disabled */
90
91#undef CONFIG_STATUS_LED /* disturbs display */
92
93#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
94
Jon Loeliger18225e82007-07-09 21:31:24 -050095/*
96 * BOOTP options
97 */
98#define CONFIG_BOOTP_SUBNETMASK
99#define CONFIG_BOOTP_GATEWAY
100#define CONFIG_BOOTP_HOSTNAME
101#define CONFIG_BOOTP_BOOTPATH
102#define CONFIG_BOOTP_BOOTFILESIZE
103
wdenke2211742002-11-02 23:30:20 +0000104
105#define CONFIG_MAC_PARTITION
106#define CONFIG_DOS_PARTITION
107
108#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
109
110
wdenk8564acf2003-07-14 22:13:32 +0000111#ifndef CONFIG_LCD
wdenke2211742002-11-02 23:30:20 +0000112#define CONFIG_VIDEO 1 /* To enable the video initialization */
113
114/* Video related */
115#define CONFIG_VIDEO_LOGO 1 /* Show the logo */
wdenk8564acf2003-07-14 22:13:32 +0000116#define CONFIG_VIDEO_ENCODER_AD7179 1 /* Enable this encoder */
117#define CONFIG_VIDEO_ENCODER_AD7179_ADDR 0x2A /* ALSB to ground */
wdenke2211742002-11-02 23:30:20 +0000118#endif
119
120/* enable I2C and select the hardware/software driver */
121#undef CONFIG_HARD_I2C /* I2C with hardware support */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200122#define CONFIG_SOFT_I2C /* I2C bit-banged */
wdenke2211742002-11-02 23:30:20 +0000123
124# define CFG_I2C_SPEED 50000 /* 50 kHz is supposed to work */
125# define CFG_I2C_SLAVE 0xFE
126
127#ifdef CONFIG_SOFT_I2C
128/*
129 * Software (bit-bang) I2C driver configuration
130 */
131#define PB_SCL 0x00000020 /* PB 26 */
132#define PB_SDA 0x00000010 /* PB 27 */
133
134#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
135#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
136#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
137#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
138#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
139 else immr->im_cpm.cp_pbdat &= ~PB_SDA
140#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
141 else immr->im_cpm.cp_pbdat &= ~PB_SCL
142#define I2C_DELAY udelay(1) /* 1/4 I2C clock duration */
143#endif /* CONFIG_SOFT_I2C */
144
145
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500146/*
147 * Command line configuration.
148 */
149#include <config_cmd_default.h>
wdenke2211742002-11-02 23:30:20 +0000150
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500151#define CONFIG_CMD_DHCP
152#define CONFIG_CMD_I2C
153#define CONFIG_CMD_IDE
154#define CONFIG_CMD_DATE
155
156#undef CONFIG_CMD_PCMCIA
157#undef CONFIG_CMD_IDE
158
wdenke2211742002-11-02 23:30:20 +0000159
160/*
161 * Miscellaneous configurable options
162 */
163#define CFG_LONGHELP /* undef to save memory */
164#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500165#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000166#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
167#else
168#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
169#endif
170#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
171#define CFG_MAXARGS 16 /* max number of command args */
172#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
173
174#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
175#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
176
177#define CFG_LOAD_ADDR 0x100000 /* default load address */
178
179#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
180
181#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
182
183/*
184 * Low Level Configuration Settings
185 * (address mappings, register initial values, etc.)
186 * You should know what you are doing if you make changes here.
187 */
188/*-----------------------------------------------------------------------
189 * Internal Memory Mapped Register
190 */
191#define CFG_IMMR 0xFFF00000
192
193/*-----------------------------------------------------------------------
194 * Definitions for initial stack pointer and data area (in DPRAM)
195 */
196#define CFG_INIT_RAM_ADDR CFG_IMMR
197#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
198#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
199#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
200#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
201
202/*-----------------------------------------------------------------------
203 * Start addresses for the final memory configuration
204 * (Set up by the startup code)
205 * Please note that CFG_SDRAM_BASE _must_ start at 0
206 */
207#define CFG_SDRAM_BASE 0x00000000
208#define CFG_FLASH_BASE 0x40000000
209#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
210#define CFG_MONITOR_BASE CFG_FLASH_BASE
211#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
212
213/*
214 * For booting Linux, the board info and command line data
215 * have to be in the first 8 MB of memory, since this is
216 * the maximum mapped by the Linux kernel during initialization.
217 */
218#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
219
220/*-----------------------------------------------------------------------
221 * FLASH organization
222 */
223#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
224#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
225
226/* timeout values are in ticks = ms */
227#define CFG_FLASH_ERASE_TOUT (120*CFG_HZ) /* Timeout for Flash Erase */
228#define CFG_FLASH_WRITE_TOUT (1 * CFG_HZ) /* Timeout for Flash Write */
229
230#define CFG_ENV_IS_IN_FLASH 1
231#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
232#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
233
234/* Address and size of Redundant Environment Sector */
235#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
236#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
237
Wolfgang Denk67c31032007-09-16 17:10:04 +0200238#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
239
wdenke2211742002-11-02 23:30:20 +0000240/*-----------------------------------------------------------------------
241 * Cache Configuration
242 */
243#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500244#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000245#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
246#endif
247
248/*-----------------------------------------------------------------------
249 * SYPCR - System Protection Control 11-9
250 * SYPCR can only be written once after reset!
251 *-----------------------------------------------------------------------
252 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
253 */
254#if defined(CONFIG_WATCHDOG)
255#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
256 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
257#else
258#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
259#endif
260
261/*-----------------------------------------------------------------------
262 * SIUMCR - SIU Module Configuration 11-6
263 *-----------------------------------------------------------------------
264 * PCMCIA config., multi-function pin tri-state
265 */
266#ifndef CONFIG_CAN_DRIVER
267#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
268#else /* we must activate GPL5 in the SIUMCR for CAN */
269#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
270#endif /* CONFIG_CAN_DRIVER */
271
272/*-----------------------------------------------------------------------
273 * TBSCR - Time Base Status and Control 11-26
274 *-----------------------------------------------------------------------
275 * Clear Reference Interrupt Status, Timebase freezing enabled
276 */
277#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
278
279/*-----------------------------------------------------------------------
280 * RTCSC - Real-Time Clock Status and Control Register 11-27
281 *-----------------------------------------------------------------------
282 */
283#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
284
285/*-----------------------------------------------------------------------
286 * PISCR - Periodic Interrupt Status and Control 11-31
287 *-----------------------------------------------------------------------
288 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
289 */
290#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
291
292/*-----------------------------------------------------------------------
293 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
294 *-----------------------------------------------------------------------
295 * Reset PLL lock status sticky bit, timer expired status bit and timer
296 * interrupt status bit
297 */
298
299/* for 64 MHz, we use a 16 MHz clock * 4 */
300#define CFG_PLPRCR ( (4-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
301
302/*-----------------------------------------------------------------------
303 * SCCR - System Clock and reset Control Register 15-27
304 *-----------------------------------------------------------------------
305 * Set clock output, timebase and RTC source and divider,
306 * power management and some other internal clocks
307 */
308#define SCCR_MASK SCCR_EBDF11
309#define CFG_SCCR (/* SCCR_TBS | */ SCCR_RTSEL | SCCR_RTDIV | \
310 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
311 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
312 SCCR_DFALCD00)
313
314/*-----------------------------------------------------------------------
315 * PCMCIA stuff
316 *-----------------------------------------------------------------------
317 *
318 */
319#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
320#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
321#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
322#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
323#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
324#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
325#define CFG_PCMCIA_IO_ADDR (0xEC000000)
326#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
327
328/*-----------------------------------------------------------------------
329 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
330 *-----------------------------------------------------------------------
331 */
332
333#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
334
335#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
336#undef CONFIG_IDE_LED /* LED for ide not supported */
337#undef CONFIG_IDE_RESET /* reset for ide not supported */
338
339#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
340#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
341
342#define CFG_ATA_IDE0_OFFSET 0x0000
343
344#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
345
346/* Offset for data I/O */
347#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
348
349/* Offset for normal register accesses */
350#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
351
352/* Offset for alternate registers */
353#define CFG_ATA_ALT_OFFSET 0x0100
354
355/*-----------------------------------------------------------------------
356 *
357 *-----------------------------------------------------------------------
358 *
359 */
wdenk8564acf2003-07-14 22:13:32 +0000360/*#define CFG_DER 0x2002000F*/
wdenke2211742002-11-02 23:30:20 +0000361#define CFG_DER 0
362
363/*
364 * Init Memory Controller:
365 *
366 * BR0/1 (FLASH)
367 */
368
369#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
370
371/* used to re-map FLASH both when starting from SRAM or FLASH:
372 * restrict access enough to keep SRAM working (if any)
373 * but not too much to meddle with FLASH accesses
374 */
375#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
376#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
377
378/*
379 * FLASH timing:
380 */
381/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
382#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
383 OR_SCY_3_CLK | OR_EHTR | OR_BI)
384
385#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
386#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
387#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
388
389/*
390 * BR2/3 and OR2/3 (SDRAM)
391 *
392 */
393#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
394#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
395#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
396
397/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
398#define CFG_OR_TIMING_SDRAM 0x00000A00
399
400#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
401#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
402
403#ifndef CONFIG_CAN_DRIVER
404#define CFG_OR3_PRELIM CFG_OR2_PRELIM
405#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
406#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
407#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
408#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
409#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
410#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
411 BR_PS_8 | BR_MS_UPMB | BR_V )
412#endif /* CONFIG_CAN_DRIVER */
413
414/*
415 * Memory Periodic Timer Prescaler
416 *
417 * The Divider for PTA (refresh timer) configuration is based on an
418 * example SDRAM configuration (64 MBit, one bank). The adjustment to
419 * the number of chip selects (NCS) and the actually needed refresh
420 * rate is done by setting MPTPR.
421 *
422 * PTA is calculated from
423 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
424 *
425 * gclk CPU clock (not bus clock!)
426 * Trefresh Refresh cycle * 4 (four word bursts used)
427 *
428 * 4096 Rows from SDRAM example configuration
429 * 1000 factor s -> ms
430 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
431 * 4 Number of refresh cycles per period
432 * 64 Refresh cycle in ms per number of rows
433 * --------------------------------------------
434 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
435 *
436 * 50 MHz => 50.000.000 / Divider = 98
437 * 66 Mhz => 66.000.000 / Divider = 129
438 * 80 Mhz => 80.000.000 / Divider = 156
439 */
440#define CFG_MAMR_PTA 129
441
442/*
443 * For 16 MBit, refresh rates could be 31.3 us
444 * (= 64 ms / 2K = 125 / quad bursts).
445 * For a simpler initialization, 15.6 us is used instead.
446 *
447 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
448 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
449 */
450#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
451#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
452
453/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
454#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
455#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
456
457/*
458 * MAMR settings for SDRAM
459 */
460
461/* 8 column SDRAM */
462#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
463 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
464 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
465/* 9 column SDRAM */
466#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
467 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
468 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
469
470
471/*
472 * Internal Definitions
473 *
474 * Boot Flags
475 */
476#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
477#define BOOTFLAG_WARM 0x02 /* Software reboot */
478
479#endif /* __CONFIG_H */