blob: 45395cdda6f0d2b7da0411afaada0af3cd8571e7 [file] [log] [blame]
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +09001/*
2 * include/configs/gose.h
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 *
6 * SPDX-License-Identifier: GPL-2.0
7 */
8
9#ifndef __GOSE_H
10#define __GOSE_H
11
12#undef DEBUG
13#define CONFIG_R8A7793
Nobuhiro Iwamatsu1cc95f62015-10-10 05:58:28 +090014#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Gose"
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090015
Nobuhiro Iwamatsu5ca6dfe2014-11-10 14:34:07 +090016#include "rcar-gen2-common.h"
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090017
Nobuhiro Iwamatsu1cc95f62015-10-10 05:58:28 +090018#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090019#define CONFIG_SYS_TEXT_BASE 0x70000000
20#else
21#define CONFIG_SYS_TEXT_BASE 0xE6304000
22#endif
23
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090024/* STACK */
Nobuhiro Iwamatsu1cc95f62015-10-10 05:58:28 +090025#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090026#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
27#else
28#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
29#endif
30
31#define STACK_AREA_SIZE 0xC000
32#define LOW_LEVEL_MERAM_STACK \
33 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
34
35/* MEMORY */
Nobuhiro Iwamatsu5ca6dfe2014-11-10 14:34:07 +090036#define RCAR_GEN2_SDRAM_BASE 0x40000000
37#define RCAR_GEN2_SDRAM_SIZE 0x40000000
38#define RCAR_GEN2_UBOOT_SDRAM_SIZE 0x20000000
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090039
40/* SCIF */
41#define CONFIG_SCIF_CONSOLE
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090042
43/* FLASH */
44#define CONFIG_SYS_NO_FLASH
45#define CONFIG_SPI
46#define CONFIG_SH_QSPI
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090047
Nobuhiro Iwamatsuf0261242014-11-06 15:42:24 +090048/* SH Ether */
Nobuhiro Iwamatsuf0261242014-11-06 15:42:24 +090049#define CONFIG_SH_ETHER
50#define CONFIG_SH_ETHER_USE_PORT 0
51#define CONFIG_SH_ETHER_PHY_ADDR 0x1
52#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
53#define CONFIG_SH_ETHER_CACHE_WRITEBACK
54#define CONFIG_SH_ETHER_CACHE_INVALIDATE
55#define CONFIG_PHYLIB
56#define CONFIG_PHY_MICREL
57#define CONFIG_BITBANGMII
58#define CONFIG_BITBANGMII_MULTI
59#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
60
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090061/* Board Clock */
62#define RMOBILE_XTAL_CLK 20000000u
63#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
64#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090065#define CONFIG_SYS_TMU_CLK_DIV 4
66
67/* I2C */
68#define CONFIG_SYS_I2C
69#define CONFIG_SYS_I2C_SH
70#define CONFIG_SYS_I2C_SLAVE 0x7F
71#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090072#define CONFIG_SYS_I2C_SH_SPEED0 400000
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090073#define CONFIG_SYS_I2C_SH_SPEED1 400000
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090074#define CONFIG_SYS_I2C_SH_SPEED2 400000
75#define CONFIG_SH_I2C_DATA_HIGH 4
76#define CONFIG_SH_I2C_DATA_LOW 5
77#define CONFIG_SH_I2C_CLOCK 10000000
78
79#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
80
Nobuhiro Iwamatsud3ee73f2014-11-06 15:42:25 +090081/* USB */
Nobuhiro Iwamatsud3ee73f2014-11-06 15:42:25 +090082#define CONFIG_USB_EHCI
83#define CONFIG_USB_EHCI_RMOBILE
84#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
85
Nobuhiro Iwamatsu8e2e5882014-12-02 16:52:24 +090086/* Module stop status bits */
87/* INTC-RT */
88#define CONFIG_SMSTP0_ENA 0x00400000
89/* MSIF */
90#define CONFIG_SMSTP2_ENA 0x00002000
91/* INTC-SYS, IRQC */
92#define CONFIG_SMSTP4_ENA 0x00000180
93/* SCIF0 */
94#define CONFIG_SMSTP7_ENA 0x00200000
95
Nobuhiro Iwamatsue2abab62014-11-12 11:29:39 +090096/* SDHI */
Nobuhiro Iwamatsue2abab62014-11-12 11:29:39 +090097#define CONFIG_GENERIC_MMC
98#define CONFIG_SH_SDHI_FREQ 97500000
99
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +0900100#endif /* __GOSE_H */