Gregory CLEMENT | 53bdae2 | 2018-12-08 09:59:01 +0100 | [diff] [blame^] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | /* |
| 3 | * Microsemi SoCs pinctrl driver |
| 4 | * |
| 5 | * Author: <alexandre.belloni@free-electrons.com> |
| 6 | * Author: <gregory.clement@bootlin.com> |
| 7 | * License: Dual MIT/GPL |
| 8 | * Copyright (c) 2017 Microsemi Corporation |
| 9 | */ |
| 10 | |
| 11 | #include <asm/gpio.h> |
| 12 | #include <asm/system.h> |
| 13 | #include <common.h> |
| 14 | #include <config.h> |
| 15 | #include <dm.h> |
| 16 | #include <dm/device-internal.h> |
| 17 | #include <dm/lists.h> |
| 18 | #include <dm/pinctrl.h> |
| 19 | #include <dm/root.h> |
| 20 | #include <errno.h> |
| 21 | #include <fdtdec.h> |
| 22 | #include <linux/io.h> |
| 23 | #include "mscc-common.h" |
| 24 | |
| 25 | enum { |
| 26 | FUNC_NONE, |
| 27 | FUNC_GPIO, |
| 28 | FUNC_IRQ0_IN, |
| 29 | FUNC_IRQ0_OUT, |
| 30 | FUNC_IRQ1_IN, |
| 31 | FUNC_IRQ1_OUT, |
| 32 | FUNC_MIIM1, |
| 33 | FUNC_PCI_WAKE, |
| 34 | FUNC_PTP0, |
| 35 | FUNC_PTP1, |
| 36 | FUNC_PTP2, |
| 37 | FUNC_PTP3, |
| 38 | FUNC_PWM, |
| 39 | FUNC_RECO_CLK0, |
| 40 | FUNC_RECO_CLK1, |
| 41 | FUNC_SFP0, |
| 42 | FUNC_SFP1, |
| 43 | FUNC_SFP2, |
| 44 | FUNC_SFP3, |
| 45 | FUNC_SFP4, |
| 46 | FUNC_SFP5, |
| 47 | FUNC_SG0, |
| 48 | FUNC_SI, |
| 49 | FUNC_TACHO, |
| 50 | FUNC_TWI, |
| 51 | FUNC_TWI_SCL_M, |
| 52 | FUNC_UART, |
| 53 | FUNC_UART2, |
| 54 | FUNC_MAX |
| 55 | }; |
| 56 | |
| 57 | static char * const ocelot_function_names[] = { |
| 58 | [FUNC_NONE] = "none", |
| 59 | [FUNC_GPIO] = "gpio", |
| 60 | [FUNC_IRQ0_IN] = "irq0_in", |
| 61 | [FUNC_IRQ0_OUT] = "irq0_out", |
| 62 | [FUNC_IRQ1_IN] = "irq1_in", |
| 63 | [FUNC_IRQ1_OUT] = "irq1_out", |
| 64 | [FUNC_MIIM1] = "miim1", |
| 65 | [FUNC_PCI_WAKE] = "pci_wake", |
| 66 | [FUNC_PTP0] = "ptp0", |
| 67 | [FUNC_PTP1] = "ptp1", |
| 68 | [FUNC_PTP2] = "ptp2", |
| 69 | [FUNC_PTP3] = "ptp3", |
| 70 | [FUNC_PWM] = "pwm", |
| 71 | [FUNC_RECO_CLK0] = "reco_clk0", |
| 72 | [FUNC_RECO_CLK1] = "reco_clk1", |
| 73 | [FUNC_SFP0] = "sfp0", |
| 74 | [FUNC_SFP1] = "sfp1", |
| 75 | [FUNC_SFP2] = "sfp2", |
| 76 | [FUNC_SFP3] = "sfp3", |
| 77 | [FUNC_SFP4] = "sfp4", |
| 78 | [FUNC_SFP5] = "sfp5", |
| 79 | [FUNC_SG0] = "sg0", |
| 80 | [FUNC_SI] = "si", |
| 81 | [FUNC_TACHO] = "tacho", |
| 82 | [FUNC_TWI] = "twi", |
| 83 | [FUNC_TWI_SCL_M] = "twi_scl_m", |
| 84 | [FUNC_UART] = "uart", |
| 85 | [FUNC_UART2] = "uart2", |
| 86 | }; |
| 87 | |
| 88 | MSCC_P(0, SG0, NONE, NONE); |
| 89 | MSCC_P(1, SG0, NONE, NONE); |
| 90 | MSCC_P(2, SG0, NONE, NONE); |
| 91 | MSCC_P(3, SG0, NONE, NONE); |
| 92 | MSCC_P(4, IRQ0_IN, IRQ0_OUT, TWI); |
| 93 | MSCC_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE); |
| 94 | MSCC_P(6, UART, TWI_SCL_M, NONE); |
| 95 | MSCC_P(7, UART, TWI_SCL_M, NONE); |
| 96 | MSCC_P(8, SI, TWI_SCL_M, IRQ0_OUT); |
| 97 | MSCC_P(9, SI, TWI_SCL_M, IRQ1_OUT); |
| 98 | MSCC_P(10, PTP2, TWI_SCL_M, SFP0); |
| 99 | MSCC_P(11, PTP3, TWI_SCL_M, SFP1); |
| 100 | MSCC_P(12, UART2, TWI_SCL_M, SFP2); |
| 101 | MSCC_P(13, UART2, TWI_SCL_M, SFP3); |
| 102 | MSCC_P(14, MIIM1, TWI_SCL_M, SFP4); |
| 103 | MSCC_P(15, MIIM1, TWI_SCL_M, SFP5); |
| 104 | MSCC_P(16, TWI, NONE, SI); |
| 105 | MSCC_P(17, TWI, TWI_SCL_M, SI); |
| 106 | MSCC_P(18, PTP0, TWI_SCL_M, NONE); |
| 107 | MSCC_P(19, PTP1, TWI_SCL_M, NONE); |
| 108 | MSCC_P(20, RECO_CLK0, TACHO, NONE); |
| 109 | MSCC_P(21, RECO_CLK1, PWM, NONE); |
| 110 | |
| 111 | #define OCELOT_PIN(n) { \ |
| 112 | .name = "GPIO_"#n, \ |
| 113 | .drv_data = &mscc_pin_##n \ |
| 114 | } |
| 115 | |
| 116 | static const struct mscc_pin_data ocelot_pins[] = { |
| 117 | OCELOT_PIN(0), |
| 118 | OCELOT_PIN(1), |
| 119 | OCELOT_PIN(2), |
| 120 | OCELOT_PIN(3), |
| 121 | OCELOT_PIN(4), |
| 122 | OCELOT_PIN(5), |
| 123 | OCELOT_PIN(6), |
| 124 | OCELOT_PIN(7), |
| 125 | OCELOT_PIN(8), |
| 126 | OCELOT_PIN(9), |
| 127 | OCELOT_PIN(10), |
| 128 | OCELOT_PIN(11), |
| 129 | OCELOT_PIN(12), |
| 130 | OCELOT_PIN(13), |
| 131 | OCELOT_PIN(14), |
| 132 | OCELOT_PIN(15), |
| 133 | OCELOT_PIN(16), |
| 134 | OCELOT_PIN(17), |
| 135 | OCELOT_PIN(18), |
| 136 | OCELOT_PIN(19), |
| 137 | OCELOT_PIN(20), |
| 138 | OCELOT_PIN(21), |
| 139 | }; |
| 140 | |
| 141 | static int ocelot_gpio_probe(struct udevice *dev) |
| 142 | { |
| 143 | struct gpio_dev_priv *uc_priv; |
| 144 | |
| 145 | uc_priv = dev_get_uclass_priv(dev); |
| 146 | uc_priv->bank_name = "ocelot-gpio"; |
| 147 | uc_priv->gpio_count = ARRAY_SIZE(ocelot_pins); |
| 148 | |
| 149 | return 0; |
| 150 | } |
| 151 | |
| 152 | static struct driver ocelot_gpio_driver = { |
| 153 | .name = "ocelot-gpio", |
| 154 | .id = UCLASS_GPIO, |
| 155 | .probe = ocelot_gpio_probe, |
| 156 | .ops = &mscc_gpio_ops, |
| 157 | }; |
| 158 | |
| 159 | int ocelot_pinctrl_probe(struct udevice *dev) |
| 160 | { |
| 161 | int ret; |
| 162 | |
| 163 | ret = mscc_pinctrl_probe(dev, FUNC_MAX, ocelot_pins, |
| 164 | ARRAY_SIZE(ocelot_pins), |
| 165 | ocelot_function_names); |
| 166 | |
| 167 | if (ret) |
| 168 | return ret; |
| 169 | |
| 170 | ret = device_bind(dev, &ocelot_gpio_driver, "ocelot-gpio", NULL, |
| 171 | dev_of_offset(dev), NULL); |
| 172 | |
| 173 | return ret; |
| 174 | } |
| 175 | |
| 176 | static const struct udevice_id ocelot_pinctrl_of_match[] = { |
| 177 | {.compatible = "mscc,ocelot-pinctrl"}, |
| 178 | {}, |
| 179 | }; |
| 180 | |
| 181 | U_BOOT_DRIVER(ocelot_pinctrl) = { |
| 182 | .name = "ocelot-pinctrl", |
| 183 | .id = UCLASS_PINCTRL, |
| 184 | .of_match = of_match_ptr(ocelot_pinctrl_of_match), |
| 185 | .probe = ocelot_pinctrl_probe, |
| 186 | .priv_auto_alloc_size = sizeof(struct mscc_pinctrl), |
| 187 | .ops = &mscc_pinctrl_ops, |
| 188 | }; |