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wdenkc6097192002-11-03 00:24:07 +00001/*
stroesea20b27a2004-12-16 18:05:42 +00002 * (C) Copyright 2001-2004
wdenkc6097192002-11-03 00:24:07 +00003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
wdenkc6097192002-11-03 00:24:07 +000038#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
wdenkc837dcb2004-01-20 23:12:12 +000039#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
Matthias Fuchs6f35c532007-06-24 17:41:21 +020040#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
wdenkc6097192002-11-03 00:24:07 +000041
wdenkc837dcb2004-01-20 23:12:12 +000042#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
wdenkc6097192002-11-03 00:24:07 +000043
stroesea20b27a2004-12-16 18:05:42 +000044#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
wdenkc6097192002-11-03 00:24:07 +000045
46#define CONFIG_BAUDRATE 9600
47#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
48
wdenkc6097192002-11-03 00:24:07 +000049#undef CONFIG_BOOTARGS
stroesea20b27a2004-12-16 18:05:42 +000050#undef CONFIG_BOOTCOMMAND
51
52#define CONFIG_PREBOOT /* enable preboot variable */
wdenkc6097192002-11-03 00:24:07 +000053
54#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkc6097192002-11-03 00:24:07 +000056
Ben Warren96e21f82008-10-27 23:50:15 -070057#define CONFIG_PPC4xx_EMAC
wdenkc6097192002-11-03 00:24:07 +000058#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000059#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000060#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Matthias Fuchs6f35c532007-06-24 17:41:21 +020061#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
62
63#define CONFIG_NET_MULTI 1
64#undef CONFIG_HAS_ETH1
wdenkc6097192002-11-03 00:24:07 +000065
66#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
67
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050068/*
69 * BOOTP options
70 */
71#define CONFIG_BOOTP_SUBNETMASK
72#define CONFIG_BOOTP_GATEWAY
73#define CONFIG_BOOTP_HOSTNAME
74#define CONFIG_BOOTP_BOOTPATH
75#define CONFIG_BOOTP_DNS
76#define CONFIG_BOOTP_DNS2
77#define CONFIG_BOOTP_SEND_HOSTNAME
stroese9919f132003-05-23 11:38:22 +000078
wdenkc6097192002-11-03 00:24:07 +000079
Jon Loeliger49cf7e82007-07-05 19:52:35 -050080/*
81 * Command line configuration.
82 */
83#include <config_cmd_default.h>
84
85#define CONFIG_CMD_DHCP
86#define CONFIG_CMD_PCI
87#define CONFIG_CMD_IRQ
88#define CONFIG_CMD_IDE
89#define CONFIG_CMD_FAT
90#define CONFIG_CMD_ELF
91#define CONFIG_CMD_DATE
Jon Loeliger49cf7e82007-07-05 19:52:35 -050092#define CONFIG_CMD_I2C
93#define CONFIG_CMD_MII
94#define CONFIG_CMD_PING
95#define CONFIG_CMD_BSP
96#define CONFIG_CMD_EEPROM
97
wdenkc6097192002-11-03 00:24:07 +000098#define CONFIG_MAC_PARTITION
99#define CONFIG_DOS_PARTITION
100
stroesea20b27a2004-12-16 18:05:42 +0000101#define CONFIG_SUPPORT_VFAT
102
wdenkc837dcb2004-01-20 23:12:12 +0000103#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenkc6097192002-11-03 00:24:07 +0000104
wdenkc837dcb2004-01-20 23:12:12 +0000105#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenkc6097192002-11-03 00:24:07 +0000106
107/*
108 * Miscellaneous configurable options
109 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_LONGHELP /* undef to save memory */
111#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenkc6097192002-11-03 00:24:07 +0000112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
114#ifdef CONFIG_SYS_HUSH_PARSER
115#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkc6097192002-11-03 00:24:07 +0000116#endif
117
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500118#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000120#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000122#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
124#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
125#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
wdenkc6097192002-11-03 00:24:07 +0000128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenkc6097192002-11-03 00:24:07 +0000130
stroesea20b27a2004-12-16 18:05:42 +0000131#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
134#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_BASE_BAUD 691200
wdenkc6097192002-11-03 00:24:07 +0000138
139/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +0000141 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
142 57600, 115200, 230400, 460800, 921600 }
wdenkc6097192002-11-03 00:24:07 +0000143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
145#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenkc6097192002-11-03 00:24:07 +0000146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc6097192002-11-03 00:24:07 +0000148
Matthias Fuchsac53ee82008-09-05 15:34:04 +0200149#define CONFIG_CMDLINE_EDITING /* add command line history */
150
stroesea20b27a2004-12-16 18:05:42 +0000151#define CONFIG_LOOPW 1 /* enable loopw command */
152
wdenkc6097192002-11-03 00:24:07 +0000153#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
154
wdenkc837dcb2004-01-20 23:12:12 +0000155#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroese9e7d5eb2003-04-04 16:48:07 +0000156
Matthias Fuchs75511b42009-02-20 10:19:14 +0100157#define CONFIG_AUTOBOOT_KEYED 1
158#define CONFIG_AUTOBOOT_PROMPT \
159 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
160#undef CONFIG_AUTOBOOT_DELAY_STR
161#define CONFIG_AUTOBOOT_STOP_STR " "
162
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroese53cf9432003-06-05 15:39:44 +0000164
wdenkc6097192002-11-03 00:24:07 +0000165/*-----------------------------------------------------------------------
166 * PCI stuff
167 *-----------------------------------------------------------------------
168 */
stroesea20b27a2004-12-16 18:05:42 +0000169#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
170#define PCI_HOST_FORCE 1 /* configure as pci host */
171#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenkc6097192002-11-03 00:24:07 +0000172
stroesea20b27a2004-12-16 18:05:42 +0000173#define CONFIG_PCI /* include pci support */
174#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
175#define CONFIG_PCI_PNP /* do pci plug-and-play */
176 /* resource configuration */
wdenkc6097192002-11-03 00:24:07 +0000177
stroesea20b27a2004-12-16 18:05:42 +0000178#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
wdenkc6097192002-11-03 00:24:07 +0000179
stroesea20b27a2004-12-16 18:05:42 +0000180#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
stroesead10dd92003-02-14 11:21:23 +0000181
stroesea20b27a2004-12-16 18:05:42 +0000182#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
185#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
186#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
187#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
188#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
189#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
190#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
191#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
192#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
193#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000194
195/*-----------------------------------------------------------------------
196 * IDE/ATA stuff
197 *-----------------------------------------------------------------------
198 */
wdenkc837dcb2004-01-20 23:12:12 +0000199#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
200#undef CONFIG_IDE_LED /* no led for ide supported */
wdenkc6097192002-11-03 00:24:07 +0000201#define CONFIG_IDE_RESET 1 /* reset for ide supported */
202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
204#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
wdenkc6097192002-11-03 00:24:07 +0000205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
207#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkc6097192002-11-03 00:24:07 +0000208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
210#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
211#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
wdenkc6097192002-11-03 00:24:07 +0000212
213/*-----------------------------------------------------------------------
214 * Start addresses for the final memory configuration
215 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000217 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_SDRAM_BASE 0x00000000
219#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
220#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
221#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
222#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000223
Matthias Fuchs3ba605d2009-01-02 12:18:49 +0100224#define CONFIG_PRAM 0 /* use pram variable to overwrite */
225
wdenkc6097192002-11-03 00:24:07 +0000226/*
227 * For booting Linux, the board info and command line data
228 * have to be in the first 8 MB of memory, since this is
229 * the maximum mapped by the Linux kernel during initialization.
230 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Matthias Fuchsac53ee82008-09-05 15:34:04 +0200232
233#define CONFIG_OF_LIBFDT
234#define CONFIG_OF_BOARD_SETUP
235
wdenkc6097192002-11-03 00:24:07 +0000236/*-----------------------------------------------------------------------
237 * FLASH organization
238 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
240#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkc6097192002-11-03 00:24:07 +0000241
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
243#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
246#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
247#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenkc6097192002-11-03 00:24:07 +0000248/*
249 * The following defines are added for buggy IOP480 byte interface.
250 * All other boards should use the standard values (CPCI405 etc.)
251 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
253#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
254#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
wdenkc6097192002-11-03 00:24:07 +0000255
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenkc6097192002-11-03 00:24:07 +0000257
wdenkc6097192002-11-03 00:24:07 +0000258#if 0 /* Use NVRAM for environment variables */
259/*-----------------------------------------------------------------------
260 * NVRAM organization
261 */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200262#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200263#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
264#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */
wdenkc6097192002-11-03 00:24:07 +0000266
267#else /* Use EEPROM for environment variables */
268
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200269#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200270#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
271#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
wdenk8bde7f72003-06-27 21:31:46 +0000272 /* total size of a CAT24WC16 is 2048 bytes */
wdenkc6097192002-11-03 00:24:07 +0000273#endif
274
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
276#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
277#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
wdenkc6097192002-11-03 00:24:07 +0000278
279/*-----------------------------------------------------------------------
280 * I2C EEPROM (CAT24WC16) for environment
281 */
282#define CONFIG_HARD_I2C /* I2c with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
284#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenkc6097192002-11-03 00:24:07 +0000285
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
287#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenkc837dcb2004-01-20 23:12:12 +0000288/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
290#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
wdenkc6097192002-11-03 00:24:07 +0000291 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000292 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkc6097192002-11-03 00:24:07 +0000294
wdenkc6097192002-11-03 00:24:07 +0000295/*
296 * Init Memory Controller:
297 *
298 * BR0/1 and OR0/1 (FLASH)
299 */
300
301#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
302#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
303
304/*-----------------------------------------------------------------------
305 * External Bus Controller (EBC) Setup
306 */
307
wdenkc837dcb2004-01-20 23:12:12 +0000308/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_EBC_PB0AP 0x92015480
310#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000311
wdenkc837dcb2004-01-20 23:12:12 +0000312/* Memory Bank 1 (Flash Bank 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_EBC_PB1AP 0x92015480
314#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000315
wdenkc837dcb2004-01-20 23:12:12 +0000316/* Memory Bank 2 (CAN0, 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
318#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
319#define CONFIG_SYS_LED_ADDR 0xF0000380
wdenkc6097192002-11-03 00:24:07 +0000320
wdenkc837dcb2004-01-20 23:12:12 +0000321/* Memory Bank 3 (CompactFlash IDE) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
323#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000324
wdenkc837dcb2004-01-20 23:12:12 +0000325/* Memory Bank 4 (NVRAM/RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326/*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
327#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
328#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000329
wdenkc837dcb2004-01-20 23:12:12 +0000330/* Memory Bank 5 (optional Quart) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
332#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000333
wdenkc837dcb2004-01-20 23:12:12 +0000334/* Memory Bank 6 (FPGA internal) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
336#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
337#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
wdenkc6097192002-11-03 00:24:07 +0000338
339/*-----------------------------------------------------------------------
340 * FPGA stuff
341 */
342/* FPGA internal regs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_FPGA_MODE 0x00
344#define CONFIG_SYS_FPGA_STATUS 0x02
345#define CONFIG_SYS_FPGA_TS 0x04
346#define CONFIG_SYS_FPGA_TS_LOW 0x06
347#define CONFIG_SYS_FPGA_TS_CAP0 0x10
348#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
349#define CONFIG_SYS_FPGA_TS_CAP1 0x14
350#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
351#define CONFIG_SYS_FPGA_TS_CAP2 0x18
352#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
353#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
354#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
wdenkc6097192002-11-03 00:24:07 +0000355
356/* FPGA Mode Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
358#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
359#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
360#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
361#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
362#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
wdenkc6097192002-11-03 00:24:07 +0000363
364/* FPGA Status Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
366#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
367#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
368#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
369#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
wdenkc6097192002-11-03 00:24:07 +0000370
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
372#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
wdenkc6097192002-11-03 00:24:07 +0000373
374/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
376#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
377#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
378#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
379#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
wdenkc6097192002-11-03 00:24:07 +0000380
381/*-----------------------------------------------------------------------
382 * Definitions for initial stack pointer and data area (in data cache)
383 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
wdenkc6097192002-11-03 00:24:07 +0000385
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
387#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
388#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
389#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
390#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000391
392
393/*
394 * Internal Definitions
395 *
396 * Boot Flags
397 */
398#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
399#define BOOTFLAG_WARM 0x02 /* Software reboot */
400
401#endif /* __CONFIG_H */