blob: 4533799971c4b989f30e9fe96bfec951f10aa959 [file] [log] [blame]
Dirk Eibachb209a112009-07-17 14:16:40 +02001/*
2 * (C) Copyright 2009
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27#define CONFIG_405EP 1 /* this is a PPC405 CPU */
28#define CONFIG_4xx 1 /* member of PPC4xx family */
29#define CONFIG_DLVISION 1 /* on a Neo board */
30
31/*
32 * Include common defines/options for all AMCC eval boards
33 */
34#define CONFIG_HOSTNAME dlvision
35#define CONFIG_IDENT_STRING " dlvision 0.01"
36#include "amcc-common.h"
37
38#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
39#define CONFIG_MISC_INIT_R /* call misc_init_r */
40
41#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
42
43/*
44 * Configure PLL
45 */
46#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
47#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
48
49/* new uImage format support */
50#define CONFIG_FIT
51#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
52
53#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
54
55/*
56 * Default environment variables
57 */
58#define CONFIG_EXTRA_ENV_SETTINGS \
59 CONFIG_AMCC_DEF_ENV \
60 CONFIG_AMCC_DEF_ENV_POWERPC \
61 CONFIG_AMCC_DEF_ENV_NOR_UPD \
62 "kernel_addr=fc000000\0" \
63 "fdt_addr=fc1e0000\0" \
64 "ramdisk_addr=fc200000\0" \
65 ""
66
67#define CONFIG_PHY_ADDR 4 /* PHY address */
68#define CONFIG_HAS_ETH0
69#define CONFIG_HAS_ETH1
70#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
71#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
72
73/*
74 * Commands additional to the ones defined in amcc-common.h
75 */
76#define CONFIG_CMD_CACHE
77#undef CONFIG_CMD_EEPROM
78
79/*
80 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
81 */
82#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
83
84/* SDRAM timings used in datasheet */
85#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
86#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
87#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
88#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
89#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
90
91/*
92 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
93 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
94 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
95 * The Linux BASE_BAUD define should match this configuration.
96 * baseBaud = cpuClock/(uartDivisor*16)
97 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
98 * set Linux BASE_BAUD to 403200.
99 */
100#undef CONFIG_SERIAL_SOFTWARE_FIFO
101#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
102#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
103#define CONFIG_SYS_BASE_BAUD 691200
104
105/*
106 * I2C stuff
107 */
108#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address*/
109
110/*
111 * FLASH organization
112 */
113#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
114#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
115
116#define CONFIG_SYS_FLASH_BASE 0xFC000000
117#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
118
119#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
120#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
121
122#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
123#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
124
125#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
126#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */
127
128#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
129#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
130
131#ifdef CONFIG_ENV_IS_IN_FLASH
132#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
133#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
134#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
135
136/* Address and size of Redundant Environment Sector */
137#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
138#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
139#endif
140
141/*
142 * PPC405 GPIO Configuration
143 */
144#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
145{ \
146/* GPIO Core 0 */ \
147{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
148{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
149{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
150{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
151{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
152{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
153{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
154{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
155{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
156{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
157{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
158{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
159{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
160{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
161{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
162{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
163{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
164{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
165{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
166{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
167{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
168{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
169{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
170{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
171{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
172{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
173{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
174{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
175{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
176{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
177{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
178{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
179} \
180}
181
182/*
183 * Definitions for initial stack pointer and data area (in data cache)
184 */
185/* use on chip memory (OCM) for temperary stack until sdram is tested */
186#define CONFIG_SYS_TEMP_STACK_OCM 1
187
188/* On Chip Memory location */
189#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
190#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
191#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
192#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
193
194#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
195#define CONFIG_SYS_GBL_DATA_OFFSET \
196 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
197#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
198
199/*
200 * External Bus Controller (EBC) Setup
201 */
202
203/* Memory Bank 0 (NOR-FLASH) initialization */
204#define CONFIG_SYS_EBC_PB0AP 0x92015480
205/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
206#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
207
208/* Memory Bank 1 (NVRAM) initializatio */
209#define CONFIG_SYS_EBC_PB1AP 0x92015480
210/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
211#define CONFIG_SYS_EBC_PB1CR 0xFB858000
212
213/* Memory Bank 2 (UART) initialization */
214#define CONFIG_UART_BASE 0x7f100000
215#define CONFIG_SYS_EBC_PB2AP 0x92015480
216/* BAS=0x7f1,BS=1MB,BU=R/W,BW=8bit */
217#define CONFIG_SYS_EBC_PB2CR 0x7f118000
218
219/* Memory Bank 3 (Latches) initialization */
220#define CONFIG_SYS_LATCH_BASE 0x7f200000
221#define CONFIG_SYS_EBC_PB3AP 0x92015480
222/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
223#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
224
225#endif /* __CONFIG_H */