Eugen Hristev | 1d463d6 | 2020-03-10 11:56:38 +0200 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_AT91=y |
| 3 | CONFIG_SYS_TEXT_BASE=0x66f00000 |
| 4 | CONFIG_TARGET_SAMA7G5EK=y |
Claudiu Beznea | 86eeab7 | 2020-06-02 15:14:14 +0300 | [diff] [blame] | 5 | CONFIG_SYS_MALLOC_F_LEN=0x11000 |
Eugen Hristev | 0f8904b | 2020-07-30 16:22:53 +0300 | [diff] [blame] | 6 | CONFIG_NR_DRAM_BANKS=1 |
Tom Rini | 472a716 | 2021-01-29 13:56:04 -0500 | [diff] [blame] | 7 | CONFIG_SYS_MEMTEST_START=0x60000000 |
| 8 | CONFIG_SYS_MEMTEST_END=0x70000000 |
Eugen Hristev | 1d463d6 | 2020-03-10 11:56:38 +0200 | [diff] [blame] | 9 | CONFIG_ENV_SIZE=0x4000 |
Eugen Hristev | 0f8904b | 2020-07-30 16:22:53 +0300 | [diff] [blame] | 10 | CONFIG_DM_GPIO=y |
Eugen Hristev | 1d463d6 | 2020-03-10 11:56:38 +0200 | [diff] [blame] | 11 | CONFIG_DEBUG_UART_BOARD_INIT=y |
| 12 | CONFIG_DEBUG_UART_BASE=0xe1824200 |
| 13 | CONFIG_DEBUG_UART_CLOCK=200000000 |
| 14 | CONFIG_DEFAULT_DEVICE_TREE="sama7g5ek" |
| 15 | CONFIG_DEBUG_UART=y |
| 16 | CONFIG_ENV_VARS_UBOOT_CONFIG=y |
| 17 | CONFIG_FIT=y |
| 18 | CONFIG_SD_BOOT=y |
| 19 | CONFIG_USE_BOOTARGS=y |
Eugen Hristev | 0f8904b | 2020-07-30 16:22:53 +0300 | [diff] [blame] | 20 | CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk1p2 rw rootwait" |
Eugen Hristev | 1d463d6 | 2020-03-10 11:56:38 +0200 | [diff] [blame] | 21 | CONFIG_MISC_INIT_R=y |
| 22 | CONFIG_HUSH_PARSER=y |
Eugen Hristev | 1d463d6 | 2020-03-10 11:56:38 +0200 | [diff] [blame] | 23 | CONFIG_CMD_BOOTZ=y |
| 24 | # CONFIG_CMD_IMI is not set |
| 25 | CONFIG_CMD_MD5SUM=y |
| 26 | CONFIG_CMD_MEMTEST=y |
Eugen Hristev | 1d463d6 | 2020-03-10 11:56:38 +0200 | [diff] [blame] | 27 | CONFIG_CMD_STRINGS=y |
| 28 | CONFIG_CMD_DM=y |
| 29 | CONFIG_CMD_GPIO=y |
| 30 | CONFIG_CMD_I2C=y |
| 31 | # CONFIG_CMD_LOADS is not set |
| 32 | CONFIG_CMD_MMC=y |
| 33 | CONFIG_CMD_DHCP=y |
Claudiu Beznea | 02dae80 | 2020-06-09 13:49:12 +0300 | [diff] [blame] | 34 | CONFIG_CMD_MII=y |
Eugen Hristev | 1d463d6 | 2020-03-10 11:56:38 +0200 | [diff] [blame] | 35 | CONFIG_CMD_PING=y |
| 36 | CONFIG_CMD_EXT4=y |
| 37 | CONFIG_CMD_FAT=y |
| 38 | CONFIG_OF_CONTROL=y |
| 39 | CONFIG_ENV_IS_IN_FAT=y |
Eugen Hristev | 0f8904b | 2020-07-30 16:22:53 +0300 | [diff] [blame] | 40 | CONFIG_ENV_FAT_DEVICE_AND_PART="1:1" |
Eugen Hristev | 1d463d6 | 2020-03-10 11:56:38 +0200 | [diff] [blame] | 41 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 42 | CONFIG_DM=y |
| 43 | CONFIG_CLK=y |
Claudiu Beznea | b17a268 | 2020-06-02 15:15:55 +0300 | [diff] [blame] | 44 | CONFIG_CLK_CCF=y |
Eugen Hristev | 1d463d6 | 2020-03-10 11:56:38 +0200 | [diff] [blame] | 45 | CONFIG_CLK_AT91=y |
| 46 | CONFIG_AT91_UTMI=y |
| 47 | CONFIG_AT91_GENERIC_CLK=y |
Claudiu Beznea | 3a2be10 | 2020-06-02 15:15:25 +0300 | [diff] [blame] | 48 | CONFIG_AT91_SAM9X60_PLL=y |
Claudiu Beznea | 2942a2f | 2020-06-02 15:35:12 +0300 | [diff] [blame] | 49 | CONFIG_CPU=y |
Eugen Hristev | 1d463d6 | 2020-03-10 11:56:38 +0200 | [diff] [blame] | 50 | CONFIG_ATMEL_PIO4=y |
| 51 | CONFIG_DM_I2C=y |
Eugen Hristev | 05176cd | 2020-07-31 15:21:45 +0300 | [diff] [blame] | 52 | CONFIG_SYS_I2C_AT91=y |
| 53 | CONFIG_I2C_EEPROM=y |
| 54 | CONFIG_MICROCHIP_FLEXCOM=y |
Eugen Hristev | 1d463d6 | 2020-03-10 11:56:38 +0200 | [diff] [blame] | 55 | CONFIG_DM_MMC=y |
| 56 | CONFIG_MMC_SDHCI=y |
| 57 | CONFIG_MMC_SDHCI_ATMEL=y |
Claudiu Beznea | a507782 | 2020-06-09 13:48:26 +0300 | [diff] [blame] | 58 | CONFIG_PHY_MICREL=y |
| 59 | CONFIG_PHY_MICREL_KSZ90X1=y |
Eugen Hristev | 1d463d6 | 2020-03-10 11:56:38 +0200 | [diff] [blame] | 60 | CONFIG_DM_ETH=y |
| 61 | CONFIG_MACB=y |
| 62 | CONFIG_PINCTRL=y |
| 63 | CONFIG_PINCTRL_AT91PIO4=y |
Eugen Hristev | 1d463d6 | 2020-03-10 11:56:38 +0200 | [diff] [blame] | 64 | CONFIG_DM_SERIAL=y |
| 65 | CONFIG_DEBUG_UART_ANNOUNCE=y |
| 66 | CONFIG_ATMEL_USART=y |
| 67 | CONFIG_TIMER=y |
Claudiu Beznea | dd2cf75 | 2020-06-02 18:42:59 +0300 | [diff] [blame] | 68 | CONFIG_MCHP_PIT64B_TIMER=y |
Eugen Hristev | 1d463d6 | 2020-03-10 11:56:38 +0200 | [diff] [blame] | 69 | CONFIG_OF_LIBFDT_OVERLAY=y |
| 70 | # CONFIG_EFI_LOADER_HII is not set |