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Mingkai Hu435acd82015-10-26 19:47:41 +08001/*
2 * Copyright 2015 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 *
6 */
7
8#ifndef __FSL_CSU_H__
9#define __FSL_CSU_H__
10
11enum csu_cslx_access {
12 CSU_NS_SUP_R = 0x08,
13 CSU_NS_SUP_W = 0x80,
14 CSU_NS_SUP_RW = 0x88,
15 CSU_NS_USER_R = 0x04,
16 CSU_NS_USER_W = 0x40,
17 CSU_NS_USER_RW = 0x44,
18 CSU_S_SUP_R = 0x02,
19 CSU_S_SUP_W = 0x20,
20 CSU_S_SUP_RW = 0x22,
21 CSU_S_USER_R = 0x01,
22 CSU_S_USER_W = 0x10,
23 CSU_S_USER_RW = 0x11,
24 CSU_ALL_RW = 0xff,
25};
26
27struct csu_ns_dev {
28 unsigned long ind;
29 uint32_t val;
30};
31
32void enable_layerscape_ns_access(void);
Hou Zhiqiangacb90e82017-07-03 17:51:10 +080033void set_devices_ns_access(unsigned long, u16 val);
Hou Zhiqiang664b6522016-08-02 19:03:26 +080034void set_pcie_ns_access(int pcie, u16 val);
Mingkai Hu435acd82015-10-26 19:47:41 +080035
36#endif