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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Tom Warrenf01b6312012-12-11 13:34:18 +00002/*
3 * (C) Copyright 2010-2012
4 * NVIDIA Corporation <www.nvidia.com>
Tom Warrenf01b6312012-12-11 13:34:18 +00005 */
6
7#ifndef _TEGRA30_COMMON_H_
8#define _TEGRA30_COMMON_H_
9#include "tegra-common.h"
10
11/*
12 * NS16550 Configuration
13 */
14#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
15
Tom Warrenf01b6312012-12-11 13:34:18 +000016/*
17 * Miscellaneous configurable options
18 */
Jonathan Hunterf16e3112019-02-12 16:03:14 +000019#define CONFIG_STACKBASE 0x83800000 /* 56MB */
Tom Warrenf01b6312012-12-11 13:34:18 +000020
Tom Warrenf01b6312012-12-11 13:34:18 +000021/*
22 * Memory layout for where various images get loaded by boot scripts:
23 *
24 * scriptaddr can be pretty much anywhere that doesn't conflict with something
25 * else. Put it above BOOTMAPSZ to eliminate conflicts.
26 *
Stephen Warrenf940c722014-02-05 09:24:59 -070027 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
28 * something else. Put it above BOOTMAPSZ to eliminate conflicts.
29 *
Tom Warrenf01b6312012-12-11 13:34:18 +000030 * kernel_addr_r must be within the first 128M of RAM in order for the
31 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
32 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
33 * should not overlap that area, or the kernel will have to copy itself
34 * somewhere else before decompression. Similarly, the address of any other
35 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
Jonathan Hunterf16e3112019-02-12 16:03:14 +000036 * this up to 32M allows for a sizable kernel to be decompressed below the
Tom Warrenf01b6312012-12-11 13:34:18 +000037 * compressed load address.
38 *
Jonathan Hunterf16e3112019-02-12 16:03:14 +000039 * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
40 * the compressed kernel to be up to 32M too.
Tom Warrenf01b6312012-12-11 13:34:18 +000041 *
Jonathan Hunterf16e3112019-02-12 16:03:14 +000042 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
Tom Warrenf01b6312012-12-11 13:34:18 +000043 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
44 */
Stephen Warren48cfca22015-04-01 15:40:53 -060045#define CONFIG_LOADADDR 0x81000000
Tom Warrenf01b6312012-12-11 13:34:18 +000046#define MEM_LAYOUT_ENV_SETTINGS \
47 "scriptaddr=0x90000000\0" \
Stephen Warrenf940c722014-02-05 09:24:59 -070048 "pxefile_addr_r=0x90100000\0" \
Stephen Warren48cfca22015-04-01 15:40:53 -060049 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
Jonathan Hunterf16e3112019-02-12 16:03:14 +000050 "fdt_addr_r=0x83000000\0" \
51 "ramdisk_addr_r=0x83100000\0"
Tom Warrenf01b6312012-12-11 13:34:18 +000052
53/* Defines for SPL */
Tom Warrenf01b6312012-12-11 13:34:18 +000054#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
55#define CONFIG_SPL_STACK 0x800ffffc
56
Jim Lind6cf7072013-06-21 19:05:48 +080057/* For USB EHCI controller */
58#define CONFIG_EHCI_IS_TDI
Jim Lin81d21e92013-11-06 14:03:44 +080059#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
Jim Lind6cf7072013-06-21 19:05:48 +080060
Tom Warrenf01b6312012-12-11 13:34:18 +000061#endif /* _TEGRA30_COMMON_H_ */