blob: 4744f08c9ad56729bb4fae85b3f53b62e73b71c5 [file] [log] [blame]
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +00001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +00005 */
6
7/*
8 * BSC9132 QDS board configuration file
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
harninder rai4aafbb42014-12-02 15:55:47 +053014#define CONFIG_DISPLAY_BOARDINFO
15
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000016#ifdef CONFIG_BSC9132QDS
17#define CONFIG_BSC9132
18#endif
19
20#define CONFIG_MISC_INIT_R
21
22#ifdef CONFIG_SDCARD
23#define CONFIG_RAMBOOT_SDCARD
24#define CONFIG_SYS_RAMBOOT
25#define CONFIG_SYS_EXTRA_ENV_RELOC
26#define CONFIG_SYS_TEXT_BASE 0x11000000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053027#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000028#endif
29#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1
30#ifdef CONFIG_SPIFLASH
31#define CONFIG_RAMBOOT_SPIFLASH
32#define CONFIG_SYS_RAMBOOT
33#define CONFIG_SYS_EXTRA_ENV_RELOC
34#define CONFIG_SYS_TEXT_BASE 0x11000000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053035#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000036#endif
Aneesh Bansalbea3cbb2014-03-12 22:00:18 +053037#ifdef CONFIG_NAND_SECBOOT
38#define CONFIG_RAMBOOT_NAND
39#define CONFIG_SYS_RAMBOOT
40#define CONFIG_SYS_EXTRA_ENV_RELOC
41#define CONFIG_SYS_TEXT_BASE 0x11000000
42#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
43#endif
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000044
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +053045#ifdef CONFIG_NAND
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +053046#define CONFIG_SPL_INIT_MINIMAL
47#define CONFIG_SPL_SERIAL_SUPPORT
48#define CONFIG_SPL_NAND_SUPPORT
Prabhakar Kushwahafbe76ae2013-12-11 12:42:11 +053049#define CONFIG_SPL_NAND_BOOT
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +053050#define CONFIG_SPL_FLUSH_IMAGE
51#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
52
53#define CONFIG_SYS_TEXT_BASE 0x00201000
54#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
55#define CONFIG_SPL_MAX_SIZE 8192
56#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
57#define CONFIG_SPL_RELOC_STACK 0x00100000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053058#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +053059#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
60#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
61#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
62#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
63#endif
64
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000065#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053066#define CONFIG_SYS_TEXT_BASE 0x8ff40000
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000067#endif
68
69#ifndef CONFIG_RESET_VECTOR_ADDRESS
70#define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc
71#endif
72
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +053073#ifdef CONFIG_SPL_BUILD
74#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
75#else
76#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000077#endif
78
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000079/* High Level Configuration Options */
80#define CONFIG_BOOKE /* BOOKE */
81#define CONFIG_E500 /* BOOKE e500 family */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000082#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +053083#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000084#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
85
86#define CONFIG_PCI /* Enable PCI/PCIE */
87#if defined(CONFIG_PCI)
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040088#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000089#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000090#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000091#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
92#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
93
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000094#define CONFIG_CMD_PCI
95
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000096/*
97 * PCI Windows
98 * Memory space is mapped 1-1, but I/O space must start from 0.
99 */
100/* controller 1, Slot 1, tgtid 1, Base address a000 */
101#define CONFIG_SYS_PCIE1_NAME "PCIe Slot"
102#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
103#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
104#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
105#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
106#define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000
107#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
108#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
109#define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000
110
111#define CONFIG_PCI_PNP /* do pci plug-and-play */
112
113#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
114#define CONFIG_DOS_PARTITION
115#endif
116
117#define CONFIG_FSL_LAW /* Use common FSL init code */
118#define CONFIG_ENV_OVERWRITE
119#define CONFIG_TSEC_ENET /* ethernet */
120
121#if defined(CONFIG_SYS_CLK_100_DDR_100)
122#define CONFIG_SYS_CLK_FREQ 100000000
123#define CONFIG_DDR_CLK_FREQ 100000000
124#elif defined(CONFIG_SYS_CLK_100_DDR_133)
125#define CONFIG_SYS_CLK_FREQ 100000000
126#define CONFIG_DDR_CLK_FREQ 133000000
127#endif
128
129#define CONFIG_MP
130
131#define CONFIG_HWCONFIG
132/*
133 * These can be toggled for performance analysis, otherwise use default.
134 */
135#define CONFIG_L2_CACHE /* toggle L2 cache */
136#define CONFIG_BTB /* enable branch predition */
137
138#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
139#define CONFIG_SYS_MEMTEST_END 0x01ffffff
140
141/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -0700142#define CONFIG_SYS_FSL_DDR3
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000143#define CONFIG_SYS_SPD_BUS_NUM 0
144#define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
145#define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
146#define CONFIG_FSL_DDR_INTERACTIVE
147
148#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
149
150#define CONFIG_SYS_SDRAM_SIZE (1024)
151#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
152#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
153
154#define CONFIG_DIMM_SLOTS_PER_CTLR 1
155
156/* DDR3 Controller Settings */
157#define CONFIG_CHIP_SELECTS_PER_CTRL 1
158#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
159#define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302
160#define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302
161#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
162#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
163#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
164#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
165#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
166#define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F
167
168#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
169#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
170#define CONFIG_SYS_DDR_RCW_1 0x00000000
171#define CONFIG_SYS_DDR_RCW_2 0x00000000
172#define CONFIG_SYS_DDR_CONTROL_800 0x470C0000
173#define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050
174#define CONFIG_SYS_DDR_TIMING_4_800 0x00220001
175#define CONFIG_SYS_DDR_TIMING_5_800 0x03402400
176
177#define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008
178#define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010
179#define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001
180#define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400
181
182#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
183#define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
184#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846
185#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF
186#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
187#define CONFIG_SYS_DDR_MODE_1_800 0x40461520
188#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
189#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000
190#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
191
192#define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000
193#define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104
194#define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45
195#define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114
196#define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000
197#define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50
198#define CONFIG_SYS_DDR_MODE_2_1333 0x00100000
199#define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513
200#define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607
201
202/*FIXME: the following params are constant w.r.t diff freq
203combinations. this should be removed later
204*/
205#if CONFIG_DDR_CLK_FREQ == 100000000
206#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
207#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
208#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
209#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
210#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
211#elif CONFIG_DDR_CLK_FREQ == 133000000
212#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
213#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333
214#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333
215#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
216#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
217#else
218#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
219#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
220#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
221#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
222#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
223#endif
224
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000225/* relocated CCSRBAR */
226#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
227#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
228
229#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
230
Priyanka Jain64501c62013-07-02 09:21:04 +0530231/* DSP CCSRBAR */
232#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
233#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
234
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000235/*
236 * IFC Definitions
237 */
238/* NOR Flash on IFC */
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530239
240#ifdef CONFIG_SPL_BUILD
241#define CONFIG_SYS_NO_FLASH
242#endif
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000243#define CONFIG_SYS_FLASH_BASE 0x88000000
244#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */
245
246#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
247
248#define CONFIG_SYS_NOR_CSPR 0x88000101
249#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
250#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5)
251/* NOR Flash Timing Params */
252
253#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \
254 | FTIM0_NOR_TEADC(0x03) \
255 | FTIM0_NOR_TAVDS(0x00) \
256 | FTIM0_NOR_TEAHC(0x0f))
257#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \
258 | FTIM1_NOR_TRAD_NOR(0x09) \
259 | FTIM1_NOR_TSEQRAD_NOR(0x09))
260#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \
261 | FTIM2_NOR_TCH(0x4) \
262 | FTIM2_NOR_TWPH(0x7) \
263 | FTIM2_NOR_TWP(0x1e))
264#define CONFIG_SYS_NOR_FTIM3 0x0
265
266#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
267#define CONFIG_SYS_FLASH_QUIET_TEST
268#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
269#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
270
271#undef CONFIG_SYS_FLASH_CHECKSUM
272#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
273#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
274
275/* CFI for NOR Flash */
276#define CONFIG_FLASH_CFI_DRIVER
277#define CONFIG_SYS_FLASH_CFI
278#define CONFIG_SYS_FLASH_EMPTY_INFO
279#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
280
281/* NAND Flash on IFC */
282#define CONFIG_SYS_NAND_BASE 0xff800000
283#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
284
285#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
286 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
287 | CSPR_MSEL_NAND /* MSEL = NAND */ \
288 | CSPR_V)
289#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
290
291#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
292 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
293 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
294 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
295 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
296 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
297 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
298
299/* NAND Flash Timing Params */
300#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
301 | FTIM0_NAND_TWP(0x05) \
302 | FTIM0_NAND_TWCHT(0x02) \
303 | FTIM0_NAND_TWH(0x04))
304#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \
305 | FTIM1_NAND_TWBE(0x1e) \
306 | FTIM1_NAND_TRR(0x07) \
307 | FTIM1_NAND_TRP(0x05))
308#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
309 | FTIM2_NAND_TREH(0x04) \
310 | FTIM2_NAND_TWHRE(0x11))
311#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
312
313#define CONFIG_SYS_NAND_DDR_LAW 11
314
315/* NAND */
316#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
317#define CONFIG_SYS_MAX_NAND_DEVICE 1
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000318#define CONFIG_CMD_NAND
319
320#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
321
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530322#ifndef CONFIG_SPL_BUILD
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000323#define CONFIG_FSL_QIXIS
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530324#endif
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000325#ifdef CONFIG_FSL_QIXIS
326#define CONFIG_SYS_FPGA_BASE 0xffb00000
327#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
328#define QIXIS_BASE CONFIG_SYS_FPGA_BASE
329#define QIXIS_LBMAP_SWITCH 9
330#define QIXIS_LBMAP_MASK 0x07
331#define QIXIS_LBMAP_SHIFT 0
332#define QIXIS_LBMAP_DFLTBANK 0x00
333#define QIXIS_LBMAP_ALTBANK 0x04
334#define QIXIS_RST_CTL_RESET 0x83
335#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
336#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
337#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
338
339#define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE
340
341#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
342 | CSPR_PORT_SIZE_8 \
343 | CSPR_MSEL_GPCM \
344 | CSPR_V)
345#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
346#define CONFIG_SYS_CSOR2 0x0
347/* CPLD Timing parameters for IFC CS3 */
348#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
349 FTIM0_GPCM_TEADC(0x0e) | \
350 FTIM0_GPCM_TEAHC(0x0e))
351#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
352 FTIM1_GPCM_TRAD(0x1f))
353#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiede519162014-06-26 14:41:33 +0800354 FTIM2_GPCM_TCH(0x8) | \
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000355 FTIM2_GPCM_TWP(0x1f))
356#define CONFIG_SYS_CS2_FTIM3 0x0
357#endif
358
359/* Set up IFC registers for boot location NOR/NAND */
Aneesh Bansal3051f3f2014-05-14 11:45:15 +0530360#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530361#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
362#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
363#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
364#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
365#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
366#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
367#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
368#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
369#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
370#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
371#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
372#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
373#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
374#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
375#else
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000376#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
377#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
378#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
379#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
380#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
381#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
382#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
383#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
384#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
385#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
386#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
387#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
388#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
389#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530390#endif
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000391
392#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
393#define CONFIG_BOARD_EARLY_INIT_R
394
395#define CONFIG_SYS_INIT_RAM_LOCK
396#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
York Sunb39d1212016-04-06 13:22:10 -0700397#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000398
York Sunb39d1212016-04-06 13:22:10 -0700399#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000400 - GENERATED_GBL_DATA_SIZE)
401#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
402
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530403#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000404#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
405
406/* Serial Port */
407#define CONFIG_CONS_INDEX 1
408#undef CONFIG_SERIAL_SOFTWARE_FIFO
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000409#define CONFIG_SYS_NS16550_SERIAL
410#define CONFIG_SYS_NS16550_REG_SIZE 1
411#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530412#ifdef CONFIG_SPL_BUILD
413#define CONFIG_NS16550_MIN_FUNCTIONS
414#endif
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000415
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000416#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
417
418#define CONFIG_SYS_BAUDRATE_TABLE \
419 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
420
421#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
422#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
423#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
424#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
425
Heiko Schocher00f792e2012-10-24 13:48:22 +0200426#define CONFIG_SYS_I2C
427#define CONFIG_SYS_I2C_FSL
428#define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/
429#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
430#define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/
431#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
432#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
433#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000434
435/* I2C EEPROM */
436#define CONFIG_ID_EEPROM
437#ifdef CONFIG_ID_EEPROM
438#define CONFIG_SYS_I2C_EEPROM_NXID
439#endif
440#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
441#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
442#define CONFIG_SYS_EEPROM_BUS_NUM 0
443
444/* enable read and write access to EEPROM */
445#define CONFIG_CMD_EEPROM
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000446#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
447#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
448#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
449
450/* I2C FPGA */
451#define CONFIG_I2C_FPGA
452#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
453
454#define CONFIG_RTC_DS3231
455#define CONFIG_SYS_I2C_RTC_ADDR 0x68
456
457/*
458 * SPI interface will not be available in case of NAND boot SPI CS0 will be
459 * used for SLIC
460 */
461/* eSPI - Enhanced SPI */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000462#ifdef CONFIG_FSL_ESPI
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000463#define CONFIG_SF_DEFAULT_SPEED 10000000
464#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
465#endif
466
467#if defined(CONFIG_TSEC_ENET)
468
469#define CONFIG_MII /* MII PHY management */
470#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
471#define CONFIG_TSEC1 1
472#define CONFIG_TSEC1_NAME "eTSEC1"
473#define CONFIG_TSEC2 1
474#define CONFIG_TSEC2_NAME "eTSEC2"
475
476#define TSEC1_PHY_ADDR 0
477#define TSEC2_PHY_ADDR 1
478
479#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
480#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
481
482#define TSEC1_PHYIDX 0
483#define TSEC2_PHYIDX 0
484
485#define CONFIG_ETHPRIME "eTSEC1"
486
487#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
488
489/* TBI PHY configuration for SGMII mode */
490#define CONFIG_TSEC_TBICR_SETTINGS ( \
491 TBICR_PHY_RESET \
492 | TBICR_ANEG_ENABLE \
493 | TBICR_FULL_DUPLEX \
494 | TBICR_SPEED1_SET \
495 )
496
497#endif /* CONFIG_TSEC_ENET */
498
499#define CONFIG_MMC
500#ifdef CONFIG_MMC
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000501#define CONFIG_DOS_PARTITION
502#define CONFIG_FSL_ESDHC
503#define CONFIG_GENERIC_MMC
504#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
505#endif
506
507#define CONFIG_USB_EHCI /* USB */
508#ifdef CONFIG_USB_EHCI
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000509#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
510#define CONFIG_USB_EHCI_FSL
511#define CONFIG_USB_STORAGE
512#define CONFIG_HAS_FSL_DR_USB
513#endif
514
515/*
516 * Environment
517 */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000518#if defined(CONFIG_RAMBOOT_SDCARD)
519#define CONFIG_ENV_IS_IN_MMC
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530520#define CONFIG_FSL_FIXED_MMC_LOCATION
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000521#define CONFIG_SYS_MMC_ENV_DEV 0
522#define CONFIG_ENV_SIZE 0x2000
523#elif defined(CONFIG_RAMBOOT_SPIFLASH)
524#define CONFIG_ENV_IS_IN_SPI_FLASH
525#define CONFIG_ENV_SPI_BUS 0
526#define CONFIG_ENV_SPI_CS 0
527#define CONFIG_ENV_SPI_MAX_HZ 10000000
528#define CONFIG_ENV_SPI_MODE 0
529#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
530#define CONFIG_ENV_SECT_SIZE 0x10000
531#define CONFIG_ENV_SIZE 0x2000
Aneesh Bansalbea3cbb2014-03-12 22:00:18 +0530532#elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530533#define CONFIG_ENV_IS_IN_NAND
534#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530535#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530536#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
537#elif defined(CONFIG_SYS_RAMBOOT)
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000538#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
539#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
540#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000541#else
542#define CONFIG_ENV_IS_IN_FLASH
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000543#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000544#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530545#define CONFIG_ENV_SECT_SIZE 0x20000
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000546#endif
547
548#define CONFIG_LOADS_ECHO /* echo on for serial download */
549#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
550
551/*
552 * Command line configuration.
553 */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000554#define CONFIG_CMD_DATE
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000555#define CONFIG_CMD_ERRATA
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000556#define CONFIG_CMD_IRQ
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000557#define CONFIG_CMD_REGINFO
558
559#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000560#define CONFIG_DOS_PARTITION
561#endif
562
Ruchika Gupta737537e2014-10-15 11:35:31 +0530563/* Hash command with SHA acceleration supported in hardware */
564#ifdef CONFIG_FSL_CAAM
565#define CONFIG_CMD_HASH
566#define CONFIG_SHA_HW_ACCEL
567#endif
568
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000569/*
570 * Miscellaneous configurable options
571 */
572#define CONFIG_SYS_LONGHELP /* undef to save memory */
573#define CONFIG_CMDLINE_EDITING /* Command-line editing */
574#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
575#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000576
577#if defined(CONFIG_CMD_KGDB)
578#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
579#else
580#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
581#endif
582#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
583 /* Print Buffer Size */
584#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
585#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000586
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000587/*
588 * For booting Linux, the board info and command line data
589 * have to be in the first 64 MB of memory, since this is
590 * the maximum mapped by the Linux kernel during initialization.
591 */
592#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
593#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
594
595#if defined(CONFIG_CMD_KGDB)
596#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000597#endif
598
599/*
Ashish Kumar42a9e2f2014-10-06 18:24:56 +0530600 * Dynamic MTD Partition support with mtdparts
601 */
602#ifndef CONFIG_SYS_NO_FLASH
603#define CONFIG_MTD_DEVICE
604#define CONFIG_MTD_PARTITIONS
605#define CONFIG_CMD_MTDPARTS
606#define CONFIG_FLASH_CFI_MTD
607#define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash,"
608#define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \
609 "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \
610 "8m(kernel),512k(dtb),-(fs)"
611#endif
612/*
613 * Override partitions in device tree using info
614 * in "mtdparts" environment variable
615 */
616#ifdef CONFIG_CMD_MTDPARTS
617#define CONFIG_FDT_FIXUP_PARTITIONS
618#endif
619
620/*
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000621 * Environment Configuration
622 */
623
624#if defined(CONFIG_TSEC_ENET)
625#define CONFIG_HAS_ETH0
626#define CONFIG_HAS_ETH1
627#endif
628
629#define CONFIG_HOSTNAME BSC9132qds
630#define CONFIG_ROOTPATH "/opt/nfsroot"
631#define CONFIG_BOOTFILE "uImage"
632#define CONFIG_UBOOTPATH "u-boot.bin"
633
634#define CONFIG_BAUDRATE 115200
635
636#ifdef CONFIG_SDCARD
637#define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
638#else
639#define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
640#endif
641
642#define CONFIG_EXTRA_ENV_SETTINGS \
643 "netdev=eth0\0" \
644 "uboot=" CONFIG_UBOOTPATH "\0" \
645 "loadaddr=1000000\0" \
646 "bootfile=uImage\0" \
647 "consoledev=ttyS0\0" \
648 "ramdiskaddr=2000000\0" \
649 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500650 "fdtaddr=1e00000\0" \
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000651 "fdtfile=bsc9132qds.dtb\0" \
652 "bdev=sda1\0" \
653 CONFIG_DEF_HWCONFIG\
654 "othbootargs=mem=880M ramdisk_size=600000 " \
655 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
656 "isolcpus=0\0" \
657 "usbext2boot=setenv bootargs root=/dev/ram rw " \
658 "console=$consoledev,$baudrate $othbootargs; " \
659 "usb start;" \
660 "ext2load usb 0:4 $loadaddr $bootfile;" \
661 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
662 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
663 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
664 "debug_halt_off=mw ff7e0e30 0xf0000000;"
665
666#define CONFIG_NFSBOOTCOMMAND \
667 "setenv bootargs root=/dev/nfs rw " \
668 "nfsroot=$serverip:$rootpath " \
669 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
670 "console=$consoledev,$baudrate $othbootargs;" \
671 "tftp $loadaddr $bootfile;" \
672 "tftp $fdtaddr $fdtfile;" \
673 "bootm $loadaddr - $fdtaddr"
674
675#define CONFIG_HDBOOT \
676 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
677 "console=$consoledev,$baudrate $othbootargs;" \
678 "usb start;" \
679 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
680 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
681 "bootm $loadaddr - $fdtaddr"
682
683#define CONFIG_RAMBOOTCOMMAND \
684 "setenv bootargs root=/dev/ram rw " \
685 "console=$consoledev,$baudrate $othbootargs; " \
686 "tftp $ramdiskaddr $ramdiskfile;" \
687 "tftp $loadaddr $bootfile;" \
688 "tftp $fdtaddr $fdtfile;" \
689 "bootm $loadaddr $ramdiskaddr $fdtaddr"
690
691#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
692
Aneesh Bansalf978f7c2014-03-12 00:07:27 +0530693#include <asm/fsl_secure_boot.h>
694
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000695#endif /* __CONFIG_H */