blob: 32f059de0ab7c0022d9035e1ff492352777f9897 [file] [log] [blame]
Jon Smirlc9969942009-06-14 18:21:28 -04001/*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2006
6 * Eric Schumann, Phytec Messatechnik GmbH
7 *
8 * (C) Copyright 2009
9 * Jon Smirl <jonsmirl@gmail.com>
10 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020011 * SPDX-License-Identifier: GPL-2.0+
Jon Smirlc9969942009-06-14 18:21:28 -040012 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
17#define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny"
18
19/*-----------------------------------------------------------------------------
20High Level Configuration Options
21(easy to change)
22-----------------------------------------------------------------------------*/
Masahiro Yamadab2a6dfe2014-01-16 11:03:07 +090023#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
Jon Smirlc9969942009-06-14 18:21:28 -040024#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */
25#define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */
26 /* FEC configuration and IDE */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020027
28/*
29 * Valid values for CONFIG_SYS_TEXT_BASE are:
30 * 0xFFF00000 boot high (standard configuration)
31 * 0xFF000000 boot low
32 * 0x00100000 boot from RAM (for testing only)
33 */
34#ifndef CONFIG_SYS_TEXT_BASE
35#define CONFIG_SYS_TEXT_BASE 0xFFF00000
36#endif
37
Jon Smirlc9969942009-06-14 18:21:28 -040038#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
Jon Smirlc9969942009-06-14 18:21:28 -040039
40/*-----------------------------------------------------------------------------
41Serial console configuration
42-----------------------------------------------------------------------------*/
43#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 -> */
44 /*define gps port conf. */
45 /* register later on to */
46 /*enable UART function! */
47#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
48#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
49
50/*
51 * Command line configuration.
52 */
Jon Smirlc9969942009-06-14 18:21:28 -040053#define CONFIG_CMD_DATE
Jon Smirlc9969942009-06-14 18:21:28 -040054#define CONFIG_CMD_EEPROM
Jon Smirlc9969942009-06-14 18:21:28 -040055#define CONFIG_CMD_JFFS2
Jon Smirlc9969942009-06-14 18:21:28 -040056#define CONFIG_CMD_PCI
57
58#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
59
Wolfgang Denk14d0a022010-10-07 21:51:12 +020060#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low */
Jon Smirlc9969942009-06-14 18:21:28 -040061#define CONFIG_SYS_LOWBOOT 1
62#endif
63/* RAMBOOT will be defined automatically in memory section */
64
65#define CONFIG_JFFS2_CMDLINE
66#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
67#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
68 "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
69
Jon Smirlc9969942009-06-14 18:21:28 -040070#undef CONFIG_BOOTARGS
71
Jon Smirlc9969942009-06-14 18:21:28 -040072#define CONFIG_PREBOOT "echo;" \
73 "echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\
74 "mount root filesystem over NFS;" \
75 "echo"
76
77#define CONFIG_EXTRA_ENV_SETTINGS \
78 "netdev=eth0\0" \
79 "uimage=uImage-pcm030\0" \
80 "oftree=oftree-pcm030.dtb\0" \
81 "jffs2=root-pcm030.jffs2\0" \
82 "uboot=u-boot-pcm030.bin\0" \
83 "bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)" \
84 " $(mtdparts) rw\0" \
85 "bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2" \
86 " rootfstype=jffs2\0" \
87 "bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs" \
88 " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::" \
89 "$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
90 "bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \
91 " tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \
92 "bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - " \
93 "0xfff40000\0" \
94 " cp.b 0x400000 0xff040000 $(filesize)\0" \
95 "prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \
96 "cp.b 0x400000 0xff200000 $(filesize)\0" \
97 "prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \
98 " cp.b 0x400000 0xfff40000 $(filesize)\0" \
99 "update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \
100 " cp.b 0x400000 0xFFF00000 $(filesize)\0" \
101 "unlock=yes\0" \
102 ""
103
104#define CONFIG_BOOTCOMMAND "run bcmd_flash"
105
106/*--------------------------------------------------------------------------
107IPB Bus clocking configuration.
108 ---------------------------------------------------------------------------*/
109#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
110
111/*-------------------------------------------------------------------------
112 * PCI Mapping:
113 * 0x40000000 - 0x4fffffff - PCI Memory
114 * 0x50000000 - 0x50ffffff - PCI IO Space
115 * -----------------------------------------------------------------------*/
116#define CONFIG_PCI 1
117#define CONFIG_PCI_PNP 1
118#define CONFIG_PCI_SCAN_SHOW 1
119#define CONFIG_PCI_MEM_BUS 0x40000000
120#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
121#define CONFIG_PCI_MEM_SIZE 0x10000000
122#define CONFIG_PCI_IO_BUS 0x50000000
123#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
124#define CONFIG_PCI_IO_SIZE 0x01000000
125#define CONFIG_SYS_XLB_PIPELINING 1
126
127/*---------------------------------------------------------------------------
128 I2C configuration
129---------------------------------------------------------------------------*/
130#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
131#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
132#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
133#define CONFIG_SYS_I2C_SLAVE 0x7F
134
135/*---------------------------------------------------------------------------
136 EEPROM CAT24WC32 configuration
137---------------------------------------------------------------------------*/
138#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */
139#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */
140#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
141#define CONFIG_SYS_EEPROM_SIZE 2048
142#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
143#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
144
145/*---------------------------------------------------------------------------
146RTC configuration
147---------------------------------------------------------------------------*/
148#define RTC
149#define CONFIG_RTC_PCF8563 1
150#define CONFIG_SYS_I2C_RTC_ADDR 0x51
151
152/*---------------------------------------------------------------------------
153 Flash configuration
154---------------------------------------------------------------------------*/
155
156#define CONFIG_SYS_FLASH_BASE 0xff000000
157#define CONFIG_SYS_FLASH_SIZE 0x01000000
158#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
159
160#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
161#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
162#define CONFIG_SYS_FLASH_EMPTY_INFO
163#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */
164#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
165 /* (= chip selects) */
166#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
167
168/*
169 * Use also hardware protection. This seems required, as the BDI uses
170 * hardware protection. Without this, U-Boot can't work with this sectors,
171 * as its protection is software only by default
172 */
173#define CONFIG_SYS_FLASH_PROTECTION 1
174
175/*---------------------------------------------------------------------------
176 Environment settings
177---------------------------------------------------------------------------*/
178
179/* pcm030 ships with environment is EEPROM by default */
180#define CONFIG_ENV_IS_IN_EEPROM 1
181#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
182 /*beginning of the EEPROM */
183#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE
184
185#define CONFIG_ENV_OVERWRITE 1
186
187/*-----------------------------------------------------------------------------
188 Memory map
189-----------------------------------------------------------------------------*/
190#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
191 /* bootloader or debugger config */
192#define CONFIG_SYS_SDRAM_BASE 0x00000000
193#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
194/* Use SRAM until RAM will be available */
195#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200196#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used */
Jon Smirlc9969942009-06-14 18:21:28 -0400197 /* area in DPRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200198#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200199 GENERATED_GBL_DATA_SIZE)
Jon Smirlc9969942009-06-14 18:21:28 -0400200#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
201
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200202#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jon Smirlc9969942009-06-14 18:21:28 -0400203#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
204# define CONFIG_SYS_RAMBOOT 1
205#endif
206
207#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
208#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
209#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
210
211/*-----------------------------------------------------------------------------
212 Ethernet configuration
213-----------------------------------------------------------------------------*/
214#define CONFIG_MPC5xxx_FEC 1
215#define CONFIG_MPC5xxx_FEC_MII100
216#define CONFIG_PHY_ADDR 0x01
217
218/*---------------------------------------------------------------------------
219 GPIO configuration
220 ---------------------------------------------------------------------------*/
221
222/* GPIO port configuration
223 *
224 * Pin mapping:
225 *
226 * [29:31] = 01x
227 * PSC1_0 -> AC97 SDATA out
228 * PSC1_1 -> AC97 SDTA in
229 * PSC1_2 -> AC97 SYNC out
230 * PSC1_3 -> AC97 bitclock out
231 * PSC1_4 -> AC97 reset out
232 *
233 * [25:27] = 001
234 * PSC2_0 -> CAN 1 Tx out
235 * PSC2_1 -> CAN 1 Rx in
236 * PSC2_2 -> CAN 2 Tx out
237 * PSC2_3 -> CAN 2 Rx in
238 * PSC2_4 -> GPIO (claimed for ATA reset, active low)
239 *
240 *
241 * [20:23] = 1100
242 * PSC3_0 -> UART Tx out
243 * PSC3_1 -> UART Rx in
244 * PSC3_2 -> UART RTS (in/out FIXME)
245 * PSC3_3 -> UART CTS (in/out FIXME)
246 * PSC3_4 -> LocalPlus Bus CS6 \
247 * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5]
248 * PSC3_6 -> dedicated SPI MOSI out (master case)
249 * PSC3_7 -> dedicated SPI MISO in (master case)
250 * PSC3_8 -> dedicated SPI SS out (master case)
251 * PSC3_9 -> dedicated SPI CLK out (master case)
252 *
253 * [18:19] = 01
254 * USB_0 -> USB OE out
255 * USB_1 -> USB Tx- out
256 * USB_2 -> USB Tx+ out
257 * USB_3 -> USB RxD (in/out FIXME)
258 * USB_4 -> USB Rx+ in
259 * USB_5 -> USB Rx- in
260 * USB_6 -> USB PortPower out
261 * USB_7 -> USB speed out
262 * USB_8 -> USB suspend (in/out FIXME)
263 * USB_9 -> USB overcurrent in
264 *
265 * [17] = 0
266 * USB differential mode
267 *
268 * [16] = 0
269 * PCI enabled
270 *
271 * [12:15] = 0101
272 * ETH_0 -> ETH Txen
273 * ETH_1 -> ETH TxD0
274 * ETH_2 -> ETH TxD1
275 * ETH_3 -> ETH TxD2
276 * ETH_4 -> ETH TxD3
277 * ETH_5 -> ETH Txerr
278 * ETH_6 -> ETH MDC
279 * ETH_7 -> ETH MDIO
280 * ETH_8 -> ETH RxDv
281 * ETH_9 -> ETH RxCLK
282 * ETH_10 -> ETH Collision
283 * ETH_11 -> ETH TxD
284 * ETH_12 -> ETH RxD0
285 * ETH_13 -> ETH RxD1
286 * ETH_14 -> ETH RxD2
287 * ETH_15 -> ETH RxD3
288 * ETH_16 -> ETH Rxerr
289 * ETH_17 -> ETH CRS
290 *
291 * [9:11] = 101
292 * PSC6_0 -> UART RxD in
293 * PSC6_1 -> UART CTS (in/out FIXME)
294 * PSC6_2 -> UART TxD out
295 * PSC6_3 -> UART RTS (in/out FIXME)
296 *
297 * [2:3/6:7] = 00/11
298 * TMR_0 -> ATA_CS0 out
299 * TMR_1 -> ATA_CS1 out
300 * TMR_2 -> GPIO
301 * TMR_3 -> GPIO
302 * TMR_4 -> GPIO
303 * TMR_5 -> GPIO
304 * TMR_6 -> GPIO
305 * TMR_7 -> GPIO
306 * I2C_0 -> I2C 1 Clock out
307 * I2C_1 -> I2C 1 IO in/out
308 * I2C_2 -> I2C 2 Clock out
309 * I2C_3 -> I2C 2 IO in/out
310 *
311 * [4] = 1
312 * PSC3_5 is used as CS7
313 *
314 * [5] = 1
315 * PSC3_4 is used as CS6
316 *
317 * [1] = 0
318 * gpio_wkup_7 is GPIO
319 *
320 * [0] = 0
321 * gpio_wkup_6 is GPIO
322 *
323 */
324#define CONFIG_SYS_GPS_PORT_CONFIG 0x0f551c12
325
326/*-----------------------------------------------------------------------------
327 Miscellaneous configurable options
328-------------------------------------------------------------------------------*/
329#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Smirlc9969942009-06-14 18:21:28 -0400330
331#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
332
333#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
334#if defined(CONFIG_CMD_KGDB)
335#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
336#endif
337
338#if defined(CONFIG_CMD_KGDB)
339#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
340#else
341#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
342#endif
343#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
344 /* Print Buffer Size */
345#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
346#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
347
348#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
349#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
350
351#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
Jon Smirlc9969942009-06-14 18:21:28 -0400352
353#define CONFIG_DISPLAY_BOARDINFO 1
354
355/*-----------------------------------------------------------------------------
356 Various low-level settings
357-----------------------------------------------------------------------------*/
358#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
359#define CONFIG_SYS_HID0_FINAL HID0_ICE
360
361/* no burst access on the LPB */
362#define CONFIG_SYS_CS_BURST 0x00000000
363/* one deadcycle for the 33MHz statemachine */
364#define CONFIG_SYS_CS_DEADCYCLE 0x33333331
365/* one additional waitstate for the 33MHz statemachine */
366#define CONFIG_SYS_BOOTCS_CFG 0x0001dd00
367#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
368#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
369
370#define CONFIG_SYS_RESET_ADDRESS 0xff000000
371
372/*-----------------------------------------------------------------------
373 * USB stuff
374 *-----------------------------------------------------------------------
375 */
376#define CONFIG_USB_CLOCK 0x0001BBBB
377#define CONFIG_USB_CONFIG 0x00001000
378
379/*---------------------------------------------------------------------------
380 IDE/ATA stuff Supports IDE harddisk
381----------------------------------------------------------------------------*/
382
383#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
384#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
385#undef CONFIG_IDE_LED /* LED for ide not supported */
386#define CONFIG_SYS_ATA_CS_ON_TIMER01
387#define CONFIG_IDE_RESET 1 /* reset for ide supported */
388#define CONFIG_IDE_PREINIT
389#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
390#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
391#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
392#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
393/* Offset for data I/O */
394#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
395/* Offset for normal register accesses */
396#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
397/* Offset for alternate registers */
398#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
399/* Interval between registers */
400#define CONFIG_SYS_ATA_STRIDE 4
401#define CONFIG_ATAPI 1
402
403/* we enable IDE and FAT support, so we also need partition support */
404#define CONFIG_DOS_PARTITION 1
405
406/* USB */
407#define CONFIG_USB_OHCI
408#define CONFIG_USB_STORAGE
409
410/* pass open firmware flat tree */
Jon Smirlc9969942009-06-14 18:21:28 -0400411#define OF_CPU "PowerPC,5200@0"
412#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
413#define OF_SOC "soc5200@f0000000"
414#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2400"
415
416#endif /* __CONFIG_H */