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wdenkc6097192002-11-03 00:24:07 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenkc6097192002-11-03 00:24:07 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 *
26 * Configuration settings for the CU824 board.
27 *
28 */
29
30/* ------------------------------------------------------------------------- */
31
32/*
33 * board/config.h - configuration options, board specific
34 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*
40 * High Level Configuration Options
41 * (easy to change)
42 */
43
44#define CONFIG_MPC824X 1
45#define CONFIG_MPC8240 1
46#define CONFIG_CU824 1
47
Wolfgang Denk2ae18242010-10-06 09:05:45 +020048#define CONFIG_SYS_TEXT_BASE 0xFFF00000
wdenkc6097192002-11-03 00:24:07 +000049
50#define CONFIG_CONS_INDEX 1
51#define CONFIG_BAUDRATE 9600
wdenkc6097192002-11-03 00:24:07 +000052
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010053#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenkc6097192002-11-03 00:24:07 +000054
55#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */
56#define CONFIG_BOOTDELAY 5
57
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050058/*
59 * BOOTP options
60 */
61#define CONFIG_BOOTP_SUBNETMASK
62#define CONFIG_BOOTP_GATEWAY
63#define CONFIG_BOOTP_HOSTNAME
64#define CONFIG_BOOTP_BOOTPATH
65#define CONFIG_BOOTP_BOOTFILESIZE
66
wdenkc6097192002-11-03 00:24:07 +000067
wdenk414eec32005-04-02 22:37:54 +000068#define CONFIG_TIMESTAMP /* Print image info with timestamp */
69
wdenkc6097192002-11-03 00:24:07 +000070
Jon Loeliger49cf7e82007-07-05 19:52:35 -050071/*
72 * Command line configuration.
wdenkc6097192002-11-03 00:24:07 +000073 */
Jon Loeliger49cf7e82007-07-05 19:52:35 -050074#include <config_cmd_default.h>
75
Wolfgang Denk5728be32007-08-06 01:01:49 +020076#define CONFIG_CMD_BEDBUG
Jon Loeliger49cf7e82007-07-05 19:52:35 -050077#define CONFIG_CMD_DHCP
78#define CONFIG_CMD_PCI
79#define CONFIG_CMD_NFS
80#define CONFIG_CMD_SNTP
wdenkc6097192002-11-03 00:24:07 +000081
82
83/*
84 * Miscellaneous configurable options
85 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_LONGHELP /* undef to save memory */
87#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
88#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000089
90#if 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
wdenkc6097192002-11-03 00:24:07 +000092#endif
wdenkc6097192002-11-03 00:24:07 +000093
94/* Print Buffer Size
95 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
wdenkc6097192002-11-03 00:24:07 +000097
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
99#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
100#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
wdenkc6097192002-11-03 00:24:07 +0000101
102/*-----------------------------------------------------------------------
103 * Start addresses for the final memory configuration
104 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000106 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_SDRAM_BASE 0x00000000
108#define CONFIG_SYS_FLASH_BASE 0xFF000000
wdenkc6097192002-11-03 00:24:07 +0000109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenkc6097192002-11-03 00:24:07 +0000111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
wdenkc6097192002-11-03 00:24:07 +0000113
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200114#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
wdenkc6097192002-11-03 00:24:07 +0000115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
117#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
120#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000121
122 /* Maximum amount of RAM.
123 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
wdenkc6097192002-11-03 00:24:07 +0000125
126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
128#undef CONFIG_SYS_RAMBOOT
wdenkc6097192002-11-03 00:24:07 +0000129#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_RAMBOOT
wdenkc6097192002-11-03 00:24:07 +0000131#endif
132
133
134/*-----------------------------------------------------------------------
135 * Definitions for initial stack pointer and data area
136 */
137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200139#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200140#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
wdenkc6097192002-11-03 00:24:07 +0000141
142/*
143 * NS16550 Configuration
144 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_NS16550
146#define CONFIG_SYS_NS16550_SERIAL
wdenkc6097192002-11-03 00:24:07 +0000147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_NS16550_REG_SIZE 4
wdenkc6097192002-11-03 00:24:07 +0000149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_NS16550_CLK (14745600 / 2)
wdenkc6097192002-11-03 00:24:07 +0000151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_NS16550_COM1 0xFE800080
153#define CONFIG_SYS_NS16550_COM2 0xFE8000C0
wdenkc6097192002-11-03 00:24:07 +0000154
155/*
156 * Low Level Configuration Settings
157 * (address mappings, register initial values, etc.)
158 * You should know what you are doing if you make changes here.
159 * For the detail description refer to the MPC8240 user's manual.
160 */
161
162#define CONFIG_SYS_CLK_FREQ 33000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_HZ 1000
wdenkc6097192002-11-03 00:24:07 +0000164
165 /* Bit-field values for MCCR1.
166 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_ROMNAL 0
168#define CONFIG_SYS_ROMFAL 7
wdenkc6097192002-11-03 00:24:07 +0000169
170 /* Bit-field values for MCCR2.
171 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_REFINT 430 /* Refresh interval */
wdenkc6097192002-11-03 00:24:07 +0000173
174 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_BSTOPRE 192
wdenkc6097192002-11-03 00:24:07 +0000177
178 /* Bit-field values for MCCR3.
179 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
181#define CONFIG_SYS_RDLAT 3 /* Data latancy from read command */
wdenkc6097192002-11-03 00:24:07 +0000182
183 /* Bit-field values for MCCR4.
184 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
186#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
187#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
188#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
189#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
190#define CONFIG_SYS_ACTORW 2
191#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
wdenkc6097192002-11-03 00:24:07 +0000192
193/* Memory bank settings.
194 * Only bits 20-29 are actually used from these vales to set the
195 * start/end addresses. The upper two bits will always be 0, and the lower
196 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
197 * address. Refer to the MPC8240 book.
198 */
199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_BANK0_START 0x00000000
201#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
202#define CONFIG_SYS_BANK0_ENABLE 1
203#define CONFIG_SYS_BANK1_START 0x3ff00000
204#define CONFIG_SYS_BANK1_END 0x3fffffff
205#define CONFIG_SYS_BANK1_ENABLE 0
206#define CONFIG_SYS_BANK2_START 0x3ff00000
207#define CONFIG_SYS_BANK2_END 0x3fffffff
208#define CONFIG_SYS_BANK2_ENABLE 0
209#define CONFIG_SYS_BANK3_START 0x3ff00000
210#define CONFIG_SYS_BANK3_END 0x3fffffff
211#define CONFIG_SYS_BANK3_ENABLE 0
212#define CONFIG_SYS_BANK4_START 0x3ff00000
213#define CONFIG_SYS_BANK4_END 0x3fffffff
214#define CONFIG_SYS_BANK4_ENABLE 0
215#define CONFIG_SYS_BANK5_START 0x3ff00000
216#define CONFIG_SYS_BANK5_END 0x3fffffff
217#define CONFIG_SYS_BANK5_ENABLE 0
218#define CONFIG_SYS_BANK6_START 0x3ff00000
219#define CONFIG_SYS_BANK6_END 0x3fffffff
220#define CONFIG_SYS_BANK6_ENABLE 0
221#define CONFIG_SYS_BANK7_START 0x3ff00000
222#define CONFIG_SYS_BANK7_END 0x3fffffff
223#define CONFIG_SYS_BANK7_ENABLE 0
wdenkc6097192002-11-03 00:24:07 +0000224
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_ODCR 0xff
wdenkc6097192002-11-03 00:24:07 +0000226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
228#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000229
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
231#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
234#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000235
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
237#define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000238
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
240#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
241#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
242#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
243#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
244#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
245#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
246#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenkc6097192002-11-03 00:24:07 +0000247
248/*
249 * For booting Linux, the board info and command line data
250 * have to be in the first 8 MB of memory, since this is
251 * the maximum mapped by the Linux kernel during initialization.
252 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000254
255/*-----------------------------------------------------------------------
256 * FLASH organization
257 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* Max number of flash banks */
259#define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
wdenkc6097192002-11-03 00:24:07 +0000260
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
262#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000263
264 /* Warining: environment is not EMBEDDED in the U-Boot code.
265 * It's stored in flash separately.
266 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200267#define CONFIG_ENV_IS_IN_FLASH 1
wdenkc6097192002-11-03 00:24:07 +0000268#if 0
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200269#define CONFIG_ENV_ADDR 0xFF008000
270#define CONFIG_ENV_SIZE 0x8000 /* Size of the Environment Sector */
wdenkc6097192002-11-03 00:24:07 +0000271#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200272#define CONFIG_ENV_ADDR 0xFFFC0000
273#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */
274#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
275#define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
wdenkc6097192002-11-03 00:24:07 +0000276#endif
277
278/*-----------------------------------------------------------------------
279 * Cache Configuration
280 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_CACHELINE_SIZE 32
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500282#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkc6097192002-11-03 00:24:07 +0000284#endif
285
wdenkc6097192002-11-03 00:24:07 +0000286/*-----------------------------------------------------------------------
287 * PCI stuff
288 *-----------------------------------------------------------------------
289 */
290#define CONFIG_PCI /* include pci support */
291#undef CONFIG_PCI_PNP
292
wdenkc6097192002-11-03 00:24:07 +0000293
294#define CONFIG_TULIP
295#define CONFIG_TULIP_USE_IO
296
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_ETH_DEV_FN 0x7800
298#define CONFIG_SYS_ETH_IOBASE 0x00104000
wdenkc6097192002-11-03 00:24:07 +0000299
wdenk3bac3512003-03-12 10:41:04 +0000300#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenk3bac3512003-03-12 10:41:04 +0000302#define PCI_ENET0_IOADDR 0x00104000
303#define PCI_ENET0_MEMADDR 0x80000000
wdenkc6097192002-11-03 00:24:07 +0000304#endif /* __CONFIG_H */