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Dirk Eibach89b86192008-12-09 13:12:40 +01001/*
2 * (C) Copyright 2008
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
5 * Based on include/configs/yosemite.h
6 * (C) Copyright 2005-2007
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28/*
29 * gdppc440etx.h - configuration for G&D 440EP/GR ETX-Module
30 */
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34/*
35 * High Level Configuration Options
36 */
37#define CONFIG_440GR 1 /* Specific PPC440GR support */
38#define CONFIG_HOSTNAME gdppc440etx
39#define CONFIG_440 1 /* ... PPC440 family */
40#define CONFIG_4xx 1 /* ... PPC4xx family */
41#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
42
43/*
44 * Include common defines/options for all AMCC eval boards
45 */
46#include "amcc-common.h"
47
48#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/
49#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
50
51/*
52 * Base addresses -- Note these are effective addresses where the
53 * actual resources get mapped (not physical addresses)
54 */
55#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
56#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory */
57#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
58#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
59#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
60
61/*Don't change either of these*/
Dirk Eibach89b86192008-12-09 13:12:40 +010062#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs */
63/*Don't change either of these*/
64
65#define CONFIG_SYS_USB_DEVICE 0x50000000
66#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
67
68/*
69 * Initial RAM & stack pointer (placed in SDRAM)
70 */
71#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram*/
72#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
73#define CONFIG_SYS_INIT_RAM_END (4 << 10)
74#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes init data*/
75#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
76 - CONFIG_SYS_GBL_DATA_SIZE)
77#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
78
79/*
80 * Serial Port
81 */
Stefan Roese550650d2010-09-20 16:05:31 +020082#define CONFIG_CONS_INDEX 2 /* Use UART1 */
83#define CONFIG_SYS_NS16550
84#define CONFIG_SYS_NS16550_SERIAL
85#define CONFIG_SYS_NS16550_REG_SIZE 1
86#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Dirk Eibach89b86192008-12-09 13:12:40 +010087#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
Dirk Eibach89b86192008-12-09 13:12:40 +010088
89/*
90 * Environment
91 * Define here the location of the environment variables (FLASH or EEPROM).
92 * Note: DENX encourages to use redundant environment in FLASH.
93 */
94#define CONFIG_ENV_IS_IN_FLASH 1 /* FLASH for env. vars*/
95
96/*
97 * FLASH related
98 */
99#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible*/
100#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
101#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB!*/
102
103#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
104#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors/chip */
105
106#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout/Flash Erase (in ms)*/
107#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout/Flash Write (in ms)*/
108
109#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x faster)*/
110
111#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
112
113#ifdef CONFIG_ENV_IS_IN_FLASH
114#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/
115#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
116#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Env. Sector */
117
118/* Address and size of Redundant Environment Sector */
119#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
120#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
121#endif /* CONFIG_ENV_IS_IN_FLASH */
122
123/*
124 * DDR SDRAM
125 */
126#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup*/
127#define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */
128#define CONFIG_SYS_SDRAM_BANKS (2)
129
130#define CONFIG_SDRAM_BANK0
131#define CONFIG_SDRAM_BANK1
132
133#define CONFIG_SYS_SDRAM0_TR0 0x410a4012
134#define CONFIG_SYS_SDRAM0_WDDCTR 0x40000000
135#define CONFIG_SYS_SDRAM0_RTR 0x04080000
136#define CONFIG_SYS_SDRAM0_CFG0 0x80000000
137
138#undef CONFIG_SDRAM_ECC
139
140/*
141 * I2C
142 */
143#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed+slave address*/
144
145/*
146 * Default environment variables
147 */
148#define CONFIG_EXTRA_ENV_SETTINGS \
149 CONFIG_AMCC_DEF_ENV \
150 CONFIG_AMCC_DEF_ENV_POWERPC \
151 CONFIG_AMCC_DEF_ENV_NOR_UPD \
152 "kernel_addr=fc000000\0" \
153 "ramdisk_addr=fc180000\0" \
154 ""
155
156#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
157#define CONFIG_PHY_ADDR 1
158#define CONFIG_PHY1_ADDR 3
159
160#ifdef DEBUG
161#define CONFIG_PANIC_HANG
162#endif
163
164/*
165 * Commands additional to the ones defined in amcc-common.h
166 */
167#define CONFIG_CMD_PCI
168#undef CONFIG_CMD_EEPROM
169
170/*
171 * PCI stuff
172 */
173
174/* General PCI */
175#define CONFIG_PCI /* include pci support */
176#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
177#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup*/
178#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to \
179 CONFIG_SYS_PCI_MEMBASE*/
180
181/* Board-specific PCI */
182#define CONFIG_SYS_PCI_TARGET_INIT
183#define CONFIG_SYS_PCI_MASTER_INIT
184
185#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
186#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* tbd */
187
188/*
189 * External Bus Controller (EBC) Setup
190 */
191#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
192
193/* Memory Bank 0 (NOR-FLASH) initialization */
194#define CONFIG_SYS_EBC_PB0AP 0x03017200
195#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000)
196
197#endif /* __CONFIG_H */