Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2018 Exceet Electronics GmbH |
| 4 | * Copyright (C) 2018 Bootlin |
| 5 | * |
| 6 | * Author: Boris Brezillon <boris.brezillon@bootlin.com> |
| 7 | */ |
| 8 | |
| 9 | #ifndef __UBOOT__ |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 10 | #include <log.h> |
Simon Glass | 61b29b8 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 11 | #include <dm/devres.h> |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 12 | #include <linux/dmaengine.h> |
| 13 | #include <linux/pm_runtime.h> |
| 14 | #include "internals.h" |
| 15 | #else |
Simon Glass | 336d461 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 16 | #include <dm/device_compat.h> |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 17 | #include <spi.h> |
| 18 | #include <spi-mem.h> |
| 19 | #endif |
| 20 | |
| 21 | #ifndef __UBOOT__ |
| 22 | /** |
| 23 | * spi_controller_dma_map_mem_op_data() - DMA-map the buffer attached to a |
| 24 | * memory operation |
| 25 | * @ctlr: the SPI controller requesting this dma_map() |
| 26 | * @op: the memory operation containing the buffer to map |
| 27 | * @sgt: a pointer to a non-initialized sg_table that will be filled by this |
| 28 | * function |
| 29 | * |
| 30 | * Some controllers might want to do DMA on the data buffer embedded in @op. |
| 31 | * This helper prepares everything for you and provides a ready-to-use |
| 32 | * sg_table. This function is not intended to be called from spi drivers. |
| 33 | * Only SPI controller drivers should use it. |
| 34 | * Note that the caller must ensure the memory region pointed by |
| 35 | * op->data.buf.{in,out} is DMA-able before calling this function. |
| 36 | * |
| 37 | * Return: 0 in case of success, a negative error code otherwise. |
| 38 | */ |
| 39 | int spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr, |
| 40 | const struct spi_mem_op *op, |
| 41 | struct sg_table *sgt) |
| 42 | { |
| 43 | struct device *dmadev; |
| 44 | |
| 45 | if (!op->data.nbytes) |
| 46 | return -EINVAL; |
| 47 | |
| 48 | if (op->data.dir == SPI_MEM_DATA_OUT && ctlr->dma_tx) |
| 49 | dmadev = ctlr->dma_tx->device->dev; |
| 50 | else if (op->data.dir == SPI_MEM_DATA_IN && ctlr->dma_rx) |
| 51 | dmadev = ctlr->dma_rx->device->dev; |
| 52 | else |
| 53 | dmadev = ctlr->dev.parent; |
| 54 | |
| 55 | if (!dmadev) |
| 56 | return -EINVAL; |
| 57 | |
| 58 | return spi_map_buf(ctlr, dmadev, sgt, op->data.buf.in, op->data.nbytes, |
| 59 | op->data.dir == SPI_MEM_DATA_IN ? |
| 60 | DMA_FROM_DEVICE : DMA_TO_DEVICE); |
| 61 | } |
| 62 | EXPORT_SYMBOL_GPL(spi_controller_dma_map_mem_op_data); |
| 63 | |
| 64 | /** |
| 65 | * spi_controller_dma_unmap_mem_op_data() - DMA-unmap the buffer attached to a |
| 66 | * memory operation |
| 67 | * @ctlr: the SPI controller requesting this dma_unmap() |
| 68 | * @op: the memory operation containing the buffer to unmap |
| 69 | * @sgt: a pointer to an sg_table previously initialized by |
| 70 | * spi_controller_dma_map_mem_op_data() |
| 71 | * |
| 72 | * Some controllers might want to do DMA on the data buffer embedded in @op. |
| 73 | * This helper prepares things so that the CPU can access the |
| 74 | * op->data.buf.{in,out} buffer again. |
| 75 | * |
| 76 | * This function is not intended to be called from SPI drivers. Only SPI |
| 77 | * controller drivers should use it. |
| 78 | * |
| 79 | * This function should be called after the DMA operation has finished and is |
| 80 | * only valid if the previous spi_controller_dma_map_mem_op_data() call |
| 81 | * returned 0. |
| 82 | * |
| 83 | * Return: 0 in case of success, a negative error code otherwise. |
| 84 | */ |
| 85 | void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr, |
| 86 | const struct spi_mem_op *op, |
| 87 | struct sg_table *sgt) |
| 88 | { |
| 89 | struct device *dmadev; |
| 90 | |
| 91 | if (!op->data.nbytes) |
| 92 | return; |
| 93 | |
| 94 | if (op->data.dir == SPI_MEM_DATA_OUT && ctlr->dma_tx) |
| 95 | dmadev = ctlr->dma_tx->device->dev; |
| 96 | else if (op->data.dir == SPI_MEM_DATA_IN && ctlr->dma_rx) |
| 97 | dmadev = ctlr->dma_rx->device->dev; |
| 98 | else |
| 99 | dmadev = ctlr->dev.parent; |
| 100 | |
| 101 | spi_unmap_buf(ctlr, dmadev, sgt, |
| 102 | op->data.dir == SPI_MEM_DATA_IN ? |
| 103 | DMA_FROM_DEVICE : DMA_TO_DEVICE); |
| 104 | } |
| 105 | EXPORT_SYMBOL_GPL(spi_controller_dma_unmap_mem_op_data); |
| 106 | #endif /* __UBOOT__ */ |
| 107 | |
| 108 | static int spi_check_buswidth_req(struct spi_slave *slave, u8 buswidth, bool tx) |
| 109 | { |
| 110 | u32 mode = slave->mode; |
| 111 | |
| 112 | switch (buswidth) { |
| 113 | case 1: |
| 114 | return 0; |
| 115 | |
| 116 | case 2: |
| 117 | if ((tx && (mode & (SPI_TX_DUAL | SPI_TX_QUAD))) || |
| 118 | (!tx && (mode & (SPI_RX_DUAL | SPI_RX_QUAD)))) |
| 119 | return 0; |
| 120 | |
| 121 | break; |
| 122 | |
| 123 | case 4: |
| 124 | if ((tx && (mode & SPI_TX_QUAD)) || |
| 125 | (!tx && (mode & SPI_RX_QUAD))) |
| 126 | return 0; |
| 127 | |
| 128 | break; |
Vignesh Raghavendra | 658df8b | 2019-12-05 15:46:05 +0530 | [diff] [blame] | 129 | case 8: |
| 130 | if ((tx && (mode & SPI_TX_OCTAL)) || |
| 131 | (!tx && (mode & SPI_RX_OCTAL))) |
| 132 | return 0; |
| 133 | |
| 134 | break; |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 135 | |
| 136 | default: |
| 137 | break; |
| 138 | } |
| 139 | |
| 140 | return -ENOTSUPP; |
| 141 | } |
| 142 | |
| 143 | bool spi_mem_default_supports_op(struct spi_slave *slave, |
| 144 | const struct spi_mem_op *op) |
| 145 | { |
| 146 | if (spi_check_buswidth_req(slave, op->cmd.buswidth, true)) |
| 147 | return false; |
| 148 | |
| 149 | if (op->addr.nbytes && |
| 150 | spi_check_buswidth_req(slave, op->addr.buswidth, true)) |
| 151 | return false; |
| 152 | |
| 153 | if (op->dummy.nbytes && |
| 154 | spi_check_buswidth_req(slave, op->dummy.buswidth, true)) |
| 155 | return false; |
| 156 | |
Tudor Ambarus | 790c169 | 2020-03-20 09:35:31 +0000 | [diff] [blame] | 157 | if (op->data.dir != SPI_MEM_NO_DATA && |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 158 | spi_check_buswidth_req(slave, op->data.buswidth, |
| 159 | op->data.dir == SPI_MEM_DATA_OUT)) |
| 160 | return false; |
| 161 | |
| 162 | return true; |
| 163 | } |
| 164 | EXPORT_SYMBOL_GPL(spi_mem_default_supports_op); |
| 165 | |
| 166 | /** |
| 167 | * spi_mem_supports_op() - Check if a memory device and the controller it is |
| 168 | * connected to support a specific memory operation |
| 169 | * @slave: the SPI device |
| 170 | * @op: the memory operation to check |
| 171 | * |
| 172 | * Some controllers are only supporting Single or Dual IOs, others might only |
| 173 | * support specific opcodes, or it can even be that the controller and device |
| 174 | * both support Quad IOs but the hardware prevents you from using it because |
| 175 | * only 2 IO lines are connected. |
| 176 | * |
| 177 | * This function checks whether a specific operation is supported. |
| 178 | * |
| 179 | * Return: true if @op is supported, false otherwise. |
| 180 | */ |
| 181 | bool spi_mem_supports_op(struct spi_slave *slave, |
| 182 | const struct spi_mem_op *op) |
| 183 | { |
| 184 | struct udevice *bus = slave->dev->parent; |
| 185 | struct dm_spi_ops *ops = spi_get_ops(bus); |
| 186 | |
| 187 | if (ops->mem_ops && ops->mem_ops->supports_op) |
| 188 | return ops->mem_ops->supports_op(slave, op); |
| 189 | |
| 190 | return spi_mem_default_supports_op(slave, op); |
| 191 | } |
| 192 | EXPORT_SYMBOL_GPL(spi_mem_supports_op); |
| 193 | |
| 194 | /** |
| 195 | * spi_mem_exec_op() - Execute a memory operation |
| 196 | * @slave: the SPI device |
| 197 | * @op: the memory operation to execute |
| 198 | * |
| 199 | * Executes a memory operation. |
| 200 | * |
| 201 | * This function first checks that @op is supported and then tries to execute |
| 202 | * it. |
| 203 | * |
| 204 | * Return: 0 in case of success, a negative error code otherwise. |
| 205 | */ |
| 206 | int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) |
| 207 | { |
| 208 | struct udevice *bus = slave->dev->parent; |
| 209 | struct dm_spi_ops *ops = spi_get_ops(bus); |
| 210 | unsigned int pos = 0; |
| 211 | const u8 *tx_buf = NULL; |
| 212 | u8 *rx_buf = NULL; |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 213 | int op_len; |
| 214 | u32 flag; |
| 215 | int ret; |
| 216 | int i; |
| 217 | |
| 218 | if (!spi_mem_supports_op(slave, op)) |
| 219 | return -ENOTSUPP; |
| 220 | |
Vignesh R | 7609448 | 2019-02-05 11:29:14 +0530 | [diff] [blame] | 221 | ret = spi_claim_bus(slave); |
| 222 | if (ret < 0) |
| 223 | return ret; |
| 224 | |
Bernhard Messerklinger | 567a3eb | 2019-03-26 10:01:24 +0100 | [diff] [blame] | 225 | if (ops->mem_ops && ops->mem_ops->exec_op) { |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 226 | #ifndef __UBOOT__ |
| 227 | /* |
| 228 | * Flush the message queue before executing our SPI memory |
| 229 | * operation to prevent preemption of regular SPI transfers. |
| 230 | */ |
| 231 | spi_flush_queue(ctlr); |
| 232 | |
| 233 | if (ctlr->auto_runtime_pm) { |
| 234 | ret = pm_runtime_get_sync(ctlr->dev.parent); |
| 235 | if (ret < 0) { |
| 236 | dev_err(&ctlr->dev, |
| 237 | "Failed to power device: %d\n", |
| 238 | ret); |
| 239 | return ret; |
| 240 | } |
| 241 | } |
| 242 | |
| 243 | mutex_lock(&ctlr->bus_lock_mutex); |
| 244 | mutex_lock(&ctlr->io_mutex); |
| 245 | #endif |
| 246 | ret = ops->mem_ops->exec_op(slave, op); |
Vignesh R | 7609448 | 2019-02-05 11:29:14 +0530 | [diff] [blame] | 247 | |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 248 | #ifndef __UBOOT__ |
| 249 | mutex_unlock(&ctlr->io_mutex); |
| 250 | mutex_unlock(&ctlr->bus_lock_mutex); |
| 251 | |
| 252 | if (ctlr->auto_runtime_pm) |
| 253 | pm_runtime_put(ctlr->dev.parent); |
| 254 | #endif |
| 255 | |
| 256 | /* |
| 257 | * Some controllers only optimize specific paths (typically the |
| 258 | * read path) and expect the core to use the regular SPI |
| 259 | * interface in other cases. |
| 260 | */ |
Vignesh R | 7609448 | 2019-02-05 11:29:14 +0530 | [diff] [blame] | 261 | if (!ret || ret != -ENOTSUPP) { |
| 262 | spi_release_bus(slave); |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 263 | return ret; |
Vignesh R | 7609448 | 2019-02-05 11:29:14 +0530 | [diff] [blame] | 264 | } |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 265 | } |
| 266 | |
| 267 | #ifndef __UBOOT__ |
| 268 | tmpbufsize = sizeof(op->cmd.opcode) + op->addr.nbytes + |
| 269 | op->dummy.nbytes; |
| 270 | |
| 271 | /* |
| 272 | * Allocate a buffer to transmit the CMD, ADDR cycles with kmalloc() so |
| 273 | * we're guaranteed that this buffer is DMA-able, as required by the |
| 274 | * SPI layer. |
| 275 | */ |
| 276 | tmpbuf = kzalloc(tmpbufsize, GFP_KERNEL | GFP_DMA); |
| 277 | if (!tmpbuf) |
| 278 | return -ENOMEM; |
| 279 | |
| 280 | spi_message_init(&msg); |
| 281 | |
| 282 | tmpbuf[0] = op->cmd.opcode; |
| 283 | xfers[xferpos].tx_buf = tmpbuf; |
| 284 | xfers[xferpos].len = sizeof(op->cmd.opcode); |
| 285 | xfers[xferpos].tx_nbits = op->cmd.buswidth; |
| 286 | spi_message_add_tail(&xfers[xferpos], &msg); |
| 287 | xferpos++; |
| 288 | totalxferlen++; |
| 289 | |
| 290 | if (op->addr.nbytes) { |
| 291 | int i; |
| 292 | |
| 293 | for (i = 0; i < op->addr.nbytes; i++) |
| 294 | tmpbuf[i + 1] = op->addr.val >> |
| 295 | (8 * (op->addr.nbytes - i - 1)); |
| 296 | |
| 297 | xfers[xferpos].tx_buf = tmpbuf + 1; |
| 298 | xfers[xferpos].len = op->addr.nbytes; |
| 299 | xfers[xferpos].tx_nbits = op->addr.buswidth; |
| 300 | spi_message_add_tail(&xfers[xferpos], &msg); |
| 301 | xferpos++; |
| 302 | totalxferlen += op->addr.nbytes; |
| 303 | } |
| 304 | |
| 305 | if (op->dummy.nbytes) { |
| 306 | memset(tmpbuf + op->addr.nbytes + 1, 0xff, op->dummy.nbytes); |
| 307 | xfers[xferpos].tx_buf = tmpbuf + op->addr.nbytes + 1; |
| 308 | xfers[xferpos].len = op->dummy.nbytes; |
| 309 | xfers[xferpos].tx_nbits = op->dummy.buswidth; |
| 310 | spi_message_add_tail(&xfers[xferpos], &msg); |
| 311 | xferpos++; |
| 312 | totalxferlen += op->dummy.nbytes; |
| 313 | } |
| 314 | |
| 315 | if (op->data.nbytes) { |
| 316 | if (op->data.dir == SPI_MEM_DATA_IN) { |
| 317 | xfers[xferpos].rx_buf = op->data.buf.in; |
| 318 | xfers[xferpos].rx_nbits = op->data.buswidth; |
| 319 | } else { |
| 320 | xfers[xferpos].tx_buf = op->data.buf.out; |
| 321 | xfers[xferpos].tx_nbits = op->data.buswidth; |
| 322 | } |
| 323 | |
| 324 | xfers[xferpos].len = op->data.nbytes; |
| 325 | spi_message_add_tail(&xfers[xferpos], &msg); |
| 326 | xferpos++; |
| 327 | totalxferlen += op->data.nbytes; |
| 328 | } |
| 329 | |
| 330 | ret = spi_sync(slave, &msg); |
| 331 | |
| 332 | kfree(tmpbuf); |
| 333 | |
| 334 | if (ret) |
| 335 | return ret; |
| 336 | |
| 337 | if (msg.actual_length != totalxferlen) |
| 338 | return -EIO; |
| 339 | #else |
| 340 | |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 341 | if (op->data.nbytes) { |
| 342 | if (op->data.dir == SPI_MEM_DATA_IN) |
| 343 | rx_buf = op->data.buf.in; |
| 344 | else |
| 345 | tx_buf = op->data.buf.out; |
| 346 | } |
| 347 | |
| 348 | op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes; |
Simon Glass | ca2abb7 | 2019-05-18 11:59:54 -0600 | [diff] [blame] | 349 | |
| 350 | /* |
| 351 | * Avoid using malloc() here so that we can use this code in SPL where |
| 352 | * simple malloc may be used. That implementation does not allow free() |
| 353 | * so repeated calls to this code can exhaust the space. |
| 354 | * |
| 355 | * The value of op_len is small, since it does not include the actual |
| 356 | * data being sent, only the op-code and address. In fact, it should be |
| 357 | * possible to just use a small fixed value here instead of op_len. |
| 358 | */ |
| 359 | u8 op_buf[op_len]; |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 360 | |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 361 | op_buf[pos++] = op->cmd.opcode; |
| 362 | |
| 363 | if (op->addr.nbytes) { |
| 364 | for (i = 0; i < op->addr.nbytes; i++) |
| 365 | op_buf[pos + i] = op->addr.val >> |
| 366 | (8 * (op->addr.nbytes - i - 1)); |
| 367 | |
| 368 | pos += op->addr.nbytes; |
| 369 | } |
| 370 | |
| 371 | if (op->dummy.nbytes) |
| 372 | memset(op_buf + pos, 0xff, op->dummy.nbytes); |
| 373 | |
| 374 | /* 1st transfer: opcode + address + dummy cycles */ |
| 375 | flag = SPI_XFER_BEGIN; |
| 376 | /* Make sure to set END bit if no tx or rx data messages follow */ |
| 377 | if (!tx_buf && !rx_buf) |
| 378 | flag |= SPI_XFER_END; |
| 379 | |
| 380 | ret = spi_xfer(slave, op_len * 8, op_buf, NULL, flag); |
| 381 | if (ret) |
| 382 | return ret; |
| 383 | |
| 384 | /* 2nd transfer: rx or tx data path */ |
| 385 | if (tx_buf || rx_buf) { |
| 386 | ret = spi_xfer(slave, op->data.nbytes * 8, tx_buf, |
| 387 | rx_buf, SPI_XFER_END); |
| 388 | if (ret) |
| 389 | return ret; |
| 390 | } |
| 391 | |
| 392 | spi_release_bus(slave); |
| 393 | |
| 394 | for (i = 0; i < pos; i++) |
| 395 | debug("%02x ", op_buf[i]); |
| 396 | debug("| [%dB %s] ", |
| 397 | tx_buf || rx_buf ? op->data.nbytes : 0, |
| 398 | tx_buf || rx_buf ? (tx_buf ? "out" : "in") : "-"); |
| 399 | for (i = 0; i < op->data.nbytes; i++) |
| 400 | debug("%02x ", tx_buf ? tx_buf[i] : rx_buf[i]); |
| 401 | debug("[ret %d]\n", ret); |
| 402 | |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 403 | if (ret < 0) |
| 404 | return ret; |
| 405 | #endif /* __UBOOT__ */ |
| 406 | |
| 407 | return 0; |
| 408 | } |
| 409 | EXPORT_SYMBOL_GPL(spi_mem_exec_op); |
| 410 | |
| 411 | /** |
| 412 | * spi_mem_adjust_op_size() - Adjust the data size of a SPI mem operation to |
| 413 | * match controller limitations |
| 414 | * @slave: the SPI device |
| 415 | * @op: the operation to adjust |
| 416 | * |
| 417 | * Some controllers have FIFO limitations and must split a data transfer |
| 418 | * operation into multiple ones, others require a specific alignment for |
| 419 | * optimized accesses. This function allows SPI mem drivers to split a single |
| 420 | * operation into multiple sub-operations when required. |
| 421 | * |
| 422 | * Return: a negative error code if the controller can't properly adjust @op, |
| 423 | * 0 otherwise. Note that @op->data.nbytes will be updated if @op |
| 424 | * can't be handled in a single step. |
| 425 | */ |
| 426 | int spi_mem_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op) |
| 427 | { |
| 428 | struct udevice *bus = slave->dev->parent; |
| 429 | struct dm_spi_ops *ops = spi_get_ops(bus); |
| 430 | |
| 431 | if (ops->mem_ops && ops->mem_ops->adjust_op_size) |
| 432 | return ops->mem_ops->adjust_op_size(slave, op); |
| 433 | |
Vignesh R | 12563f7 | 2019-02-05 11:29:13 +0530 | [diff] [blame] | 434 | if (!ops->mem_ops || !ops->mem_ops->exec_op) { |
| 435 | unsigned int len; |
| 436 | |
| 437 | len = sizeof(op->cmd.opcode) + op->addr.nbytes + |
| 438 | op->dummy.nbytes; |
| 439 | if (slave->max_write_size && len > slave->max_write_size) |
| 440 | return -EINVAL; |
| 441 | |
Ye Li | 535b1fd | 2019-07-10 09:23:51 +0000 | [diff] [blame] | 442 | if (op->data.dir == SPI_MEM_DATA_IN) { |
| 443 | if (slave->max_read_size) |
| 444 | op->data.nbytes = min(op->data.nbytes, |
Vignesh R | 12563f7 | 2019-02-05 11:29:13 +0530 | [diff] [blame] | 445 | slave->max_read_size); |
Ye Li | 535b1fd | 2019-07-10 09:23:51 +0000 | [diff] [blame] | 446 | } else if (slave->max_write_size) { |
Vignesh R | 12563f7 | 2019-02-05 11:29:13 +0530 | [diff] [blame] | 447 | op->data.nbytes = min(op->data.nbytes, |
| 448 | slave->max_write_size - len); |
Ye Li | 535b1fd | 2019-07-10 09:23:51 +0000 | [diff] [blame] | 449 | } |
Vignesh R | 12563f7 | 2019-02-05 11:29:13 +0530 | [diff] [blame] | 450 | |
| 451 | if (!op->data.nbytes) |
| 452 | return -EINVAL; |
| 453 | } |
| 454 | |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 455 | return 0; |
| 456 | } |
| 457 | EXPORT_SYMBOL_GPL(spi_mem_adjust_op_size); |
| 458 | |
| 459 | #ifndef __UBOOT__ |
| 460 | static inline struct spi_mem_driver *to_spi_mem_drv(struct device_driver *drv) |
| 461 | { |
| 462 | return container_of(drv, struct spi_mem_driver, spidrv.driver); |
| 463 | } |
| 464 | |
| 465 | static int spi_mem_probe(struct spi_device *spi) |
| 466 | { |
| 467 | struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver); |
| 468 | struct spi_mem *mem; |
| 469 | |
| 470 | mem = devm_kzalloc(&spi->dev, sizeof(*mem), GFP_KERNEL); |
| 471 | if (!mem) |
| 472 | return -ENOMEM; |
| 473 | |
| 474 | mem->spi = spi; |
| 475 | spi_set_drvdata(spi, mem); |
| 476 | |
| 477 | return memdrv->probe(mem); |
| 478 | } |
| 479 | |
| 480 | static int spi_mem_remove(struct spi_device *spi) |
| 481 | { |
| 482 | struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver); |
| 483 | struct spi_mem *mem = spi_get_drvdata(spi); |
| 484 | |
| 485 | if (memdrv->remove) |
| 486 | return memdrv->remove(mem); |
| 487 | |
| 488 | return 0; |
| 489 | } |
| 490 | |
| 491 | static void spi_mem_shutdown(struct spi_device *spi) |
| 492 | { |
| 493 | struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver); |
| 494 | struct spi_mem *mem = spi_get_drvdata(spi); |
| 495 | |
| 496 | if (memdrv->shutdown) |
| 497 | memdrv->shutdown(mem); |
| 498 | } |
| 499 | |
| 500 | /** |
| 501 | * spi_mem_driver_register_with_owner() - Register a SPI memory driver |
| 502 | * @memdrv: the SPI memory driver to register |
| 503 | * @owner: the owner of this driver |
| 504 | * |
| 505 | * Registers a SPI memory driver. |
| 506 | * |
| 507 | * Return: 0 in case of success, a negative error core otherwise. |
| 508 | */ |
| 509 | |
| 510 | int spi_mem_driver_register_with_owner(struct spi_mem_driver *memdrv, |
| 511 | struct module *owner) |
| 512 | { |
| 513 | memdrv->spidrv.probe = spi_mem_probe; |
| 514 | memdrv->spidrv.remove = spi_mem_remove; |
| 515 | memdrv->spidrv.shutdown = spi_mem_shutdown; |
| 516 | |
| 517 | return __spi_register_driver(owner, &memdrv->spidrv); |
| 518 | } |
| 519 | EXPORT_SYMBOL_GPL(spi_mem_driver_register_with_owner); |
| 520 | |
| 521 | /** |
| 522 | * spi_mem_driver_unregister_with_owner() - Unregister a SPI memory driver |
| 523 | * @memdrv: the SPI memory driver to unregister |
| 524 | * |
| 525 | * Unregisters a SPI memory driver. |
| 526 | */ |
| 527 | void spi_mem_driver_unregister(struct spi_mem_driver *memdrv) |
| 528 | { |
| 529 | spi_unregister_driver(&memdrv->spidrv); |
| 530 | } |
| 531 | EXPORT_SYMBOL_GPL(spi_mem_driver_unregister); |
| 532 | #endif /* __UBOOT__ */ |