blob: f84e356216bd9a0e941872f9739a01a7e29d9099 [file] [log] [blame]
stroese13fdf8a2003-09-12 08:55:18 +00001/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405EP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
stroesea20b27a2004-12-16 18:05:42 +000038#define CONFIG_HUB405 1 /* ...on a HUB405 board */
stroese13fdf8a2003-09-12 08:55:18 +000039
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
41#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
stroese13fdf8a2003-09-12 08:55:18 +000042
stroesea20b27a2004-12-16 18:05:42 +000043#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
stroese13fdf8a2003-09-12 08:55:18 +000044
stroese47b1e3d2005-03-01 17:26:39 +000045#define CONFIG_BOARD_TYPES 1 /* support board types */
46
stroese13fdf8a2003-09-12 08:55:18 +000047#define CONFIG_BAUDRATE 9600
48#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
49
50#undef CONFIG_BOOTARGS
stroesea20b27a2004-12-16 18:05:42 +000051#undef CONFIG_BOOTCOMMAND
stroese13fdf8a2003-09-12 08:55:18 +000052
stroesea20b27a2004-12-16 18:05:42 +000053#define CONFIG_PREBOOT /* enable preboot variable */
54
stroese13fdf8a2003-09-12 08:55:18 +000055#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
56
57#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000058#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000059#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
60
61#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
stroese13fdf8a2003-09-12 08:55:18 +000062
63#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
64 CFG_CMD_DHCP | \
65 CFG_CMD_IRQ | \
66 CFG_CMD_ELF | \
67 CFG_CMD_NAND | \
68 CFG_CMD_I2C | \
69 CFG_CMD_MII | \
70 CFG_CMD_PING | \
wdenkc837dcb2004-01-20 23:12:12 +000071 CFG_CMD_EEPROM )
stroese13fdf8a2003-09-12 08:55:18 +000072
73/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
74#include <cmd_confdefs.h>
75
wdenkc837dcb2004-01-20 23:12:12 +000076#undef CONFIG_WATCHDOG /* watchdog disabled */
stroese13fdf8a2003-09-12 08:55:18 +000077
wdenkc837dcb2004-01-20 23:12:12 +000078#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
stroese13fdf8a2003-09-12 08:55:18 +000079
80/*
81 * Miscellaneous configurable options
82 */
83#define CFG_LONGHELP /* undef to save memory */
84#define CFG_PROMPT "=> " /* Monitor Command Prompt */
85
86#undef CFG_HUSH_PARSER /* use "hush" command parser */
87#ifdef CFG_HUSH_PARSER
wdenkc837dcb2004-01-20 23:12:12 +000088#define CFG_PROMPT_HUSH_PS2 "> "
stroese13fdf8a2003-09-12 08:55:18 +000089#endif
90
91#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
wdenkc837dcb2004-01-20 23:12:12 +000092#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +000093#else
wdenkc837dcb2004-01-20 23:12:12 +000094#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +000095#endif
96#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
97#define CFG_MAXARGS 16 /* max number of command args */
98#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
99
wdenkc837dcb2004-01-20 23:12:12 +0000100#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
stroese13fdf8a2003-09-12 08:55:18 +0000101
wdenkc837dcb2004-01-20 23:12:12 +0000102#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroese13fdf8a2003-09-12 08:55:18 +0000103
104#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
105#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
106
wdenkc837dcb2004-01-20 23:12:12 +0000107#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
108#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
109#define CFG_BASE_BAUD 691200
110#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */
stroese13fdf8a2003-09-12 08:55:18 +0000111
112/* The following table includes the supported baudrates */
wdenkc837dcb2004-01-20 23:12:12 +0000113#define CFG_BAUDRATE_TABLE \
stroese13fdf8a2003-09-12 08:55:18 +0000114 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
115 57600, 115200, 230400, 460800, 921600 }
116
117#define CFG_LOAD_ADDR 0x100000 /* default load address */
118#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
119
wdenkc837dcb2004-01-20 23:12:12 +0000120#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
stroese13fdf8a2003-09-12 08:55:18 +0000121
122#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
123
wdenkc837dcb2004-01-20 23:12:12 +0000124#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroese13fdf8a2003-09-12 08:55:18 +0000125
wdenkc837dcb2004-01-20 23:12:12 +0000126#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroese13fdf8a2003-09-12 08:55:18 +0000127
stroesea20b27a2004-12-16 18:05:42 +0000128/* Ethernet stuff */
129#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
130#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE
wdenke2ffd592004-12-31 09:32:47 +0000131#define CONFIG_HAS_ETH1
stroesea20b27a2004-12-16 18:05:42 +0000132#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
133
stroese13fdf8a2003-09-12 08:55:18 +0000134/*-----------------------------------------------------------------------
135 * NAND-FLASH stuff
136 *-----------------------------------------------------------------------
137 */
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100138#define CFG_NAND_LEGACY
139
stroese13fdf8a2003-09-12 08:55:18 +0000140#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
141#define SECTORSIZE 512
142
143#define ADDR_COLUMN 1
144#define ADDR_PAGE 2
145#define ADDR_COLUMN_PAGE 3
146
wdenkc837dcb2004-01-20 23:12:12 +0000147#define NAND_ChipID_UNKNOWN 0x00
stroese13fdf8a2003-09-12 08:55:18 +0000148#define NAND_MAX_FLOORS 1
149#define NAND_MAX_CHIPS 1
150
wdenkc837dcb2004-01-20 23:12:12 +0000151#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
152#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
153#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
154#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
stroese13fdf8a2003-09-12 08:55:18 +0000155
156#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
157#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
158#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
159#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
160#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
161#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
162#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
163
164#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
165#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
166#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
167#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
168
stroesea20b27a2004-12-16 18:05:42 +0000169#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
170
stroese13fdf8a2003-09-12 08:55:18 +0000171/*-----------------------------------------------------------------------
172 * PCI stuff
173 *-----------------------------------------------------------------------
174 */
wdenkc837dcb2004-01-20 23:12:12 +0000175#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
176#define PCI_HOST_FORCE 1 /* configure as pci host */
177#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
stroese13fdf8a2003-09-12 08:55:18 +0000178
wdenkc837dcb2004-01-20 23:12:12 +0000179#undef CONFIG_PCI /* include pci support */
180#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
181#undef CONFIG_PCI_PNP /* do pci plug-and-play */
182 /* resource configuration */
stroese13fdf8a2003-09-12 08:55:18 +0000183
wdenkc837dcb2004-01-20 23:12:12 +0000184#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
stroese13fdf8a2003-09-12 08:55:18 +0000185
wdenkc837dcb2004-01-20 23:12:12 +0000186#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
187#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
188#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
189#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
190#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
191#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
192#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
193#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
194#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
stroese13fdf8a2003-09-12 08:55:18 +0000195
196/*-----------------------------------------------------------------------
197 * Start addresses for the final memory configuration
198 * (Set up by the startup code)
199 * Please note that CFG_SDRAM_BASE _must_ start at 0
200 */
201#define CFG_SDRAM_BASE 0x00000000
202#define CFG_FLASH_BASE 0xFFFC0000
203#define CFG_MONITOR_BASE CFG_FLASH_BASE
204#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
205#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
206
207/*
208 * For booting Linux, the board info and command line data
209 * have to be in the first 8 MB of memory, since this is
210 * the maximum mapped by the Linux kernel during initialization.
211 */
212#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
213/*-----------------------------------------------------------------------
214 * FLASH organization
215 */
216#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
217#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
218
219#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
220#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
221
wdenkc837dcb2004-01-20 23:12:12 +0000222#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
223#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
224#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
stroese13fdf8a2003-09-12 08:55:18 +0000225/*
226 * The following defines are added for buggy IOP480 byte interface.
227 * All other boards should use the standard values (CPCI405 etc.)
228 */
wdenkc837dcb2004-01-20 23:12:12 +0000229#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
230#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
231#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
stroese13fdf8a2003-09-12 08:55:18 +0000232
wdenkc837dcb2004-01-20 23:12:12 +0000233#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroese13fdf8a2003-09-12 08:55:18 +0000234
235#if 0 /* test-only */
wdenkc837dcb2004-01-20 23:12:12 +0000236#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
237#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
stroese13fdf8a2003-09-12 08:55:18 +0000238#endif
239
240/*-----------------------------------------------------------------------
241 * Environment Variable setup
242 */
wdenkc837dcb2004-01-20 23:12:12 +0000243#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
244#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
245#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
stroese13fdf8a2003-09-12 08:55:18 +0000246 /* total size of a CAT24WC16 is 2048 bytes */
247
248#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
wdenkc837dcb2004-01-20 23:12:12 +0000249#define CFG_NVRAM_SIZE 242 /* NVRAM size */
stroese13fdf8a2003-09-12 08:55:18 +0000250
251/*-----------------------------------------------------------------------
252 * I2C EEPROM (CAT24WC16) for environment
253 */
254#define CONFIG_HARD_I2C /* I2c with hardware support */
255#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
256#define CFG_I2C_SLAVE 0x7F
257
258#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
wdenkc837dcb2004-01-20 23:12:12 +0000259#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
260/* mask of address bits that overflow into the "EEPROM chip address" */
stroese13fdf8a2003-09-12 08:55:18 +0000261#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
262#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
263 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000264 /* last 4 bits of the address */
stroese13fdf8a2003-09-12 08:55:18 +0000265#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
266#define CFG_EEPROM_PAGE_WRITE_ENABLE
267
268/*-----------------------------------------------------------------------
269 * Cache Configuration
270 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200271#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
wdenkc837dcb2004-01-20 23:12:12 +0000272 /* have only 8kB, 16kB is save here */
stroese13fdf8a2003-09-12 08:55:18 +0000273#define CFG_CACHELINE_SIZE 32 /* ... */
274#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
275#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
276#endif
277
278/*
279 * Init Memory Controller:
280 *
281 * BR0/1 and OR0/1 (FLASH)
282 */
283
284#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
285
286/*-----------------------------------------------------------------------
287 * External Bus Controller (EBC) Setup
288 */
289
wdenkc837dcb2004-01-20 23:12:12 +0000290/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
291#define CFG_EBC_PB0AP 0x92015480
292/*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
293#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
stroese13fdf8a2003-09-12 08:55:18 +0000294
wdenkc837dcb2004-01-20 23:12:12 +0000295/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
296#define CFG_EBC_PB1AP 0x92015480
297#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
stroese13fdf8a2003-09-12 08:55:18 +0000298
wdenkc837dcb2004-01-20 23:12:12 +0000299/* Memory Bank 2 (8 Bit Peripheral: UART) initialization */
stroese13fdf8a2003-09-12 08:55:18 +0000300#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000301#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
302#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
stroese13fdf8a2003-09-12 08:55:18 +0000303#else
wdenkc837dcb2004-01-20 23:12:12 +0000304#define CFG_EBC_PB2AP 0x92015480
305#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
stroese13fdf8a2003-09-12 08:55:18 +0000306#endif
307
wdenkc837dcb2004-01-20 23:12:12 +0000308#define DUART0_BA 0xF0000000 /* DUART Base Address */
309#define DUART1_BA 0xF0000008 /* DUART Base Address */
310#define DUART2_BA 0xF0000010 /* DUART Base Address */
311#define DUART3_BA 0xF0000018 /* DUART Base Address */
312#define CFG_NAND_BASE 0xF4000000
stroese13fdf8a2003-09-12 08:55:18 +0000313
314/*-----------------------------------------------------------------------
315 * FPGA stuff
316 */
wdenkc837dcb2004-01-20 23:12:12 +0000317#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
318#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
stroese13fdf8a2003-09-12 08:55:18 +0000319
320/* FPGA program pin configuration */
wdenkc837dcb2004-01-20 23:12:12 +0000321#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
322#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
323#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
324#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
325#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
stroese13fdf8a2003-09-12 08:55:18 +0000326
327/*-----------------------------------------------------------------------
328 * Definitions for initial stack pointer and data area (in data cache)
329 */
330/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
wdenkc837dcb2004-01-20 23:12:12 +0000331#define CFG_TEMP_STACK_OCM 1
stroese13fdf8a2003-09-12 08:55:18 +0000332
333/* On Chip Memory location */
334#define CFG_OCM_DATA_ADDR 0xF8000000
335#define CFG_OCM_DATA_SIZE 0x1000
336#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
337#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
338
339#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
340#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenkc837dcb2004-01-20 23:12:12 +0000341#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
stroese13fdf8a2003-09-12 08:55:18 +0000342
343/*-----------------------------------------------------------------------
344 * Definitions for GPIO setup (PPC405EP specific)
345 *
wdenkc837dcb2004-01-20 23:12:12 +0000346 * GPIO0[0] - External Bus Controller BLAST output
347 * GPIO0[1-9] - Instruction trace outputs -> GPIO
stroese13fdf8a2003-09-12 08:55:18 +0000348 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
349 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
350 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
351 * GPIO0[24-27] - UART0 control signal inputs/outputs
352 * GPIO0[28-29] - UART1 data signal input/output
353 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
354 */
wdenkc837dcb2004-01-20 23:12:12 +0000355#define CFG_GPIO0_OSRH 0x40000550
356#define CFG_GPIO0_OSRL 0x00000110
357#define CFG_GPIO0_ISR1H 0x00000000
358#define CFG_GPIO0_ISR1L 0x15555445
359#define CFG_GPIO0_TSRH 0x00000000
360#define CFG_GPIO0_TSRL 0x00000000
361#define CFG_GPIO0_TCR 0xF7FE0014
stroese13fdf8a2003-09-12 08:55:18 +0000362
stroesea20b27a2004-12-16 18:05:42 +0000363#define CFG_DUART_RST (0x80000000 >> 14)
364#define CFG_UART2_RS232 (0x80000000 >> 5)
365#define CFG_UART3_RS232 (0x80000000 >> 6)
366#define CFG_UART4_RS232 (0x80000000 >> 7)
367#define CFG_UART5_RS232 (0x80000000 >> 8)
stroese13fdf8a2003-09-12 08:55:18 +0000368
369/*
370 * Internal Definitions
371 *
372 * Boot Flags
373 */
374#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
375#define BOOTFLAG_WARM 0x02 /* Software reboot */
376
377/*
378 * Default speed selection (cpu_plb_opb_ebc) in mhz.
379 * This value will be set if iic boot eprom is disabled.
380 */
381#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000382#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
383#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
stroese13fdf8a2003-09-12 08:55:18 +0000384#endif
385#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000386#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
387#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
stroese13fdf8a2003-09-12 08:55:18 +0000388#endif
389#if 1
wdenkc837dcb2004-01-20 23:12:12 +0000390#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
391#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
stroese13fdf8a2003-09-12 08:55:18 +0000392#endif
393
394#endif /* __CONFIG_H */