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wdenk7abf0c52004-04-18 21:45:42 +00001/*
2 * (C) Copyright 2003 Embedded Edge, LLC
3 * Dan Malek <dan@embeddededge.com>
4 * Copied from ADS85xx.
5 * Updates for Silicon Tx GP3 8560 board.
6 *
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/* mpc8560ads board configuration file */
30/* please refer to doc/README.mpc85xx for more info */
31/* make sure you change the MAC address and other network params first,
32 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
38/* High Level Configuration Options */
39#define CONFIG_BOOKE 1 /* BOOKE */
40#define CONFIG_E500 1 /* BOOKE e500 family */
41#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050042#define CONFIG_CPM2 1 /* has CPM2 */
wdenk7abf0c52004-04-18 21:45:42 +000043#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/
44
45#undef CONFIG_PCI /* pci ethernet support */
46#define CONFIG_TSEC_ENET /* tsec ethernet support*/
47#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
48#define CONFIG_ENV_OVERWRITE
49#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
50#undef CONFIG_DDR_ECC /* only for ECC DDR module */
wdenk7abf0c52004-04-18 21:45:42 +000051#define CONFIG_DDR_DLL /* possible DLL fix needed */
wdenk9aea9532004-08-01 23:02:45 +000052#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
wdenk7abf0c52004-04-18 21:45:42 +000053
wdenk9aea9532004-08-01 23:02:45 +000054
55/* sysclk for MPC85xx
wdenk7abf0c52004-04-18 21:45:42 +000056 */
wdenk7abf0c52004-04-18 21:45:42 +000057
58#define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */
59
60/* Blinkin' LEDs for Robert :-)
61*/
62#define CONFIG_SHOW_ACTIVITY 1
63
wdenk9aea9532004-08-01 23:02:45 +000064/*
65 * These can be toggled for performance analysis, otherwise use default.
66 */
wdenk7abf0c52004-04-18 21:45:42 +000067#define CONFIG_L2_CACHE /* toggle L2 cache */
wdenk9aea9532004-08-01 23:02:45 +000068#define CONFIG_BTB /* toggle branch predition */
69#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
wdenk7abf0c52004-04-18 21:45:42 +000070
wdenk9aea9532004-08-01 23:02:45 +000071#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
wdenk7abf0c52004-04-18 21:45:42 +000072
73#undef CFG_DRAM_TEST /* memory test, takes time */
74#define CFG_MEMTEST_START 0x00200000 /* memtest region */
75#define CFG_MEMTEST_END 0x00400000
76
wdenk7abf0c52004-04-18 21:45:42 +000077
78/* Localbus SDRAM is an option, not all boards have it.
wdenk9aea9532004-08-01 23:02:45 +000079 * This address, however, is used to configure a 256M local bus
80 * window that includes the Config latch below.
81 */
82#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
83#define CFG_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */
wdenk7abf0c52004-04-18 21:45:42 +000084
wdenk7abf0c52004-04-18 21:45:42 +000085#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
86#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk7abf0c52004-04-18 21:45:42 +000087
88#define CFG_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */
89#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
90#define CFG_MAX_FLASH_SECT 136 /* sectors per device */
91#undef CFG_FLASH_CHECKSUM
92#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */
93#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
94
95/* The configuration latch is Chip Select 1.
wdenk9aea9532004-08-01 23:02:45 +000096 * It's an 8-bit latch in the lower 8 bits of the word.
wdenk7abf0c52004-04-18 21:45:42 +000097 */
98#define CFG_BR1_PRELIM 0xfc001801 /* 32-bit port */
99#define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
100#define CFG_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */
101
102#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
103
104#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
105#define CFG_RAMBOOT
106#else
107#undef CFG_RAMBOOT
108#endif
109
110#ifdef CFG_RAMBOOT
111#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
112#else
113#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
114#endif
115#define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
116#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
117
118
wdenk9aea9532004-08-01 23:02:45 +0000119/*
120 * DDR Setup
121 */
wdenk7abf0c52004-04-18 21:45:42 +0000122
wdenk9aea9532004-08-01 23:02:45 +0000123/*
124 * Base addresses -- Note these are effective addresses where the
125 * actual resources get mapped (not physical addresses)
126 */
127#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
128#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
129
130#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
wdenk7abf0c52004-04-18 21:45:42 +0000131
132#undef CONFIG_CLOCKS_IN_MHZ
133
134/* local bus definitions */
135#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
136#define CFG_OR2_PRELIM 0xfc006901
137#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
138#define CFG_LBC_LBCR 0x00000000
139#define CFG_LBC_LSRT 0x20000000
140#define CFG_LBC_MRTPR 0x20000000
141#define CFG_LBC_LSDMR_1 0x2861b723
142#define CFG_LBC_LSDMR_2 0x0861b723
143#define CFG_LBC_LSDMR_3 0x0861b723
144#define CFG_LBC_LSDMR_4 0x1861b723
145#define CFG_LBC_LSDMR_5 0x4061b723
146
147#define CONFIG_L1_INIT_RAM
148#define CFG_INIT_RAM_LOCK 1
149#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
150#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
151
152#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
153#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
154#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
155
156#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
157#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
158
159/* Serial Port */
160#define CONFIG_CONS_ON_SCC /* define if console on SCC */
161#undef CONFIG_CONS_NONE /* define if console on something else */
162#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
163
164#define CONFIG_BAUDRATE 38400
165
166#define CFG_BAUDRATE_TABLE \
167 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
168
169/* Use the HUSH parser */
170#define CFG_HUSH_PARSER
171#ifdef CFG_HUSH_PARSER
172#define CFG_PROMPT_HUSH_PS2 "> "
173#endif
174
175/* I2C */
176#define CONFIG_HARD_I2C /* I2C with hardware support*/
177#undef CONFIG_SOFT_I2C /* I2C bit-banged */
178#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
179#define CFG_I2C_SLAVE 0x7F
180#if 0
181#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */
182#else
183/* I did the 'if 0' so we could keep the syntax above if ever needed. */
184#undef CFG_I2C_NOPROBES
185#endif
186
wdenk9aea9532004-08-01 23:02:45 +0000187/* RapdIO Map configuration, mapped 1:1.
188*/
189#define CFG_RIO_MEM_BASE 0xc0000000
190#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
191#define CFG_RIO_MEM_SIZE 0x200000000 /* 512 M */
192
193/* Standard 8560 PCI addressing, mapped 1:1.
194*/
195#define CFG_PCI1_MEM_BASE 0x80000000
196#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
197#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
198#define CFG_PCI1_IO_BASE 0xe2000000
199#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
200#define CFG_PCI1_IO_SIZE 0x01000000 /* 16 M */
wdenk7abf0c52004-04-18 21:45:42 +0000201
202#if defined(CONFIG_PCI) /* PCI Ethernet card */
wdenk9aea9532004-08-01 23:02:45 +0000203
wdenk7abf0c52004-04-18 21:45:42 +0000204#define CONFIG_NET_MULTI
wdenk7abf0c52004-04-18 21:45:42 +0000205#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk9aea9532004-08-01 23:02:45 +0000206
207#undef CONFIG_EEPRO100
208#undef CONFIG_TULIP
209
210#if !defined(CONFIG_PCI_PNP)
wdenk7abf0c52004-04-18 21:45:42 +0000211 #define PCI_ENET0_IOADDR 0xe0000000
212 #define PCI_ENET0_MEMADDR 0xe0000000
213 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk7abf0c52004-04-18 21:45:42 +0000214#endif
wdenk9aea9532004-08-01 23:02:45 +0000215
216#undef CONFIG_PCI_SCAN_SHOW
217#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
218
219#endif /* CONFIG_PCI */
220
221#if defined(CONFIG_TSEC_ENET)
222
223#ifndef CONFIG_NET_MULTI
wdenk7abf0c52004-04-18 21:45:42 +0000224#define CONFIG_NET_MULTI 1
wdenk9aea9532004-08-01 23:02:45 +0000225#endif
226
wdenk7abf0c52004-04-18 21:45:42 +0000227#define CONFIG_MII 1 /* MII PHY management */
wdenk9aea9532004-08-01 23:02:45 +0000228
229#define CONFIG_MPC85XX_TSEC1 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500230#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
wdenk9aea9532004-08-01 23:02:45 +0000231#define CONFIG_MPC85XX_TSEC2 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500232#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
wdenk9aea9532004-08-01 23:02:45 +0000233#undef CONFIG_MPS85XX_FEC
234
235#define TSEC1_PHY_ADDR 2
236#define TSEC2_PHY_ADDR 4
237#define TSEC1_PHYIDX 0
238#define TSEC2_PHYIDX 0
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500239#define CONFIG_ETHPRIME "TSEC0"
wdenk9aea9532004-08-01 23:02:45 +0000240
wdenk7abf0c52004-04-18 21:45:42 +0000241#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
wdenk9aea9532004-08-01 23:02:45 +0000242
wdenk7abf0c52004-04-18 21:45:42 +0000243#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
244#undef CONFIG_ETHER_NONE /* define if ether on something else */
245#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
wdenk9aea9532004-08-01 23:02:45 +0000246
247#if (CONFIG_ETHER_INDEX == 2)
wdenk7abf0c52004-04-18 21:45:42 +0000248 /*
249 * - Rx-CLK is CLK13
250 * - Tx-CLK is CLK14
251 * - Select bus for bd/buffers
252 * - Full duplex
253 */
254 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
255 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
256 #define CFG_CPMFCR_RAMTYPE 0
257#if 0
258 #define CFG_FCC_PSMR (FCC_PSMR_FDE)
259#else
260 #define CFG_FCC_PSMR 0
261#endif
262 #define FETH2_RST 0x01
wdenk9aea9532004-08-01 23:02:45 +0000263#elif (CONFIG_ETHER_INDEX == 3)
wdenk7abf0c52004-04-18 21:45:42 +0000264 /* need more definitions here for FE3 */
265 #define FETH3_RST 0x80
wdenk9aea9532004-08-01 23:02:45 +0000266#endif /* CONFIG_ETHER_INDEX */
267
268/* MDIO is done through the TSEC0 control.
269*/
wdenk7abf0c52004-04-18 21:45:42 +0000270#define CONFIG_MII /* MII PHY management */
271#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
wdenk7abf0c52004-04-18 21:45:42 +0000272
wdenk7abf0c52004-04-18 21:45:42 +0000273#endif
274
275/* Environment */
276/* We use the top boot sector flash, so we have some 16K sectors for env
wdenk7abf0c52004-04-18 21:45:42 +0000277 */
278#ifndef CFG_RAMBOOT
wdenk7abf0c52004-04-18 21:45:42 +0000279 #define CFG_ENV_IS_IN_FLASH 1
280 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x60000)
281 #define CFG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */
wdenk7abf0c52004-04-18 21:45:42 +0000282 #define CFG_ENV_SIZE 0x2000
283#else
wdenk9aea9532004-08-01 23:02:45 +0000284 #define CFG_NO_FLASH 1 /* Flash is not usable now */
285 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
286 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
287 #define CFG_ENV_SIZE 0x2000
wdenk7abf0c52004-04-18 21:45:42 +0000288#endif
289
290#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400"
wdenk9aea9532004-08-01 23:02:45 +0000291#define CONFIG_BOOTCOMMAND "bootm 0xff000000 0xff100000"
wdenk7abf0c52004-04-18 21:45:42 +0000292#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
293
294#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
295#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
296
wdenk9aea9532004-08-01 23:02:45 +0000297#if defined(CFG_RAMBOOT)
wdenk7abf0c52004-04-18 21:45:42 +0000298 #if defined(CONFIG_PCI)
299 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
300 CFG_CMD_PING | CFG_CMD_I2C) & \
301 ~(CFG_CMD_ENV | \
302 CFG_CMD_LOADS ))
303 #elif defined(CONFIG_TSEC_ENET)
304 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \
305 CFG_CMD_MII | CFG_CMD_I2C ) & \
306 ~(CFG_CMD_ENV))
307 #elif defined(CONFIG_ETHER_ON_FCC)
308 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
309 CFG_CMD_PING | CFG_CMD_I2C) & \
310 ~(CFG_CMD_ENV))
311 #endif
312#else
313 #if defined(CONFIG_PCI)
314 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
wdenk9aea9532004-08-01 23:02:45 +0000315 CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
wdenk7abf0c52004-04-18 21:45:42 +0000316 #elif defined(CONFIG_TSEC_ENET)
317 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \
wdenk9aea9532004-08-01 23:02:45 +0000318 CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C)
wdenk7abf0c52004-04-18 21:45:42 +0000319 #elif defined(CONFIG_ETHER_ON_FCC)
320 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
wdenk9aea9532004-08-01 23:02:45 +0000321 CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
wdenk7abf0c52004-04-18 21:45:42 +0000322 #endif
323#endif
324#include <cmd_confdefs.h>
325
326#undef CONFIG_WATCHDOG /* watchdog disabled */
327
328/*
329 * Miscellaneous configurable options
330 */
331#define CFG_LONGHELP /* undef to save memory */
332#define CFG_PROMPT "GPPP=> " /* Monitor Command Prompt */
333#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
334#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
335#else
336#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
337#endif
338#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
339#define CFG_MAXARGS 16 /* max number of command args */
340#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
341#define CFG_LOAD_ADDR 0x1000000 /* default load address */
342#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
343
344/*
345 * For booting Linux, the board info and command line data
346 * have to be in the first 8 MB of memory, since this is
347 * the maximum mapped by the Linux kernel during initialization.
348 */
349#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
350
351/* Cache Configuration */
352#define CFG_DCACHE_SIZE 32768
353#define CFG_CACHELINE_SIZE 32
354#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
355#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
356#endif
357
358/*
359 * Internal Definitions
360 *
361 * Boot Flags
362 */
363#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
364#define BOOTFLAG_WARM 0x02 /* Software reboot */
365
366#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
367#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
368#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
369#endif
370
371/*Note: change below for your network setting!!! */
372#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
wdenke2ffd592004-12-31 09:32:47 +0000373#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
374#define CONFIG_HAS_ETH1
wdenk9aea9532004-08-01 23:02:45 +0000375#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
wdenke2ffd592004-12-31 09:32:47 +0000376#define CONFIG_HAS_ETH2
wdenk9aea9532004-08-01 23:02:45 +0000377#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
wdenk7abf0c52004-04-18 21:45:42 +0000378#endif
379
380#define CONFIG_SERVERIP 192.168.85.1
381#define CONFIG_IPADDR 192.168.85.60
382#define CONFIG_GATEWAYIP 192.168.85.1
383#define CONFIG_NETMASK 255.255.255.0
384#define CONFIG_HOSTNAME STX_GP3
385#define CONFIG_ROOTPATH /gppproot
386#define CONFIG_BOOTFILE uImage
wdenk9aea9532004-08-01 23:02:45 +0000387#define CONFIG_LOADADDR 0x1000000
wdenk7abf0c52004-04-18 21:45:42 +0000388
389#endif /* __CONFIG_H */