| Jean-Jacques Hiblot | 1a83f99 | 2021-07-21 21:28:38 +0530 | [diff] [blame] | 1 | config PHY_J721E_WIZ |
| 2 | tristate "TI J721E WIZ (SERDES Wrapper) support" | ||||
| 3 | depends on ARCH_K3 | ||||
| 4 | help | ||||
| 5 | This option enables support for WIZ module present in TI's J721E | ||||
| 6 | SoC. WIZ is a serdes wrapper used to configure some of the input | ||||
| 7 | signals to the SERDES (Sierra/Torrent). This driver configures | ||||
| 8 | three clock selects (pll0, pll1, dig) and resets for each of the | ||||
| 9 | lanes. | ||||