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Paul Burtonbaf37f02013-11-08 11:18:50 +00001/*
2 * Copyright (C) 2013 Imagination Technologies
Paul Burtonc5bf1612017-10-30 16:58:21 -07003 * Author: Paul Burton <paul.burton@mips.com>
Paul Burtonbaf37f02013-11-08 11:18:50 +00004 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef __MSC01_H__
9#define __MSC01_H__
10
11/*
12 * Bus Interface Unit
13 */
14
15#define MSC01_BIU_IP1BAS1L_OFS 0x0208
16#define MSC01_BIU_IP1MSK1L_OFS 0x0218
17#define MSC01_BIU_IP1BAS2L_OFS 0x0248
18#define MSC01_BIU_IP1MSK2L_OFS 0x0258
19#define MSC01_BIU_IP2BAS1L_OFS 0x0288
20#define MSC01_BIU_IP2MSK1L_OFS 0x0298
21#define MSC01_BIU_IP2BAS2L_OFS 0x02c8
22#define MSC01_BIU_IP2MSK2L_OFS 0x02d8
23#define MSC01_BIU_IP3BAS1L_OFS 0x0308
24#define MSC01_BIU_IP3MSK1L_OFS 0x0318
25#define MSC01_BIU_IP3BAS2L_OFS 0x0348
26#define MSC01_BIU_IP3MSK2L_OFS 0x0358
27#define MSC01_BIU_MCBAS1L_OFS 0x0388
28#define MSC01_BIU_MCMSK1L_OFS 0x0398
29#define MSC01_BIU_MCBAS2L_OFS 0x03c8
30#define MSC01_BIU_MCMSK2L_OFS 0x03d8
31
32/*
33 * PCI Bridge
34 */
35
36#define MSC01_PCI_SC2PMBASL_OFS 0x0208
37#define MSC01_PCI_SC2PMMSKL_OFS 0x0218
38#define MSC01_PCI_SC2PMMAPL_OFS 0x0228
39#define MSC01_PCI_SC2PIOBASL_OFS 0x0248
40#define MSC01_PCI_SC2PIOMSKL_OFS 0x0258
41#define MSC01_PCI_SC2PIOMAPL_OFS 0x0268
42#define MSC01_PCI_P2SCMSKL_OFS 0x0308
43#define MSC01_PCI_P2SCMAPL_OFS 0x0318
44#define MSC01_PCI_INTSTAT_OFS 0x0608
45#define MSC01_PCI_CFGADDR_OFS 0x0610
46#define MSC01_PCI_CFGDATA_OFS 0x0618
47#define MSC01_PCI_HEAD0_OFS 0x2000
48#define MSC01_PCI_HEAD1_OFS 0x2008
49#define MSC01_PCI_HEAD2_OFS 0x2010
50#define MSC01_PCI_HEAD3_OFS 0x2018
51#define MSC01_PCI_HEAD4_OFS 0x2020
52#define MSC01_PCI_HEAD5_OFS 0x2028
53#define MSC01_PCI_HEAD6_OFS 0x2030
54#define MSC01_PCI_HEAD7_OFS 0x2038
55#define MSC01_PCI_HEAD8_OFS 0x2040
56#define MSC01_PCI_HEAD9_OFS 0x2048
57#define MSC01_PCI_HEAD10_OFS 0x2050
58#define MSC01_PCI_HEAD11_OFS 0x2058
59#define MSC01_PCI_HEAD12_OFS 0x2060
60#define MSC01_PCI_HEAD13_OFS 0x2068
61#define MSC01_PCI_HEAD14_OFS 0x2070
62#define MSC01_PCI_HEAD15_OFS 0x2078
63#define MSC01_PCI_BAR0_OFS 0x2220
64#define MSC01_PCI_CFG_OFS 0x2380
65#define MSC01_PCI_SWAP_OFS 0x2388
66
67#define MSC01_PCI_SC2PMMSKL_MSK_MSK 0xff000000
68#define MSC01_PCI_SC2PIOMSKL_MSK_MSK 0xff000000
69
70#define MSC01_PCI_INTSTAT_TA_SHF 6
71#define MSC01_PCI_INTSTAT_TA_MSK (0x1 << MSC01_PCI_INTSTAT_TA_SHF)
72#define MSC01_PCI_INTSTAT_MA_SHF 7
73#define MSC01_PCI_INTSTAT_MA_MSK (0x1 << MSC01_PCI_INTSTAT_MA_SHF)
74
75#define MSC01_PCI_CFGADDR_BNUM_SHF 16
76#define MSC01_PCI_CFGADDR_BNUM_MSK (0xff << MSC01_PCI_CFGADDR_BNUM_SHF)
77#define MSC01_PCI_CFGADDR_DNUM_SHF 11
78#define MSC01_PCI_CFGADDR_DNUM_MSK (0x1f << MSC01_PCI_CFGADDR_DNUM_SHF)
79#define MSC01_PCI_CFGADDR_FNUM_SHF 8
80#define MSC01_PCI_CFGADDR_FNUM_MSK (0x3 << MSC01_PCI_CFGADDR_FNUM_SHF)
81#define MSC01_PCI_CFGADDR_RNUM_SHF 2
82#define MSC01_PCI_CFGADDR_RNUM_MSK (0x3f << MSC01_PCI_CFGADDR_RNUM_SHF)
83
84#define MSC01_PCI_HEAD0_VENDORID_SHF 0
85#define MSC01_PCI_HEAD0_DEVICEID_SHF 16
86
87#define MSC01_PCI_HEAD2_REV_SHF 0
88#define MSC01_PCI_HEAD2_CLASS_SHF 16
89
90#define MSC01_PCI_CFG_EN_SHF 15
91#define MSC01_PCI_CFG_EN_MSK (0x1 << MSC01_PCI_CFG_EN_SHF)
92#define MSC01_PCI_CFG_G_SHF 16
93#define MSC01_PCI_CFG_G_MSK (0x1 << MSC01_PCI_CFG_G_SHF)
94#define MSC01_PCI_CFG_RA_SHF 17
95#define MSC01_PCI_CFG_RA_MSK (0x1 << MSC01_PCI_CFG_RA_SHF)
96
97#define MSC01_PCI_SWAP_BAR0_BSWAP_SHF 0
98#define MSC01_PCI_SWAP_IO_BSWAP_SHF 18
99
100/*
101 * Peripheral Bus Controller
102 */
103
104#define MSC01_PBC_CLKCFG_OFS 0x0100
105#define MSC01_PBC_CS0CFG_OFS 0x0400
106#define MSC01_PBC_CS0TIM_OFS 0x0500
107#define MSC01_PBC_CS0RW_OFS 0x0600
108
109#define MSC01_PBC_CLKCFG_SHF 0
110#define MSC01_PBC_CLKCFG_MSK (0x1f << MSC01_PBC_CLKCFG_SHF)
111
112#define MSC01_PBC_CS0CFG_WS_SHF 0
113#define MSC01_PBC_CS0CFG_WS_MSK (0x1f << MSC01_PBC_CS0CFG_WS_SHF)
114#define MSC01_PBC_CS0CFG_WSIDLE_SHF 8
115#define MSC01_PBC_CS0CFG_WSIDLE_MSK (0x1f << MSC01_PBC_CS0CFG_WSIDLE_SHF)
116#define MSC01_PBC_CS0CFG_DTYP_SHF 16
117#define MSC01_PBC_CS0CFG_DTYP_MSK (0x3 << MSC01_PBC_CS0CFG_DTYP_SHF)
118#define MSC01_PBC_CS0CFG_ADM_SHF 20
119#define MSC01_PBC_CS0CFG_ADM_MSK (0x1 << MSC01_PBC_CS0CFG_ADM_SHF)
120
121#define MSC01_PBC_CS0TIM_CAT_SHF 0
122#define MSC01_PBC_CS0TIM_CAT_MSK (0x1f << MSC01_PBC_CS0TIM_CAT_SHF)
123#define MSC01_PBC_CS0TIM_CDT_SHF 8
124#define MSC01_PBC_CS0TIM_CDT_MSK (0x1f << MSC01_PBC_CS0TIM_CDT_SHF)
125
126#define MSC01_PBC_CS0RW_WAT_SHF 0
127#define MSC01_PBC_CS0RW_WAT_MSK (0x1f << MSC01_PBC_CS0RW_WAT_SHF)
128#define MSC01_PBC_CS0RW_WDT_SHF 8
129#define MSC01_PBC_CS0RW_WDT_MSK (0x1f << MSC01_PBC_CS0RW_WDT_SHF)
130#define MSC01_PBC_CS0RW_RAT_SHF 16
131#define MSC01_PBC_CS0RW_RAT_MSK (0x1f << MSC01_PBC_CS0RW_RAT_SHF)
132#define MSC01_PBC_CS0RW_RDT_SHF 24
133#define MSC01_PBC_CS0RW_RDT_MSK (0x1f << MSC01_PBC_CS0RW_RDT_SHF)
134
135#endif /* __MSC01_H__ */