| Mike Frysinger | d4d7730 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 1 | /* DO NOT EDIT THIS FILE |
| 2 | * Automatically generated by generate-cdef-headers.xsl |
| 3 | * DO NOT EDIT THIS FILE |
| 4 | */ |
| 5 | |
| 6 | #ifndef __BFIN_CDEF_ADSP_EDN_BF52x_extended__ |
| 7 | #define __BFIN_CDEF_ADSP_EDN_BF52x_extended__ |
| 8 | |
| 9 | #define pSIC_RVECT ((uint32_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */ |
| 10 | #define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) |
| 11 | #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) |
| 12 | #define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* Interrupt Mask Register */ |
| 13 | #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) |
| 14 | #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) |
| 15 | #define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */ |
| 16 | #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) |
| 17 | #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) |
| 18 | #define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */ |
| 19 | #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) |
| 20 | #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) |
| 21 | #define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */ |
| 22 | #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) |
| 23 | #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) |
| 24 | #define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */ |
| 25 | #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) |
| 26 | #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) |
| 27 | #define pSIC_ISR0 ((uint32_t volatile *)SIC_ISR0) /* Interrupt Status Register */ |
| 28 | #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) |
| 29 | #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) |
| 30 | #define pSIC_IWR0 ((uint32_t volatile *)SIC_IWR0) /* Interrupt Wakeup Register */ |
| 31 | #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) |
| 32 | #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) |
| 33 | #define pSIC_IMASK1 ((uint32_t volatile *)SIC_IMASK1) /* Interrupt Mask register of SIC2 */ |
| 34 | #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) |
| 35 | #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) |
| 36 | #define pSIC_IAR4 ((uint32_t volatile *)SIC_IAR4) /* Interrupt Assignment register4 */ |
| 37 | #define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) |
| 38 | #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) |
| 39 | #define pSIC_IAR5 ((uint32_t volatile *)SIC_IAR5) /* Interrupt Assignment register5 */ |
| 40 | #define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) |
| 41 | #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) |
| 42 | #define pSIC_IAR6 ((uint32_t volatile *)SIC_IAR6) /* Interrupt Assignment register6 */ |
| 43 | #define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) |
| 44 | #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) |
| 45 | #define pSIC_IAR7 ((uint32_t volatile *)SIC_IAR7) /* Interrupt Assignment register7 */ |
| 46 | #define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) |
| 47 | #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) |
| 48 | #define pSIC_ISR1 ((uint32_t volatile *)SIC_ISR1) /* Interrupt Status register */ |
| 49 | #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) |
| 50 | #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) |
| 51 | #define pSIC_IWR1 ((uint32_t volatile *)SIC_IWR1) /* Interrupt Wakeup register */ |
| 52 | #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) |
| 53 | #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) |
| 54 | #define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */ |
| 55 | #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) |
| 56 | #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) |
| 57 | #define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */ |
| 58 | #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) |
| 59 | #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) |
| 60 | #define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */ |
| 61 | #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) |
| 62 | #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) |
| 63 | #define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */ |
| 64 | #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) |
| 65 | #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) |
| 66 | #define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */ |
| 67 | #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) |
| 68 | #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) |
| 69 | #define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */ |
| 70 | #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) |
| 71 | #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) |
| 72 | #define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */ |
| 73 | #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) |
| 74 | #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) |
| 75 | #define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Time Register */ |
| 76 | #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) |
| 77 | #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) |
| 78 | #define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */ |
| 79 | #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) |
| 80 | #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) |
| 81 | #define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Holding register */ |
| 82 | #define bfin_read_UART0_THR() bfin_read16(UART0_THR) |
| 83 | #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) |
| 84 | #define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer register */ |
| 85 | #define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) |
| 86 | #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) |
| 87 | #define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch (Low-Byte) */ |
| 88 | #define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) |
| 89 | #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) |
| 90 | #define pUART0_IER ((uint16_t volatile *)UART0_IER) /* Interrupt Enable Register */ |
| 91 | #define bfin_read_UART0_IER() bfin_read16(UART0_IER) |
| 92 | #define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) |
| 93 | #define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch (High-Byte) */ |
| 94 | #define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) |
| 95 | #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) |
| 96 | #define pUART0_IIR ((uint16_t volatile *)UART0_IIR) /* Interrupt Identification Register */ |
| 97 | #define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) |
| 98 | #define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) |
| 99 | #define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */ |
| 100 | #define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) |
| 101 | #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) |
| 102 | #define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */ |
| 103 | #define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) |
| 104 | #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) |
| 105 | #define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */ |
| 106 | #define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) |
| 107 | #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) |
| 108 | #define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */ |
| 109 | #define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) |
| 110 | #define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) |
| 111 | #define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* SCR Scratch Register */ |
| 112 | #define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) |
| 113 | #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) |
| 114 | #define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */ |
| 115 | #define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) |
| 116 | #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) |
| 117 | #define pSPI_CTL ((uint16_t volatile *)SPI_CTL) /* SPI Control Register */ |
| 118 | #define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) |
| 119 | #define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) |
| 120 | #define pSPI_FLG ((uint16_t volatile *)SPI_FLG) /* SPI Flag register */ |
| 121 | #define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) |
| 122 | #define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) |
| 123 | #define pSPI_STAT ((uint16_t volatile *)SPI_STAT) /* SPI Status register */ |
| 124 | #define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) |
| 125 | #define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) |
| 126 | #define pSPI_TDBR ((uint16_t volatile *)SPI_TDBR) /* SPI Transmit Data Buffer Register */ |
| 127 | #define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) |
| 128 | #define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) |
| 129 | #define pSPI_RDBR ((uint16_t volatile *)SPI_RDBR) /* SPI Receive Data Buffer Register */ |
| 130 | #define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) |
| 131 | #define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) |
| 132 | #define pSPI_BAUD ((uint16_t volatile *)SPI_BAUD) /* SPI Baud rate Register */ |
| 133 | #define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) |
| 134 | #define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) |
| 135 | #define pSPI_SHADOW ((uint16_t volatile *)SPI_SHADOW) /* SPI_RDBR Shadow Register */ |
| 136 | #define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) |
| 137 | #define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) |
| 138 | #define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */ |
| 139 | #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) |
| 140 | #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) |
| 141 | #define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */ |
| 142 | #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) |
| 143 | #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) |
| 144 | #define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */ |
| 145 | #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) |
| 146 | #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) |
| 147 | #define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */ |
| 148 | #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) |
| 149 | #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) |
| 150 | #define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */ |
| 151 | #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) |
| 152 | #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) |
| 153 | #define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */ |
| 154 | #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) |
| 155 | #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) |
| 156 | #define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */ |
| 157 | #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) |
| 158 | #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) |
| 159 | #define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */ |
| 160 | #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) |
| 161 | #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) |
| 162 | #define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */ |
| 163 | #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) |
| 164 | #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) |
| 165 | #define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */ |
| 166 | #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) |
| 167 | #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) |
| 168 | #define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */ |
| 169 | #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) |
| 170 | #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) |
| 171 | #define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */ |
| 172 | #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) |
| 173 | #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) |
| 174 | #define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */ |
| 175 | #define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) |
| 176 | #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) |
| 177 | #define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */ |
| 178 | #define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) |
| 179 | #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) |
| 180 | #define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */ |
| 181 | #define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) |
| 182 | #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) |
| 183 | #define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */ |
| 184 | #define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) |
| 185 | #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) |
| 186 | #define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */ |
| 187 | #define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) |
| 188 | #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) |
| 189 | #define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */ |
| 190 | #define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) |
| 191 | #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) |
| 192 | #define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */ |
| 193 | #define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) |
| 194 | #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) |
| 195 | #define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */ |
| 196 | #define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) |
| 197 | #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) |
| 198 | #define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */ |
| 199 | #define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) |
| 200 | #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) |
| 201 | #define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */ |
| 202 | #define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) |
| 203 | #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) |
| 204 | #define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */ |
| 205 | #define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) |
| 206 | #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) |
| 207 | #define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */ |
| 208 | #define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) |
| 209 | #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) |
| 210 | #define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */ |
| 211 | #define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) |
| 212 | #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) |
| 213 | #define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */ |
| 214 | #define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) |
| 215 | #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) |
| 216 | #define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */ |
| 217 | #define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) |
| 218 | #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) |
| 219 | #define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register\n */ |
| 220 | #define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) |
| 221 | #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) |
| 222 | #define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */ |
| 223 | #define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) |
| 224 | #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) |
| 225 | #define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */ |
| 226 | #define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) |
| 227 | #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) |
| 228 | #define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */ |
| 229 | #define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) |
| 230 | #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) |
| 231 | #define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */ |
| 232 | #define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) |
| 233 | #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) |
| 234 | #define pTIMER_ENABLE ((uint16_t volatile *)TIMER_ENABLE) /* Timer Enable Register */ |
| 235 | #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) |
| 236 | #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) |
| 237 | #define pTIMER_DISABLE ((uint16_t volatile *)TIMER_DISABLE) /* Timer Disable Register */ |
| 238 | #define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) |
| 239 | #define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) |
| 240 | #define pTIMER_STATUS ((uint32_t volatile *)TIMER_STATUS) /* Timer Status Register */ |
| 241 | #define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) |
| 242 | #define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) |
| 243 | #define pPORTFIO ((uint16_t volatile *)PORTFIO) /* Port F I/O Pin State Specify Register */ |
| 244 | #define bfin_read_PORTFIO() bfin_read16(PORTFIO) |
| 245 | #define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) |
| 246 | #define pPORTFIO_CLEAR ((uint16_t volatile *)PORTFIO_CLEAR) /* Port F I/O Peripheral Interrupt Clear Register */ |
| 247 | #define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) |
| 248 | #define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) |
| 249 | #define pPORTFIO_SET ((uint16_t volatile *)PORTFIO_SET) /* Port F I/O Peripheral Interrupt Set Register */ |
| 250 | #define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) |
| 251 | #define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) |
| 252 | #define pPORTFIO_TOGGLE ((uint16_t volatile *)PORTFIO_TOGGLE) /* Port F I/O Pin State Toggle Register */ |
| 253 | #define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) |
| 254 | #define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) |
| 255 | #define pPORTFIO_MASKA ((uint16_t volatile *)PORTFIO_MASKA) /* Port F I/O Mask State Specify Interrupt A Register */ |
| 256 | #define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) |
| 257 | #define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) |
| 258 | #define pPORTFIO_MASKA_CLEAR ((uint16_t volatile *)PORTFIO_MASKA_CLEAR) /* Port F I/O Mask Disable Interrupt A Register */ |
| 259 | #define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) |
| 260 | #define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) |
| 261 | #define pPORTFIO_MASKA_SET ((uint16_t volatile *)PORTFIO_MASKA_SET) /* Port F I/O Mask Enable Interrupt A Register */ |
| 262 | #define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) |
| 263 | #define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) |
| 264 | #define pPORTFIO_MASKA_TOGGLE ((uint16_t volatile *)PORTFIO_MASKA_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt A Register */ |
| 265 | #define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) |
| 266 | #define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) |
| 267 | #define pPORTFIO_MASKB ((uint16_t volatile *)PORTFIO_MASKB) /* Port F I/O Mask State Specify Interrupt B Register */ |
| 268 | #define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) |
| 269 | #define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) |
| 270 | #define pPORTFIO_MASKB_CLEAR ((uint16_t volatile *)PORTFIO_MASKB_CLEAR) /* Port F I/O Mask Disable Interrupt B Register */ |
| 271 | #define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) |
| 272 | #define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) |
| 273 | #define pPORTFIO_MASKB_SET ((uint16_t volatile *)PORTFIO_MASKB_SET) /* Port F I/O Mask Enable Interrupt B Register */ |
| 274 | #define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) |
| 275 | #define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) |
| 276 | #define pPORTFIO_MASKB_TOGGLE ((uint16_t volatile *)PORTFIO_MASKB_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt B Register */ |
| 277 | #define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) |
| 278 | #define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) |
| 279 | #define pPORTFIO_DIR ((uint16_t volatile *)PORTFIO_DIR) /* Port F I/O Direction Register */ |
| 280 | #define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) |
| 281 | #define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) |
| 282 | #define pPORTFIO_POLAR ((uint16_t volatile *)PORTFIO_POLAR) /* Port F I/O Source Polarity Register */ |
| 283 | #define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) |
| 284 | #define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) |
| 285 | #define pPORTFIO_EDGE ((uint16_t volatile *)PORTFIO_EDGE) /* Port F I/O Source Sensitivity Register */ |
| 286 | #define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) |
| 287 | #define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) |
| 288 | #define pPORTFIO_BOTH ((uint16_t volatile *)PORTFIO_BOTH) /* Port F I/O Set on BOTH Edges Register */ |
| 289 | #define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) |
| 290 | #define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) |
| 291 | #define pPORTFIO_INEN ((uint16_t volatile *)PORTFIO_INEN) /* Port F I/O Input Enable Register */ |
| 292 | #define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) |
| 293 | #define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) |
| 294 | #define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */ |
| 295 | #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) |
| 296 | #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) |
| 297 | #define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */ |
| 298 | #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) |
| 299 | #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) |
| 300 | #define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */ |
| 301 | #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) |
| 302 | #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) |
| 303 | #define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */ |
| 304 | #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) |
| 305 | #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) |
| 306 | #define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */ |
| 307 | #define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) |
| 308 | #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) |
| 309 | #define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */ |
| 310 | #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) |
| 311 | #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) |
| 312 | #define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */ |
| 313 | #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) |
| 314 | #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) |
| 315 | #define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */ |
| 316 | #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) |
| 317 | #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) |
| 318 | #define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */ |
| 319 | #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) |
| 320 | #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) |
| 321 | #define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */ |
| 322 | #define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) |
| 323 | #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) |
| 324 | #define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */ |
| 325 | #define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) |
| 326 | #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) |
| 327 | #define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */ |
| 328 | #define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) |
| 329 | #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) |
| 330 | #define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */ |
| 331 | #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) |
| 332 | #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) |
| 333 | #define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */ |
| 334 | #define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) |
| 335 | #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) |
| 336 | #define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi-Channel Transmit Select Register 0 */ |
| 337 | #define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) |
| 338 | #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) |
| 339 | #define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi-Channel Transmit Select Register 1 */ |
| 340 | #define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) |
| 341 | #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) |
| 342 | #define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi-Channel Transmit Select Register 2 */ |
| 343 | #define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) |
| 344 | #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) |
| 345 | #define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi-Channel Transmit Select Register 3 */ |
| 346 | #define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) |
| 347 | #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) |
| 348 | #define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi-Channel Receive Select Register 0 */ |
| 349 | #define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) |
| 350 | #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) |
| 351 | #define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel Receive Select Register 1 */ |
| 352 | #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) |
| 353 | #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) |
| 354 | #define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi-Channel Receive Select Register 2 */ |
| 355 | #define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) |
| 356 | #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) |
| 357 | #define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi-Channel Receive Select Register 3 */ |
| 358 | #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) |
| 359 | #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) |
| 360 | #define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */ |
| 361 | #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) |
| 362 | #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) |
| 363 | #define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */ |
| 364 | #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) |
| 365 | #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) |
| 366 | #define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */ |
| 367 | #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) |
| 368 | #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) |
| 369 | #define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */ |
| 370 | #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) |
| 371 | #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) |
| 372 | #define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */ |
| 373 | #define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) |
| 374 | #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) |
| 375 | #define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */ |
| 376 | #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) |
| 377 | #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) |
| 378 | #define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */ |
| 379 | #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) |
| 380 | #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) |
| 381 | #define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */ |
| 382 | #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) |
| 383 | #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) |
| 384 | #define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */ |
| 385 | #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) |
| 386 | #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) |
| 387 | #define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */ |
| 388 | #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) |
| 389 | #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) |
| 390 | #define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */ |
| 391 | #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) |
| 392 | #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) |
| 393 | #define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */ |
| 394 | #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) |
| 395 | #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) |
| 396 | #define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */ |
| 397 | #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) |
| 398 | #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) |
| 399 | #define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */ |
| 400 | #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) |
| 401 | #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) |
| 402 | #define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi-Channel Transmit Select Register 0 */ |
| 403 | #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) |
| 404 | #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) |
| 405 | #define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi-Channel Transmit Select Register 1 */ |
| 406 | #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) |
| 407 | #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) |
| 408 | #define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi-Channel Transmit Select Register 2 */ |
| 409 | #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) |
| 410 | #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) |
| 411 | #define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi-Channel Transmit Select Register 3 */ |
| 412 | #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) |
| 413 | #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) |
| 414 | #define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi-Channel Receive Select Register 0 */ |
| 415 | #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) |
| 416 | #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) |
| 417 | #define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi-Channel Receive Select Register 1 */ |
| 418 | #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) |
| 419 | #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) |
| 420 | #define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi-Channel Receive Select Register 2 */ |
| 421 | #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) |
| 422 | #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) |
| 423 | #define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi-Channel Receive Select Register 3 */ |
| 424 | #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) |
| 425 | #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) |
| 426 | #define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */ |
| 427 | #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) |
| 428 | #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) |
| 429 | #define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register 0 */ |
| 430 | #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) |
| 431 | #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) |
| 432 | #define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register 1 */ |
| 433 | #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) |
| 434 | #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) |
| 435 | #define pEBIU_SDGCTL ((uint32_t volatile *)EBIU_SDGCTL) /* SDRAM Global Control Register */ |
| 436 | #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) |
| 437 | #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) |
| 438 | #define pEBIU_SDBCTL ((uint16_t volatile *)EBIU_SDBCTL) /* SDRAM Bank Control Register */ |
| 439 | #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) |
| 440 | #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) |
| 441 | #define pEBIU_SDRRC ((uint16_t volatile *)EBIU_SDRRC) /* SDRAM Refresh Rate Control Register */ |
| 442 | #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) |
| 443 | #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) |
| 444 | #define pEBIU_SDSTAT ((uint16_t volatile *)EBIU_SDSTAT) /* SDRAM Status Register */ |
| 445 | #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) |
| 446 | #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) |
| 447 | #define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */ |
| 448 | #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) |
| 449 | #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) |
| 450 | #define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */ |
| 451 | #define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) |
| 452 | #define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) |
| 453 | #define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */ |
| 454 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) |
| 455 | #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) |
| 456 | #define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */ |
| 457 | #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) |
| 458 | #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) |
| 459 | #define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */ |
| 460 | #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) |
| 461 | #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) |
| 462 | #define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */ |
| 463 | #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) |
| 464 | #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) |
| 465 | #define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */ |
| 466 | #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) |
| 467 | #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) |
| 468 | #define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */ |
| 469 | #define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) |
| 470 | #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) |
| 471 | #define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */ |
| 472 | #define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) |
| 473 | #define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) |
| 474 | #define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */ |
| 475 | #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) |
| 476 | #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) |
| 477 | #define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */ |
| 478 | #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) |
| 479 | #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) |
| 480 | #define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */ |
| 481 | #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) |
| 482 | #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) |
| 483 | #define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */ |
| 484 | #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) |
| 485 | #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) |
| 486 | #define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */ |
| 487 | #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) |
| 488 | #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) |
| 489 | #define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */ |
| 490 | #define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) |
| 491 | #define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) |
| 492 | #define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */ |
| 493 | #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) |
| 494 | #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) |
| 495 | #define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */ |
| 496 | #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) |
| 497 | #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) |
| 498 | #define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */ |
| 499 | #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) |
| 500 | #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) |
| 501 | #define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */ |
| 502 | #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) |
| 503 | #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) |
| 504 | #define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */ |
| 505 | #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) |
| 506 | #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) |
| 507 | #define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */ |
| 508 | #define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) |
| 509 | #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) |
| 510 | #define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */ |
| 511 | #define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) |
| 512 | #define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) |
| 513 | #define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */ |
| 514 | #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) |
| 515 | #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) |
| 516 | #define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */ |
| 517 | #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) |
| 518 | #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) |
| 519 | #define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */ |
| 520 | #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) |
| 521 | #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) |
| 522 | #define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */ |
| 523 | #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) |
| 524 | #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) |
| 525 | #define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */ |
| 526 | #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) |
| 527 | #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) |
| 528 | #define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */ |
| 529 | #define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) |
| 530 | #define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) |
| 531 | #define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */ |
| 532 | #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) |
| 533 | #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) |
| 534 | #define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */ |
| 535 | #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) |
| 536 | #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) |
| 537 | #define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */ |
| 538 | #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) |
| 539 | #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) |
| 540 | #define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */ |
| 541 | #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) |
| 542 | #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) |
| 543 | #define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */ |
| 544 | #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) |
| 545 | #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) |
| 546 | #define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */ |
| 547 | #define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) |
| 548 | #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) |
| 549 | #define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */ |
| 550 | #define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) |
| 551 | #define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) |
| 552 | #define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */ |
| 553 | #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) |
| 554 | #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) |
| 555 | #define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */ |
| 556 | #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) |
| 557 | #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) |
| 558 | #define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */ |
| 559 | #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) |
| 560 | #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) |
| 561 | #define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */ |
| 562 | #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) |
| 563 | #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) |
| 564 | #define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */ |
| 565 | #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) |
| 566 | #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) |
| 567 | #define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */ |
| 568 | #define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) |
| 569 | #define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) |
| 570 | #define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */ |
| 571 | #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) |
| 572 | #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) |
| 573 | #define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */ |
| 574 | #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) |
| 575 | #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) |
| 576 | #define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */ |
| 577 | #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) |
| 578 | #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) |
| 579 | #define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */ |
| 580 | #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) |
| 581 | #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) |
| 582 | #define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */ |
| 583 | #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) |
| 584 | #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) |
| 585 | #define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */ |
| 586 | #define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) |
| 587 | #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) |
| 588 | #define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */ |
| 589 | #define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) |
| 590 | #define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) |
| 591 | #define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */ |
| 592 | #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) |
| 593 | #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) |
| 594 | #define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */ |
| 595 | #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) |
| 596 | #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) |
| 597 | #define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */ |
| 598 | #define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) |
| 599 | #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) |
| 600 | #define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */ |
| 601 | #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) |
| 602 | #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) |
| 603 | #define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */ |
| 604 | #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) |
| 605 | #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) |
| 606 | #define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */ |
| 607 | #define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) |
| 608 | #define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) |
| 609 | #define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */ |
| 610 | #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) |
| 611 | #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) |
| 612 | #define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */ |
| 613 | #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) |
| 614 | #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) |
| 615 | #define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */ |
| 616 | #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) |
| 617 | #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) |
| 618 | #define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */ |
| 619 | #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) |
| 620 | #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) |
| 621 | #define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */ |
| 622 | #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) |
| 623 | #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) |
| 624 | #define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */ |
| 625 | #define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) |
| 626 | #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) |
| 627 | #define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */ |
| 628 | #define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) |
| 629 | #define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) |
| 630 | #define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */ |
| 631 | #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) |
| 632 | #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) |
| 633 | #define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */ |
| 634 | #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) |
| 635 | #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) |
| 636 | #define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */ |
| 637 | #define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) |
| 638 | #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) |
| 639 | #define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */ |
| 640 | #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) |
| 641 | #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) |
| 642 | #define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */ |
| 643 | #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) |
| 644 | #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) |
| 645 | #define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */ |
| 646 | #define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) |
| 647 | #define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) |
| 648 | #define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */ |
| 649 | #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) |
| 650 | #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) |
| 651 | #define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */ |
| 652 | #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) |
| 653 | #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) |
| 654 | #define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */ |
| 655 | #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) |
| 656 | #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) |
| 657 | #define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */ |
| 658 | #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) |
| 659 | #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) |
| 660 | #define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */ |
| 661 | #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) |
| 662 | #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) |
| 663 | #define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */ |
| 664 | #define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) |
| 665 | #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) |
| 666 | #define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */ |
| 667 | #define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) |
| 668 | #define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) |
| 669 | #define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */ |
| 670 | #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) |
| 671 | #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) |
| 672 | #define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */ |
| 673 | #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) |
| 674 | #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) |
| 675 | #define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */ |
| 676 | #define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) |
| 677 | #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) |
| 678 | #define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */ |
| 679 | #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) |
| 680 | #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) |
| 681 | #define pDMA6_NEXT_DESC_PTR ((uint32_t volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */ |
| 682 | #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) |
| 683 | #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) |
| 684 | #define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */ |
| 685 | #define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) |
| 686 | #define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) |
| 687 | #define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */ |
| 688 | #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) |
| 689 | #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) |
| 690 | #define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */ |
| 691 | #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) |
| 692 | #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) |
| 693 | #define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */ |
| 694 | #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) |
| 695 | #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) |
| 696 | #define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */ |
| 697 | #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) |
| 698 | #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) |
| 699 | #define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */ |
| 700 | #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) |
| 701 | #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) |
| 702 | #define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */ |
| 703 | #define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) |
| 704 | #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) |
| 705 | #define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */ |
| 706 | #define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) |
| 707 | #define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) |
| 708 | #define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */ |
| 709 | #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) |
| 710 | #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) |
| 711 | #define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */ |
| 712 | #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) |
| 713 | #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) |
| 714 | #define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */ |
| 715 | #define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) |
| 716 | #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) |
| 717 | #define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */ |
| 718 | #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) |
| 719 | #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) |
| 720 | #define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */ |
| 721 | #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) |
| 722 | #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) |
| 723 | #define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */ |
| 724 | #define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) |
| 725 | #define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) |
| 726 | #define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */ |
| 727 | #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) |
| 728 | #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) |
| 729 | #define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */ |
| 730 | #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) |
| 731 | #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) |
| 732 | #define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */ |
| 733 | #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) |
| 734 | #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) |
| 735 | #define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */ |
| 736 | #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) |
| 737 | #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) |
| 738 | #define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */ |
| 739 | #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) |
| 740 | #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) |
| 741 | #define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */ |
| 742 | #define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) |
| 743 | #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) |
| 744 | #define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */ |
| 745 | #define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) |
| 746 | #define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) |
| 747 | #define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */ |
| 748 | #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) |
| 749 | #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) |
| 750 | #define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */ |
| 751 | #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) |
| 752 | #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) |
| 753 | #define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */ |
| 754 | #define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) |
| 755 | #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) |
| 756 | #define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */ |
| 757 | #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) |
| 758 | #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) |
| 759 | #define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */ |
| 760 | #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) |
| 761 | #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) |
| 762 | #define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */ |
| 763 | #define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) |
| 764 | #define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) |
| 765 | #define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */ |
| 766 | #define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) |
| 767 | #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) |
| 768 | #define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */ |
| 769 | #define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) |
| 770 | #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) |
| 771 | #define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */ |
| 772 | #define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) |
| 773 | #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) |
| 774 | #define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */ |
| 775 | #define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) |
| 776 | #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) |
| 777 | #define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */ |
| 778 | #define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) |
| 779 | #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) |
| 780 | #define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */ |
| 781 | #define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) |
| 782 | #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) |
| 783 | #define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */ |
| 784 | #define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) |
| 785 | #define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) |
| 786 | #define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */ |
| 787 | #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) |
| 788 | #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) |
| 789 | #define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */ |
| 790 | #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) |
| 791 | #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) |
| 792 | #define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */ |
| 793 | #define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) |
| 794 | #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) |
| 795 | #define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */ |
| 796 | #define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) |
| 797 | #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) |
| 798 | #define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */ |
| 799 | #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) |
| 800 | #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) |
| 801 | #define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */ |
| 802 | #define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) |
| 803 | #define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) |
| 804 | #define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */ |
| 805 | #define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) |
| 806 | #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) |
| 807 | #define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */ |
| 808 | #define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) |
| 809 | #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) |
| 810 | #define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */ |
| 811 | #define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) |
| 812 | #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) |
| 813 | #define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */ |
| 814 | #define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) |
| 815 | #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) |
| 816 | #define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */ |
| 817 | #define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) |
| 818 | #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) |
| 819 | #define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */ |
| 820 | #define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) |
| 821 | #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) |
| 822 | #define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */ |
| 823 | #define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) |
| 824 | #define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) |
| 825 | #define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */ |
| 826 | #define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) |
| 827 | #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) |
| 828 | #define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */ |
| 829 | #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) |
| 830 | #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) |
| 831 | #define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */ |
| 832 | #define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) |
| 833 | #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) |
| 834 | #define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */ |
| 835 | #define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) |
| 836 | #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) |
| 837 | #define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */ |
| 838 | #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) |
| 839 | #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) |
| 840 | #define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */ |
| 841 | #define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) |
| 842 | #define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) |
| 843 | #define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */ |
| 844 | #define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) |
| 845 | #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) |
| 846 | #define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */ |
| 847 | #define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) |
| 848 | #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) |
| 849 | #define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */ |
| 850 | #define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) |
| 851 | #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) |
| 852 | #define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */ |
| 853 | #define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) |
| 854 | #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) |
| 855 | #define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */ |
| 856 | #define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) |
| 857 | #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) |
| 858 | #define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */ |
| 859 | #define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) |
| 860 | #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) |
| 861 | #define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */ |
| 862 | #define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) |
| 863 | #define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) |
| 864 | #define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */ |
| 865 | #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) |
| 866 | #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) |
| 867 | #define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */ |
| 868 | #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) |
| 869 | #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) |
| 870 | #define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */ |
| 871 | #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) |
| 872 | #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) |
| 873 | #define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */ |
| 874 | #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) |
| 875 | #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) |
| 876 | #define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */ |
| 877 | #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) |
| 878 | #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) |
| 879 | #define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */ |
| 880 | #define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) |
| 881 | #define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) |
| 882 | #define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */ |
| 883 | #define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) |
| 884 | #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) |
| 885 | #define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */ |
| 886 | #define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) |
| 887 | #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) |
| 888 | #define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */ |
| 889 | #define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) |
| 890 | #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) |
| 891 | #define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */ |
| 892 | #define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) |
| 893 | #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) |
| 894 | #define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */ |
| 895 | #define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) |
| 896 | #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) |
| 897 | #define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */ |
| 898 | #define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) |
| 899 | #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) |
| 900 | #define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */ |
| 901 | #define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) |
| 902 | #define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) |
| 903 | #define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */ |
| 904 | #define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) |
| 905 | #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) |
| 906 | #define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */ |
| 907 | #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) |
| 908 | #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) |
| 909 | #define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */ |
| 910 | #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) |
| 911 | #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) |
| 912 | #define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */ |
| 913 | #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) |
| 914 | #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) |
| 915 | #define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ |
| 916 | #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) |
| 917 | #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) |
| 918 | #define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* MemDMA Stream 0 Source Start Address Register */ |
| 919 | #define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) |
| 920 | #define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) |
| 921 | #define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* MemDMA Stream 0 Source Configuration Register */ |
| 922 | #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) |
| 923 | #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) |
| 924 | #define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* MemDMA Stream 0 Source X Count Register */ |
| 925 | #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) |
| 926 | #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) |
| 927 | #define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* MemDMA Stream 0 Source X Modify Register */ |
| 928 | #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) |
| 929 | #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) |
| 930 | #define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* MemDMA Stream 0 Source Y Count Register */ |
| 931 | #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) |
| 932 | #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) |
| 933 | #define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* MemDMA Stream 0 Source Y Modify Register */ |
| 934 | #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) |
| 935 | #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) |
| 936 | #define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ |
| 937 | #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) |
| 938 | #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) |
| 939 | #define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* MemDMA Stream 0 Source Current Address Register */ |
| 940 | #define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) |
| 941 | #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) |
| 942 | #define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* MemDMA Stream 0 Source Interrupt/Status Register */ |
| 943 | #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) |
| 944 | #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) |
| 945 | #define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* MemDMA Stream 0 Source Peripheral Map Register */ |
| 946 | #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) |
| 947 | #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) |
| 948 | #define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* MemDMA Stream 0 Source Current X Count Register */ |
| 949 | #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) |
| 950 | #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) |
| 951 | #define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* MemDMA Stream 0 Source Current Y Count Register */ |
| 952 | #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) |
| 953 | #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) |
| 954 | #define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ |
| 955 | #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) |
| 956 | #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) |
| 957 | #define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* MemDMA Stream 0 Destination Start Address Register */ |
| 958 | #define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) |
| 959 | #define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) |
| 960 | #define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* MemDMA Stream 0 Destination Configuration Register */ |
| 961 | #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) |
| 962 | #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) |
| 963 | #define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* MemDMA Stream 0 Destination X Count Register */ |
| 964 | #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) |
| 965 | #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) |
| 966 | #define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* MemDMA Stream 0 Destination X Modify Register */ |
| 967 | #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) |
| 968 | #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) |
| 969 | #define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* MemDMA Stream 0 Destination Y Count Register */ |
| 970 | #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) |
| 971 | #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) |
| 972 | #define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* MemDMA Stream 0 Destination Y Modify Register */ |
| 973 | #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) |
| 974 | #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) |
| 975 | #define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ |
| 976 | #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) |
| 977 | #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) |
| 978 | #define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* MemDMA Stream 0 Destination Current Address Register */ |
| 979 | #define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) |
| 980 | #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) |
| 981 | #define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* MemDMA Stream 0 Destination Interrupt/Status Register */ |
| 982 | #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) |
| 983 | #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) |
| 984 | #define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* MemDMA Stream 0 Destination Peripheral Map Register */ |
| 985 | #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) |
| 986 | #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) |
| 987 | #define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* MemDMA Stream 0 Destination Current X Count Register */ |
| 988 | #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) |
| 989 | #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) |
| 990 | #define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* MemDMA Stream 0 Destination Current Y Count Register */ |
| 991 | #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) |
| 992 | #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) |
| 993 | #define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ |
| 994 | #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) |
| 995 | #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) |
| 996 | #define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* MemDMA Stream 1 Source Start Address Register */ |
| 997 | #define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) |
| 998 | #define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) |
| 999 | #define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* MemDMA Stream 1 Source Configuration Register */ |
| 1000 | #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) |
| 1001 | #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) |
| 1002 | #define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* MemDMA Stream 1 Source X Count Register */ |
| 1003 | #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) |
| 1004 | #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) |
| 1005 | #define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* MemDMA Stream 1 Source X Modify Register */ |
| 1006 | #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) |
| 1007 | #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) |
| 1008 | #define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* MemDMA Stream 1 Source Y Count Register */ |
| 1009 | #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) |
| 1010 | #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) |
| 1011 | #define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* MemDMA Stream 1 Source Y Modify Register */ |
| 1012 | #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) |
| 1013 | #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) |
| 1014 | #define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ |
| 1015 | #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) |
| 1016 | #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) |
| 1017 | #define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* MemDMA Stream 1 Source Current Address Register */ |
| 1018 | #define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) |
| 1019 | #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) |
| 1020 | #define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* MemDMA Stream 1 Source Interrupt/Status Register */ |
| 1021 | #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) |
| 1022 | #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) |
| 1023 | #define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* MemDMA Stream 1 Source Peripheral Map Register */ |
| 1024 | #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) |
| 1025 | #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) |
| 1026 | #define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* MemDMA Stream 1 Source Current X Count Register */ |
| 1027 | #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) |
| 1028 | #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) |
| 1029 | #define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* MemDMA Stream 1 Source Current Y Count Register */ |
| 1030 | #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) |
| 1031 | #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) |
| 1032 | #define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ |
| 1033 | #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) |
| 1034 | #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) |
| 1035 | #define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* MemDMA Stream 1 Destination Start Address Register */ |
| 1036 | #define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) |
| 1037 | #define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) |
| 1038 | #define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */ |
| 1039 | #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) |
| 1040 | #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) |
| 1041 | #define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* MemDMA Stream 1 Destination X Count Register */ |
| 1042 | #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) |
| 1043 | #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) |
| 1044 | #define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* MemDMA Stream 1 Destination X Modify Register */ |
| 1045 | #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) |
| 1046 | #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) |
| 1047 | #define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* MemDMA Stream 1 Destination Y Count Register */ |
| 1048 | #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) |
| 1049 | #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) |
| 1050 | #define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* MemDMA Stream 1 Destination Y Modify Register */ |
| 1051 | #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) |
| 1052 | #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) |
| 1053 | #define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ |
| 1054 | #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) |
| 1055 | #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) |
| 1056 | #define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* MemDMA Stream 1 Destination Current Address Register */ |
| 1057 | #define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) |
| 1058 | #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) |
| 1059 | #define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* MemDMA Stream 1 Destination Interrupt/Status Register */ |
| 1060 | #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) |
| 1061 | #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) |
| 1062 | #define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* MemDMA Stream 1 Destination Peripheral Map Register */ |
| 1063 | #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) |
| 1064 | #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) |
| 1065 | #define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* MemDMA Stream 1 Destination Current X Count Register */ |
| 1066 | #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) |
| 1067 | #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) |
| 1068 | #define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* MemDMA Stream 1 Destination Current Y Count Register */ |
| 1069 | #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) |
| 1070 | #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) |
| 1071 | #define pPPI_CONTROL ((uint16_t volatile *)PPI_CONTROL) /* PPI Control Register */ |
| 1072 | #define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) |
| 1073 | #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) |
| 1074 | #define pPPI_STATUS ((uint16_t volatile *)PPI_STATUS) /* PPI Status Register */ |
| 1075 | #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) |
| 1076 | #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) |
| 1077 | #define pPPI_COUNT ((uint16_t volatile *)PPI_COUNT) /* PPI Transfer Count Register */ |
| 1078 | #define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) |
| 1079 | #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) |
| 1080 | #define pPPI_DELAY ((uint16_t volatile *)PPI_DELAY) /* PPI Delay Count Register */ |
| 1081 | #define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) |
| 1082 | #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) |
| 1083 | #define pPPI_FRAME ((uint16_t volatile *)PPI_FRAME) /* PPI Frame Length Register */ |
| 1084 | #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) |
| 1085 | #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) |
| 1086 | #define pTWI_CLKDIV ((uint16_t volatile *)TWI_CLKDIV) /* Serial Clock Divider Register */ |
| 1087 | #define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV) |
| 1088 | #define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val) |
| 1089 | #define pTWI_CONTROL ((uint16_t volatile *)TWI_CONTROL) /* TWI Control Register */ |
| 1090 | #define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL) |
| 1091 | #define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val) |
| 1092 | #define pTWI_SLAVE_CTL ((uint16_t volatile *)TWI_SLAVE_CTL) /* Slave Mode Control Register */ |
| 1093 | #define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL) |
| 1094 | #define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val) |
| 1095 | #define pTWI_SLAVE_STAT ((uint16_t volatile *)TWI_SLAVE_STAT) /* Slave Mode Status Register */ |
| 1096 | #define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT) |
| 1097 | #define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val) |
| 1098 | #define pTWI_SLAVE_ADDR ((uint16_t volatile *)TWI_SLAVE_ADDR) /* Slave Mode Address Register */ |
| 1099 | #define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR) |
| 1100 | #define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val) |
| 1101 | #define pTWI_MASTER_CTL ((uint16_t volatile *)TWI_MASTER_CTL) /* Master Mode Control Register */ |
| 1102 | #define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL) |
| 1103 | #define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val) |
| 1104 | #define pTWI_MASTER_STAT ((uint16_t volatile *)TWI_MASTER_STAT) /* Master Mode Status Register */ |
| 1105 | #define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT) |
| 1106 | #define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val) |
| 1107 | #define pTWI_MASTER_ADDR ((uint16_t volatile *)TWI_MASTER_ADDR) /* Master Mode Address Register */ |
| 1108 | #define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR) |
| 1109 | #define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val) |
| 1110 | #define pTWI_INT_STAT ((uint16_t volatile *)TWI_INT_STAT) /* TWI Interrupt Status Register */ |
| 1111 | #define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT) |
| 1112 | #define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val) |
| 1113 | #define pTWI_INT_MASK ((uint16_t volatile *)TWI_INT_MASK) /* TWI Master Interrupt Mask Register */ |
| 1114 | #define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK) |
| 1115 | #define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val) |
| 1116 | #define pTWI_FIFO_CTL ((uint16_t volatile *)TWI_FIFO_CTL) /* FIFO Control Register */ |
| 1117 | #define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL) |
| 1118 | #define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val) |
| 1119 | #define pTWI_FIFO_STAT ((uint16_t volatile *)TWI_FIFO_STAT) /* FIFO Status Register */ |
| 1120 | #define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT) |
| 1121 | #define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val) |
| 1122 | #define pTWI_XMT_DATA8 ((uint16_t volatile *)TWI_XMT_DATA8) /* FIFO Transmit Data Single Byte Register */ |
| 1123 | #define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8) |
| 1124 | #define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val) |
| 1125 | #define pTWI_XMT_DATA16 ((uint16_t volatile *)TWI_XMT_DATA16) /* FIFO Transmit Data Double Byte Register */ |
| 1126 | #define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16) |
| 1127 | #define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val) |
| 1128 | #define pTWI_RCV_DATA8 ((uint16_t volatile *)TWI_RCV_DATA8) /* FIFO Receive Data Single Byte Register */ |
| 1129 | #define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8) |
| 1130 | #define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val) |
| 1131 | #define pTWI_RCV_DATA16 ((uint16_t volatile *)TWI_RCV_DATA16) /* FIFO Receive Data Double Byte Register */ |
| 1132 | #define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16) |
| 1133 | #define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val) |
| 1134 | #define pPORTGIO ((uint16_t volatile *)PORTGIO) /* Port G I/O Pin State Specify Register */ |
| 1135 | #define bfin_read_PORTGIO() bfin_read16(PORTGIO) |
| 1136 | #define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) |
| 1137 | #define pPORTGIO_CLEAR ((uint16_t volatile *)PORTGIO_CLEAR) /* Port G I/O Peripheral Interrupt Clear Register */ |
| 1138 | #define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) |
| 1139 | #define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) |
| 1140 | #define pPORTGIO_SET ((uint16_t volatile *)PORTGIO_SET) /* Port G I/O Peripheral Interrupt Set Register */ |
| 1141 | #define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) |
| 1142 | #define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) |
| 1143 | #define pPORTGIO_TOGGLE ((uint16_t volatile *)PORTGIO_TOGGLE) /* Port G I/O Pin State Toggle Register */ |
| 1144 | #define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) |
| 1145 | #define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) |
| 1146 | #define pPORTGIO_MASKA ((uint16_t volatile *)PORTGIO_MASKA) /* Port G I/O Mask State Specify Interrupt A Register */ |
| 1147 | #define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) |
| 1148 | #define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) |
| 1149 | #define pPORTGIO_MASKA_CLEAR ((uint16_t volatile *)PORTGIO_MASKA_CLEAR) /* Port G I/O Mask Disable Interrupt A Register */ |
| 1150 | #define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) |
| 1151 | #define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) |
| 1152 | #define pPORTGIO_MASKA_SET ((uint16_t volatile *)PORTGIO_MASKA_SET) /* Port G I/O Mask Enable Interrupt A Register */ |
| 1153 | #define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) |
| 1154 | #define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) |
| 1155 | #define pPORTGIO_MASKA_TOGGLE ((uint16_t volatile *)PORTGIO_MASKA_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt A Register */ |
| 1156 | #define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) |
| 1157 | #define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) |
| 1158 | #define pPORTGIO_MASKB ((uint16_t volatile *)PORTGIO_MASKB) /* Port G I/O Mask State Specify Interrupt B Register */ |
| 1159 | #define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) |
| 1160 | #define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) |
| 1161 | #define pPORTGIO_MASKB_CLEAR ((uint16_t volatile *)PORTGIO_MASKB_CLEAR) /* Port G I/O Mask Disable Interrupt B Register */ |
| 1162 | #define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) |
| 1163 | #define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) |
| 1164 | #define pPORTGIO_MASKB_SET ((uint16_t volatile *)PORTGIO_MASKB_SET) /* Port G I/O Mask Enable Interrupt B Register */ |
| 1165 | #define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) |
| 1166 | #define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) |
| 1167 | #define pPORTGIO_MASKB_TOGGLE ((uint16_t volatile *)PORTGIO_MASKB_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt B Register */ |
| 1168 | #define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) |
| 1169 | #define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) |
| 1170 | #define pPORTGIO_DIR ((uint16_t volatile *)PORTGIO_DIR) /* Port G I/O Direction Register */ |
| 1171 | #define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) |
| 1172 | #define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) |
| 1173 | #define pPORTGIO_POLAR ((uint16_t volatile *)PORTGIO_POLAR) /* Port G I/O Source Polarity Register */ |
| 1174 | #define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) |
| 1175 | #define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) |
| 1176 | #define pPORTGIO_EDGE ((uint16_t volatile *)PORTGIO_EDGE) /* Port G I/O Source Sensitivity Register */ |
| 1177 | #define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) |
| 1178 | #define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) |
| 1179 | #define pPORTGIO_BOTH ((uint16_t volatile *)PORTGIO_BOTH) /* Port G I/O Set on BOTH Edges Register */ |
| 1180 | #define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) |
| 1181 | #define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) |
| 1182 | #define pPORTGIO_INEN ((uint16_t volatile *)PORTGIO_INEN) /* Port G I/O Input Enable Register */ |
| 1183 | #define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) |
| 1184 | #define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) |
| 1185 | #define pPORTHIO ((uint16_t volatile *)PORTHIO) /* Port H I/O Pin State Specify Register */ |
| 1186 | #define bfin_read_PORTHIO() bfin_read16(PORTHIO) |
| 1187 | #define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) |
| 1188 | #define pPORTHIO_CLEAR ((uint16_t volatile *)PORTHIO_CLEAR) /* Port H I/O Peripheral Interrupt Clear Register */ |
| 1189 | #define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) |
| 1190 | #define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) |
| 1191 | #define pPORTHIO_SET ((uint16_t volatile *)PORTHIO_SET) /* Port H I/O Peripheral Interrupt Set Register */ |
| 1192 | #define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) |
| 1193 | #define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) |
| 1194 | #define pPORTHIO_TOGGLE ((uint16_t volatile *)PORTHIO_TOGGLE) /* Port H I/O Pin State Toggle Register */ |
| 1195 | #define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) |
| 1196 | #define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) |
| 1197 | #define pPORTHIO_MASKA ((uint16_t volatile *)PORTHIO_MASKA) /* Port H I/O Mask State Specify Interrupt A Register */ |
| 1198 | #define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) |
| 1199 | #define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) |
| 1200 | #define pPORTHIO_MASKA_CLEAR ((uint16_t volatile *)PORTHIO_MASKA_CLEAR) /* Port H I/O Mask Disable Interrupt A Register */ |
| 1201 | #define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) |
| 1202 | #define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) |
| 1203 | #define pPORTHIO_MASKA_SET ((uint16_t volatile *)PORTHIO_MASKA_SET) /* Port H I/O Mask Enable Interrupt A Register */ |
| 1204 | #define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) |
| 1205 | #define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) |
| 1206 | #define pPORTHIO_MASKA_TOGGLE ((uint16_t volatile *)PORTHIO_MASKA_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt A Register */ |
| 1207 | #define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) |
| 1208 | #define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) |
| 1209 | #define pPORTHIO_MASKB ((uint16_t volatile *)PORTHIO_MASKB) /* Port H I/O Mask State Specify Interrupt B Register */ |
| 1210 | #define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) |
| 1211 | #define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) |
| 1212 | #define pPORTHIO_MASKB_CLEAR ((uint16_t volatile *)PORTHIO_MASKB_CLEAR) /* Port H I/O Mask Disable Interrupt B Register */ |
| 1213 | #define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) |
| 1214 | #define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) |
| 1215 | #define pPORTHIO_MASKB_SET ((uint16_t volatile *)PORTHIO_MASKB_SET) /* Port H I/O Mask Enable Interrupt B Register */ |
| 1216 | #define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) |
| 1217 | #define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) |
| 1218 | #define pPORTHIO_MASKB_TOGGLE ((uint16_t volatile *)PORTHIO_MASKB_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt B Register */ |
| 1219 | #define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) |
| 1220 | #define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) |
| 1221 | #define pPORTHIO_DIR ((uint16_t volatile *)PORTHIO_DIR) /* Port H I/O Direction Register */ |
| 1222 | #define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) |
| 1223 | #define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) |
| 1224 | #define pPORTHIO_POLAR ((uint16_t volatile *)PORTHIO_POLAR) /* Port H I/O Source Polarity Register */ |
| 1225 | #define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) |
| 1226 | #define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) |
| 1227 | #define pPORTHIO_EDGE ((uint16_t volatile *)PORTHIO_EDGE) /* Port H I/O Source Sensitivity Register */ |
| 1228 | #define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) |
| 1229 | #define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) |
| 1230 | #define pPORTHIO_BOTH ((uint16_t volatile *)PORTHIO_BOTH) /* Port H I/O Set on BOTH Edges Register */ |
| 1231 | #define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) |
| 1232 | #define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) |
| 1233 | #define pPORTHIO_INEN ((uint16_t volatile *)PORTHIO_INEN) /* Port H I/O Input Enable Register */ |
| 1234 | #define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) |
| 1235 | #define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) |
| 1236 | #define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Holding register */ |
| 1237 | #define bfin_read_UART1_THR() bfin_read16(UART1_THR) |
| 1238 | #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) |
| 1239 | #define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer register */ |
| 1240 | #define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) |
| 1241 | #define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) |
| 1242 | #define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch (Low-Byte) */ |
| 1243 | #define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) |
| 1244 | #define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) |
| 1245 | #define pUART1_IER ((uint16_t volatile *)UART1_IER) /* Interrupt Enable Register */ |
| 1246 | #define bfin_read_UART1_IER() bfin_read16(UART1_IER) |
| 1247 | #define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) |
| 1248 | #define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch (High-Byte) */ |
| 1249 | #define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) |
| 1250 | #define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) |
| 1251 | #define pUART1_IIR ((uint16_t volatile *)UART1_IIR) /* Interrupt Identification Register */ |
| 1252 | #define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) |
| 1253 | #define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) |
| 1254 | #define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */ |
| 1255 | #define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) |
| 1256 | #define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) |
| 1257 | #define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */ |
| 1258 | #define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) |
| 1259 | #define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) |
| 1260 | #define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */ |
| 1261 | #define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) |
| 1262 | #define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) |
| 1263 | #define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */ |
| 1264 | #define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) |
| 1265 | #define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) |
| 1266 | #define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* SCR Scratch Register */ |
| 1267 | #define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) |
| 1268 | #define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) |
| 1269 | #define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */ |
| 1270 | #define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) |
| 1271 | #define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) |
| 1272 | #define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Port F Function Enable Register (Alternate/Flag*) */ |
| 1273 | #define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) |
| 1274 | #define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) |
| 1275 | #define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Port G Function Enable Register (Alternate/Flag*) */ |
| 1276 | #define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) |
| 1277 | #define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) |
| 1278 | #define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Port H Function Enable Register (Alternate/Flag*) */ |
| 1279 | #define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) |
| 1280 | #define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) |
| 1281 | #define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */ |
| 1282 | #define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) |
| 1283 | #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) |
| 1284 | #define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* HMDMA0 Initial Edge Count Register */ |
| 1285 | #define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) |
| 1286 | #define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) |
| 1287 | #define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* HMDMA0 Initial Block Count Register */ |
| 1288 | #define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) |
| 1289 | #define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) |
| 1290 | #define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* HMDMA0 Urgent Edge Count Threshhold Register */ |
| 1291 | #define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) |
| 1292 | #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) |
| 1293 | #define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* HMDMA0 Edge Count Overflow Interrupt Register */ |
| 1294 | #define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) |
| 1295 | #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) |
| 1296 | #define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* HMDMA0 Current Edge Count Register */ |
| 1297 | #define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) |
| 1298 | #define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) |
| 1299 | #define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* HMDMA0 Current Block Count Register */ |
| 1300 | #define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) |
| 1301 | #define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) |
| 1302 | #define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */ |
| 1303 | #define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) |
| 1304 | #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) |
| 1305 | #define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* HMDMA1 Initial Edge Count Register */ |
| 1306 | #define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) |
| 1307 | #define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) |
| 1308 | #define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* HMDMA1 Initial Block Count Register */ |
| 1309 | #define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) |
| 1310 | #define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) |
| 1311 | #define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* HMDMA1 Urgent Edge Count Threshhold Register */ |
| 1312 | #define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) |
| 1313 | #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) |
| 1314 | #define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* HMDMA1 Edge Count Overflow Interrupt Register */ |
| 1315 | #define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) |
| 1316 | #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) |
| 1317 | #define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* HMDMA1 Current Edge Count Register */ |
| 1318 | #define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) |
| 1319 | #define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) |
| 1320 | #define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* HMDMA1 Current Block Count Register */ |
| 1321 | #define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) |
| 1322 | #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) |
| 1323 | #define pPORTF_MUX ((uint16_t volatile *)PORTF_MUX) /* Port F mux control */ |
| 1324 | #define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX) |
| 1325 | #define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val) |
| 1326 | #define pPORTG_MUX ((uint16_t volatile *)PORTG_MUX) /* Port G mux control */ |
| 1327 | #define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX) |
| 1328 | #define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val) |
| 1329 | #define pPORTH_MUX ((uint16_t volatile *)PORTH_MUX) /* Port H mux control */ |
| 1330 | #define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX) |
| 1331 | #define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val) |
| 1332 | #define pPORTF_DRIVE ((uint16_t volatile *)PORTF_DRIVE) /* Port F drive strength control */ |
| 1333 | #define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE) |
| 1334 | #define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val) |
| 1335 | #define pPORTG_DRIVE ((uint16_t volatile *)PORTG_DRIVE) /* Port G drive strength control */ |
| 1336 | #define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE) |
| 1337 | #define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val) |
| 1338 | #define pPORTH_DRIVE ((uint16_t volatile *)PORTH_DRIVE) /* Port H drive strength control */ |
| 1339 | #define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE) |
| 1340 | #define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val) |
| 1341 | #define pPORTF_SLEW ((uint16_t volatile *)PORTF_SLEW) /* Port F slew control */ |
| 1342 | #define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW) |
| 1343 | #define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val) |
| 1344 | #define pPORTG_SLEW ((uint16_t volatile *)PORTG_SLEW) /* Port G slew control */ |
| 1345 | #define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW) |
| 1346 | #define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) |
| 1347 | #define pPORTH_SLEW ((uint16_t volatile *)PORTH_SLEW) /* Port H slew control */ |
| 1348 | #define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) |
| 1349 | #define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) |
| 1350 | #define pPORTF_HYSTERESIS ((uint16_t volatile *)PORTF_HYSTERESIS) /* Port F Schmitt trigger control */ |
| 1351 | #define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS) |
| 1352 | #define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val) |
| 1353 | #define pPORTG_HYSTERESIS ((uint16_t volatile *)PORTG_HYSTERESIS) /* Port G Schmitt trigger control */ |
| 1354 | #define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS) |
| 1355 | #define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val) |
| 1356 | #define pPORTH_HYSTERESIS ((uint16_t volatile *)PORTH_HYSTERESIS) /* Port H Schmitt trigger control */ |
| 1357 | #define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS) |
| 1358 | #define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val) |
| 1359 | #define pNONGPIO_DRIVE ((uint16_t volatile *)NONGPIO_DRIVE) /* Non-GPIO Port drive strength control */ |
| 1360 | #define bfin_read_NONGPIO_DRIVE() bfin_read16(NONGPIO_DRIVE) |
| 1361 | #define bfin_write_NONGPIO_DRIVE(val) bfin_write16(NONGPIO_DRIVE, val) |
| 1362 | #define pNONGPIO_SLEW ((uint16_t volatile *)NONGPIO_SLEW) /* Non-GPIO Port slew control */ |
| 1363 | #define bfin_read_NONGPIO_SLEW() bfin_read16(NONGPIO_SLEW) |
| 1364 | #define bfin_write_NONGPIO_SLEW(val) bfin_write16(NONGPIO_SLEW, val) |
| 1365 | #define pNONGPIO_HYSTERESIS ((uint16_t volatile *)NONGPIO_HYSTERESIS) /* Non-GPIO Port Schmitt trigger control */ |
| 1366 | #define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS) |
| 1367 | #define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val) |
| 1368 | #define pHOST_CONTROL ((uint16_t volatile *)HOST_CONTROL) /* HOST Control Register */ |
| 1369 | #define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) |
| 1370 | #define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) |
| 1371 | #define pHOST_STATUS ((uint16_t volatile *)HOST_STATUS) /* HOST Status Register */ |
| 1372 | #define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) |
| 1373 | #define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) |
| 1374 | #define pHOST_TIMEOUT ((uint16_t volatile *)HOST_TIMEOUT) /* HOST Acknowledge Mode Timeout Register */ |
| 1375 | #define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) |
| 1376 | #define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) |
| 1377 | #define pCNT_CONFIG ((uint16_t volatile *)CNT_CONFIG) /* Configuration/Control Register */ |
| 1378 | #define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) |
| 1379 | #define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) |
| 1380 | #define pCNT_IMASK ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */ |
| 1381 | #define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) |
| 1382 | #define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) |
| 1383 | #define pCNT_STATUS ((uint16_t volatile *)CNT_STATUS) /* Status Register */ |
| 1384 | #define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) |
| 1385 | #define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) |
| 1386 | #define pCNT_COMMAND ((uint16_t volatile *)CNT_COMMAND) /* Command Register */ |
| 1387 | #define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) |
| 1388 | #define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) |
| 1389 | #define pCNT_DEBOUNCE ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Prescaler Register */ |
| 1390 | #define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) |
| 1391 | #define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) |
| 1392 | #define pCNT_COUNTER ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */ |
| 1393 | #define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) |
| 1394 | #define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) |
| 1395 | #define pCNT_MAX ((uint32_t volatile *)CNT_MAX) /* Maximal Count Boundary Value Register */ |
| 1396 | #define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) |
| 1397 | #define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) |
| 1398 | #define pCNT_MIN ((uint32_t volatile *)CNT_MIN) /* Minimal Count Boundary Value Register */ |
| 1399 | #define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) |
| 1400 | #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) |
| 1401 | #define pOTP_CONTROL ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */ |
| 1402 | #define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) |
| 1403 | #define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) |
| 1404 | #define pOTP_BEN ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */ |
| 1405 | #define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) |
| 1406 | #define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) |
| 1407 | #define pOTP_STATUS ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */ |
| 1408 | #define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) |
| 1409 | #define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) |
| 1410 | #define pOTP_TIMING ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */ |
| 1411 | #define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) |
| 1412 | #define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) |
| 1413 | #define pSECURE_SYSSWT ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */ |
| 1414 | #define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) |
| 1415 | #define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) |
| 1416 | #define pSECURE_CONTROL ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */ |
| 1417 | #define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) |
| 1418 | #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) |
| 1419 | #define pSECURE_STATUS ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */ |
| 1420 | #define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) |
| 1421 | #define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) |
| 1422 | #define pOTP_DATA0 ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ |
| 1423 | #define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) |
| 1424 | #define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) |
| 1425 | #define pOTP_DATA1 ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ |
| 1426 | #define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) |
| 1427 | #define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) |
| 1428 | #define pOTP_DATA2 ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ |
| 1429 | #define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) |
| 1430 | #define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) |
| 1431 | #define pOTP_DATA3 ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ |
| 1432 | #define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) |
| 1433 | #define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) |
| 1434 | #define pNFC_CTL ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */ |
| 1435 | #define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) |
| 1436 | #define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) |
| 1437 | #define pNFC_STAT ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */ |
| 1438 | #define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) |
| 1439 | #define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) |
| 1440 | #define pNFC_IRQSTAT ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */ |
| 1441 | #define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) |
| 1442 | #define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) |
| 1443 | #define pNFC_IRQMASK ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */ |
| 1444 | #define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) |
| 1445 | #define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) |
| 1446 | #define pNFC_ECC0 ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */ |
| 1447 | #define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) |
| 1448 | #define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) |
| 1449 | #define pNFC_ECC1 ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */ |
| 1450 | #define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) |
| 1451 | #define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) |
| 1452 | #define pNFC_ECC2 ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */ |
| 1453 | #define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) |
| 1454 | #define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) |
| 1455 | #define pNFC_ECC3 ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */ |
| 1456 | #define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) |
| 1457 | #define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) |
| 1458 | #define pNFC_COUNT ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */ |
| 1459 | #define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) |
| 1460 | #define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) |
| 1461 | #define pNFC_RST ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */ |
| 1462 | #define bfin_read_NFC_RST() bfin_read16(NFC_RST) |
| 1463 | #define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) |
| 1464 | #define pNFC_PGCTL ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */ |
| 1465 | #define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) |
| 1466 | #define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) |
| 1467 | #define pNFC_READ ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */ |
| 1468 | #define bfin_read_NFC_READ() bfin_read16(NFC_READ) |
| 1469 | #define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) |
| 1470 | #define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */ |
| 1471 | #define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) |
| 1472 | #define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) |
| 1473 | #define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */ |
| 1474 | #define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) |
| 1475 | #define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) |
| 1476 | #define pNFC_DATA_WR ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */ |
| 1477 | #define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) |
| 1478 | #define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) |
| 1479 | #define pNFC_DATA_RD ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */ |
| 1480 | #define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) |
| 1481 | #define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) |
| 1482 | #define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ |
| 1483 | #define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) |
| 1484 | #define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) |
| 1485 | #define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */ |
| 1486 | #define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) |
| 1487 | #define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) |
| 1488 | #define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */ |
| 1489 | #define bfin_read_TBUF() bfin_readPTR(TBUF) |
| 1490 | #define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) |
| 1491 | #define pPFCTL ((uint32_t volatile *)PFCTL) |
| 1492 | #define bfin_read_PFCTL() bfin_read32(PFCTL) |
| 1493 | #define bfin_write_PFCTL(val) bfin_write32(PFCTL, val) |
| 1494 | #define pPFCNTR0 ((uint32_t volatile *)PFCNTR0) |
| 1495 | #define bfin_read_PFCNTR0() bfin_read32(PFCNTR0) |
| 1496 | #define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val) |
| 1497 | #define pPFCNTR1 ((uint32_t volatile *)PFCNTR1) |
| 1498 | #define bfin_read_PFCNTR1() bfin_read32(PFCNTR1) |
| 1499 | #define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val) |
| 1500 | #define pDMA_TC_CNT ((uint16_t volatile *)DMA_TC_CNT) |
| 1501 | #define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) |
| 1502 | #define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) |
| 1503 | #define pDMA_TC_PER ((uint16_t volatile *)DMA_TC_PER) |
| 1504 | #define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) |
| 1505 | #define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) |
| 1506 | |
| 1507 | #endif /* __BFIN_CDEF_ADSP_EDN_BF52x_extended__ */ |