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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2002
6 * Gregory E. Allen, gallen@arlut.utexas.edu
7 * Matthew E. Karger, karger@arlut.utexas.edu
8 * Applied Research Laboratories, The University of Texas at Austin
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/*
30 *
31 * Configuration settings for the utx8245 board.
32 *
33 */
34
35/* ------------------------------------------------------------------------- */
36
37/*
38 * board/config.h - configuration options, board specific
39 */
40
41#ifndef __CONFIG_H
42#define __CONFIG_H
43
44/*
45 * High Level Configuration Options
46 * (easy to change)
47 */
48
49#define CONFIG_MPC824X 1
50#define CONFIG_MPC8245 1
51#define CONFIG_UTX8245 1
52#define DEBUG 1
53
wdenk7a8e9bed2003-05-31 18:35:21 +000054#define CONFIG_IDENT_STRING " [UTX5] "
55
wdenkc6097192002-11-03 00:24:07 +000056#define CONFIG_CONS_INDEX 1
57#define CONFIG_BAUDRATE 57600
58#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
59
wdenk7a8e9bed2003-05-31 18:35:21 +000060#define CONFIG_BOOTDELAY 2
Wolfgang Denk53677ef2008-05-20 16:00:29 +020061#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
wdenk7a8e9bed2003-05-31 18:35:21 +000062#define CONFIG_BOOTCOMMAND "run nfsboot" /* autoboot command */
wdenkc6097192002-11-03 00:24:07 +000063#define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,57600" /* RAMdisk */
wdenk7a8e9bed2003-05-31 18:35:21 +000064#define CONFIG_ETHADDR 00:AA:00:14:00:05 /* UTX5 */
65#define CONFIG_SERVERIP 10.8.17.105 /* Spree */
66#define CFG_TFTP_LOADADDR 10000
67
68#define CONFIG_EXTRA_ENV_SETTINGS \
69 "kernel_addr=FFA00000\0" \
70 "ramdisk_addr=FF800000\0" \
71 "u-boot_startaddr=FFB00000\0" \
72 "u-boot_endaddr=FFB2FFFF\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010073 "nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \
74nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \
75 "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \
76 "smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \
77 "fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \
78 "nfsboot=run nfsargs;bootm ${kernel_addr}\0" \
79 "ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
80 "smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
81 "fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
82 "update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \
83${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \
84${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\
85protect on ${u-boot_startaddr} ${u-boot_endaddr}"
wdenk7a8e9bed2003-05-31 18:35:21 +000086
wdenkc6097192002-11-03 00:24:07 +000087#define CONFIG_ENV_OVERWRITE
88
wdenkc6097192002-11-03 00:24:07 +000089
Jon Loeliger6c18eb92007-07-04 22:33:38 -050090/*
Jon Loeliger079a1362007-07-10 10:12:10 -050091 * BOOTP options
92 */
93#define CONFIG_BOOTP_BOOTFILESIZE
94#define CONFIG_BOOTP_BOOTPATH
95#define CONFIG_BOOTP_GATEWAY
96#define CONFIG_BOOTP_HOSTNAME
97
98
99/*
Jon Loeliger6c18eb92007-07-04 22:33:38 -0500100 * Command line configuration.
wdenkc6097192002-11-03 00:24:07 +0000101 */
Jon Loeliger6c18eb92007-07-04 22:33:38 -0500102#include <config_cmd_default.h>
103
104#define CONFIG_CMD_BDI
105#define CONFIG_CMD_PCI
106#define CONFIG_CMD_FLASH
107#define CONFIG_CMD_MEMORY
108#define CONFIG_CMD_ENV
109#define CONFIG_CMD_CONSOLE
110#define CONFIG_CMD_LOADS
111#define CONFIG_CMD_LOADB
112#define CONFIG_CMD_IMI
113#define CONFIG_CMD_CACHE
114#define CONFIG_CMD_REGINFO
115#define CONFIG_CMD_NET
116#define CONFIG_CMD_DHCP
117#define CONFIG_CMD_I2C
118#define CONFIG_CMD_DATE
wdenkc6097192002-11-03 00:24:07 +0000119
120
121/*
122 * Miscellaneous configurable options
123 */
wdenk7a8e9bed2003-05-31 18:35:21 +0000124#define CFG_LONGHELP /* undef to save memory */
125#define CFG_PROMPT "=> " /* Monitor Command Prompt */
126#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000127
128/* Print Buffer Size */
129#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
130
131#define CFG_MAXARGS 16 /* max number of command args */
132#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
133#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
134
135
136/*-----------------------------------------------------------------------
137 * PCI configuration
138 *-----------------------------------------------------------------------
139 */
140#define CONFIG_PCI /* include pci support */
141#undef CONFIG_PCI_PNP
142#define CONFIG_PCI_SCAN_SHOW
143#define CONFIG_NET_MULTI
144#define CONFIG_EEPRO100
stroese53cf9432003-06-05 15:39:44 +0000145#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenk7a8e9bed2003-05-31 18:35:21 +0000146#define CONFIG_EEPRO100_SROM_WRITE
wdenkc6097192002-11-03 00:24:07 +0000147
wdenk7a8e9bed2003-05-31 18:35:21 +0000148#define PCI_ENET0_IOADDR 0xF0000000
149#define PCI_ENET0_MEMADDR 0xF0000000
150
151#define PCI_FIREWIRE_IOADDR 0xF1000000
152#define PCI_FIREWIRE_MEMADDR 0xF1000000
153/*
154#define PCI_ENET0_IOADDR 0xFE000000
wdenkc6097192002-11-03 00:24:07 +0000155#define PCI_ENET0_MEMADDR 0x80000000
wdenk7a8e9bed2003-05-31 18:35:21 +0000156
wdenkc6097192002-11-03 00:24:07 +0000157#define PCI_FIREWIRE_IOADDR 0x81000000
158#define PCI_FIREWIRE_MEMADDR 0x81000000
wdenk7a8e9bed2003-05-31 18:35:21 +0000159*/
wdenkc6097192002-11-03 00:24:07 +0000160
161/*-----------------------------------------------------------------------
162 * Start addresses for the final memory configuration
163 * (Set up by the startup code)
164 * Please note that CFG_SDRAM_BASE _must_ start at 0
165 */
166#define CFG_SDRAM_BASE 0x00000000
wdenk7a8e9bed2003-05-31 18:35:21 +0000167#define CFG_MAX_RAM_SIZE 0x10000000 /* 256MB */
168/*#define CFG_VERY_BIG_RAM 1 */
wdenkc6097192002-11-03 00:24:07 +0000169
wdenk7a8e9bed2003-05-31 18:35:21 +0000170/* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector
171 * is actually located at FFF00100. Therefore, U-Boot is
172 * physically located at 0xFFB0_0000, but is also mirrored at
173 * 0xFFF0_0000.
wdenkc6097192002-11-03 00:24:07 +0000174 */
175#define CFG_RESET_ADDRESS 0xFFF00100
176
177#define CFG_EUMB_ADDR 0xFC000000
178
179#define CFG_MONITOR_BASE TEXT_BASE
180
181#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
182#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
183
184/*#define CFG_DRAM_TEST 1 */
185#define CFG_MEMTEST_START 0x00003000 /* memtest works on 0...256 MB */
wdenk7a8e9bed2003-05-31 18:35:21 +0000186#define CFG_MEMTEST_END 0x0ff8ffa7 /* in SDRAM, skips exception */
wdenkc6097192002-11-03 00:24:07 +0000187 /* vectors and U-Boot */
188
189
190/*--------------------------------------------------------------------
191 * Definitions for initial stack pointer and data area
192 *------------------------------------------------------------------*/
wdenk7a8e9bed2003-05-31 18:35:21 +0000193#define CFG_INIT_DATA_SIZE 128 /* Size in bytes reserved for */
wdenkc6097192002-11-03 00:24:07 +0000194 /* initial data */
195#define CFG_INIT_RAM_ADDR 0x40000000
196#define CFG_INIT_RAM_END 0x1000
wdenk7a8e9bed2003-05-31 18:35:21 +0000197#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
198#define CFG_GBL_DATA_SIZE 128
wdenkc6097192002-11-03 00:24:07 +0000199#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
200
201/*--------------------------------------------------------------------
202 * NS16550 Configuration
203 *------------------------------------------------------------------*/
204#define CFG_NS16550
205#define CFG_NS16550_SERIAL
206
207#define CFG_NS16550_REG_SIZE 1
208
wdenk7a8e9bed2003-05-31 18:35:21 +0000209#if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2)
210# define CFG_NS16550_CLK get_bus_freq(0)
211#else
212# define CFG_NS16550_CLK 33000000
213#endif
wdenkc6097192002-11-03 00:24:07 +0000214
215#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500)
216#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600)
wdenk7a8e9bed2003-05-31 18:35:21 +0000217#define CFG_NS16550_COM3 0xFF000000
218#define CFG_NS16550_COM4 0xFF000008
wdenkc6097192002-11-03 00:24:07 +0000219
220/*--------------------------------------------------------------------
221 * Low Level Configuration Settings
222 * (address mappings, register initial values, etc.)
223 * You should know what you are doing if you make changes here.
224 * For the detail description refer to the MPC8240 user's manual.
225 *------------------------------------------------------------------*/
226
227#define CONFIG_SYS_CLK_FREQ 33000000
228#define CFG_HZ 1000
229
wdenk7a8e9bed2003-05-31 18:35:21 +0000230/*#define CFG_ETH_DEV_FN 0x7800 */
231/*#define CFG_ETH_IOBASE 0x00104000 */
wdenkc6097192002-11-03 00:24:07 +0000232
wdenk7a8e9bed2003-05-31 18:35:21 +0000233/*--------------------------------------------------------------------
234 * I2C Configuration
235 *------------------------------------------------------------------*/
236#if 1
237#define CONFIG_HARD_I2C 1 /* To enable I2C support */
238#undef CONFIG_SOFT_I2C /* I2C bit-banged */
239#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
240#define CFG_I2C_SLAVE 0x7F
241#endif
242
243#define CONFIG_RTC_PCF8563 1 /* enable I2C support for */
244 /* Philips PCF8563 RTC */
245#define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
wdenkc6097192002-11-03 00:24:07 +0000246
247/*--------------------------------------------------------------------
248 * Memory Control Configuration Register values
249 * - see sec. 4.12 of MPC8245 UM
250 *------------------------------------------------------------------*/
251
wdenk7a8e9bed2003-05-31 18:35:21 +0000252/**** MCCR1 ****/
wdenkc6097192002-11-03 00:24:07 +0000253#define CFG_ROMNAL 0
wdenk7a8e9bed2003-05-31 18:35:21 +0000254#define CFG_ROMFAL 10 /* (tacc=70ns)*mem_freq - 2,
255 mem_freq = 100MHz */
wdenkc6097192002-11-03 00:24:07 +0000256
wdenk7a8e9bed2003-05-31 18:35:21 +0000257#define CFG_BANK7_ROW 0 /* SDRAM bank 7-0 row address */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200258#define CFG_BANK6_ROW 0 /* bit count */
wdenk7a8e9bed2003-05-31 18:35:21 +0000259#define CFG_BANK5_ROW 0
260#define CFG_BANK4_ROW 0
261#define CFG_BANK3_ROW 0
262#define CFG_BANK2_ROW 0
263#define CFG_BANK1_ROW 2
264#define CFG_BANK0_ROW 2
265
266/**** MCCR2, refresh interval clock cycles ****/
wdenkc6097192002-11-03 00:24:07 +0000267#define CFG_REFINT 480 /* 33 MHz SDRAM clock was 480 */
268
wdenk7a8e9bed2003-05-31 18:35:21 +0000269/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
wdenkc6097192002-11-03 00:24:07 +0000270#define CFG_BSTOPRE 1023 /* burst to precharge[0..9], */
271 /* sets open page interval */
272
wdenk7a8e9bed2003-05-31 18:35:21 +0000273/**** MCCR3 ****/
274#define CFG_REFREC 7 /* Refresh to activate interval, trc */
wdenkc6097192002-11-03 00:24:07 +0000275
wdenk7a8e9bed2003-05-31 18:35:21 +0000276/**** MCCR4 ****/
wdenkc6097192002-11-03 00:24:07 +0000277#define CFG_PRETOACT 2 /* trp */
wdenk7a8e9bed2003-05-31 18:35:21 +0000278#define CFG_ACTTOPRE 7 /* trcd + (burst length - 1) + trdl */
wdenkc6097192002-11-03 00:24:07 +0000279#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
280#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type, sequential */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200281#define CFG_ACTORW 2 /* trcd min */
wdenkc6097192002-11-03 00:24:07 +0000282#define CFG_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */
283#define CFG_REGISTERD_TYPE_BUFFER 1
wdenk7a8e9bed2003-05-31 18:35:21 +0000284#define CFG_EXTROM 0 /* we don't need extended ROM space */
wdenkc6097192002-11-03 00:24:07 +0000285#define CFG_REGDIMM 0
286
287/* calculate according to formula in sec. 6-22 of 8245 UM */
288#define CFG_PGMAX 50 /* how long the 8245 retains the */
289 /* currently accessed page in memory */
290 /* was 45 */
291
292#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note */
wdenk7a8e9bed2003-05-31 18:35:21 +0000293 /* bits 7,6, and 3-0 MUST be 0 */
wdenkc6097192002-11-03 00:24:07 +0000294
wdenk7a8e9bed2003-05-31 18:35:21 +0000295#if 0
wdenkc6097192002-11-03 00:24:07 +0000296#define CFG_DLL_MAX_DELAY 0x04
wdenk7a8e9bed2003-05-31 18:35:21 +0000297#else
298#define CFG_DLL_MAX_DELAY 0
299#endif
300#if 0 /* need for 33MHz SDRAM */
wdenkc6097192002-11-03 00:24:07 +0000301#define CFG_DLL_EXTEND 0x80
wdenk7a8e9bed2003-05-31 18:35:21 +0000302#else
303#define CFG_DLL_EXTEND 0
304#endif
wdenkc6097192002-11-03 00:24:07 +0000305#define CFG_PCI_HOLD_DEL 0x20
306
307
308/* Memory bank settings.
309 * Only bits 20-29 are actually used from these values to set the
310 * start/end addresses. The upper two bits will always be 0, and the lower
311 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
312 * address. Refer to the MPC8245 user manual.
313 */
314
315#define CFG_BANK0_START 0x00000000
316#define CFG_BANK0_END (CFG_MAX_RAM_SIZE/2 - 1)
317#define CFG_BANK0_ENABLE 1
318#define CFG_BANK1_START CFG_MAX_RAM_SIZE/2
319#define CFG_BANK1_END (CFG_MAX_RAM_SIZE - 1)
320#define CFG_BANK1_ENABLE 1
321#define CFG_BANK2_START 0x3ff00000 /* not available in this design */
322#define CFG_BANK2_END 0x3fffffff
323#define CFG_BANK2_ENABLE 0
324#define CFG_BANK3_START 0x3ff00000
325#define CFG_BANK3_END 0x3fffffff
326#define CFG_BANK3_ENABLE 0
327#define CFG_BANK4_START 0x3ff00000
328#define CFG_BANK4_END 0x3fffffff
329#define CFG_BANK4_ENABLE 0
330#define CFG_BANK5_START 0x3ff00000
331#define CFG_BANK5_END 0x3fffffff
332#define CFG_BANK5_ENABLE 0
333#define CFG_BANK6_START 0x3ff00000
334#define CFG_BANK6_END 0x3fffffff
335#define CFG_BANK6_ENABLE 0
336#define CFG_BANK7_START 0x3ff00000
337#define CFG_BANK7_END 0x3fffffff
338#define CFG_BANK7_ENABLE 0
339
wdenk7a8e9bed2003-05-31 18:35:21 +0000340/*--------------------------------------------------------------------*/
341/* 4.4 - Output Driver Control Register */
342/*--------------------------------------------------------------------*/
wdenkc6097192002-11-03 00:24:07 +0000343#define CFG_ODCR 0xe5
344
wdenk7a8e9bed2003-05-31 18:35:21 +0000345/*--------------------------------------------------------------------*/
346/* 4.8 - Error Handling Registers */
347/*-------------------------------CFG_SDMODE_BURSTLEN-------------------------------------*/
wdenkc6097192002-11-03 00:24:07 +0000348#define CFG_ERRENR1 0x11 /* enable SDRAM refresh overflow error */
349
350/* SDRAM 0-256 MB */
351#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
wdenk7a8e9bed2003-05-31 18:35:21 +0000352/*#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */
wdenkc6097192002-11-03 00:24:07 +0000353#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
354
355/* stack in dcache */
356#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
357#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
358
wdenkc6097192002-11-03 00:24:07 +0000359
wdenk7a8e9bed2003-05-31 18:35:21 +0000360#define CFG_IBAT2L (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
361#define CFG_IBAT2U (CFG_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP)
362
363/* PCI memory */
364/*#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */
365/*#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */
366
367/*Flash, config addrs, etc. */
wdenkc6097192002-11-03 00:24:07 +0000368#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
369#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
370
371#define CFG_DBAT0L CFG_IBAT0L
372#define CFG_DBAT0U CFG_IBAT0U
373#define CFG_DBAT1L CFG_IBAT1L
374#define CFG_DBAT1U CFG_IBAT1U
375#define CFG_DBAT2L CFG_IBAT2L
376#define CFG_DBAT2U CFG_IBAT2U
377#define CFG_DBAT3L CFG_IBAT3L
378#define CFG_DBAT3U CFG_IBAT3U
379
380/*
381 * For booting Linux, the board info and command line data
382 * have to be in the first 8 MB of memory, since this is
383 * the maximum mapped by the Linux kernel during initialization.
384 */
385#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
386
387/*-----------------------------------------------------------------------
wdenk7a8e9bed2003-05-31 18:35:21 +0000388 * FLASH organization
389 *----------------------------------------------------------------------*/
wdenkc6097192002-11-03 00:24:07 +0000390#define CFG_FLASH_BASE 0xFF800000
wdenk7a8e9bed2003-05-31 18:35:21 +0000391#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
wdenkc6097192002-11-03 00:24:07 +0000392
wdenk7a8e9bed2003-05-31 18:35:21 +0000393/* NOTE: environment is not EMBEDDED in the u-boot code.
394 It's stored in flash in its own separate sector. */
395#define CFG_ENV_IS_IN_FLASH 1
396
397#if 1 /* AMD AM29LV033C */
398#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */
399#define CFG_ENV_ADDR 0xFFBF0000 /* flash sector SA63 */
400#define CFG_ENV_SECT_SIZE (64*1024) /* Size of the Environment Sector */
401#else /* AMD AM29LV116D */
wdenkc6097192002-11-03 00:24:07 +0000402#define CFG_MAX_FLASH_SECT 35 /* Max number of sectors in one bank */
wdenk7a8e9bed2003-05-31 18:35:21 +0000403#define CFG_ENV_ADDR 0xFF9FA000 /* flash sector SA33 */
404#define CFG_ENV_SECT_SIZE (8*1024) /* Size of the Environment Sector */
405#endif /* #if */
406
407#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* Size of the Environment */
408#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
wdenkc6097192002-11-03 00:24:07 +0000409
410#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
411#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
412
wdenkc6097192002-11-03 00:24:07 +0000413#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
414#undef CFG_RAMBOOT
415#else
416#define CFG_RAMBOOT
417#endif
418
419
420/*-----------------------------------------------------------------------
421 * Cache Configuration
422 */
423#define CFG_CACHELINE_SIZE 32
Jon Loeliger6c18eb92007-07-04 22:33:38 -0500424#if defined(CONFIG_CMD_KGDB)
wdenkc6097192002-11-03 00:24:07 +0000425# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
426#endif
427
428/*
429 * Internal Definitions
430 *
431 * Boot Flags
432 */
433#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
434#define BOOTFLAG_WARM 0x02 /* Software reboot */
435
436
437#endif /* __CONFIG_H */