blob: c065d3328c97be28156e6d2e38ef6e9114a03cde [file] [log] [blame]
Stefan Roese5e4b3362005-08-22 17:51:53 +02001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*************************************************************************
25 * (c) 2005 esd gmbh Hannover
26 *
27 *
28 * from IceCube.h file
29 * by Reinhard Arlt reinhard.arlt@esd-electronics.com
30 *
31 *************************************************************************/
32
33#ifndef __CONFIG_H
34#define __CONFIG_H
35
36/*
37 * High Level Configuration Options
38 * (easy to change)
39 */
40
41#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */
42#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
43#define CONFIG_ICECUBE 1 /* ... on IceCube board */
44#define CONFIG_PF5200 1 /* ... on PF5200 board */
45#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
46
47#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
48
49#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
50#define BOOTFLAG_WARM 0x02 /* Software reboot */
51
Becky Bruce31d82672008-05-08 19:02:12 -050052#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Stefan Roese5e4b3362005-08-22 17:51:53 +020053/*
54 * Serial console configuration
55 */
56#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
57#if 0 /* test-only */
58#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
59#else
60#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
61#endif
62#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
63
64#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
65/*
66 * PCI Mapping:
67 * 0x40000000 - 0x4fffffff - PCI Memory
68 * 0x50000000 - 0x50ffffff - PCI IO Space
69 */
70#define CONFIG_PCI 1
71#define CONFIG_PCI_PNP 1
72#define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liewf33fca22008-03-30 01:19:06 -050073#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
Stefan Roese5e4b3362005-08-22 17:51:53 +020074
75#define CONFIG_PCI_MEM_BUS 0x40000000
76#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
77#define CONFIG_PCI_MEM_SIZE 0x10000000
78
79#define CONFIG_PCI_IO_BUS 0x50000000
80#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
81#define CONFIG_PCI_IO_SIZE 0x01000000
82
Marian Balakowicz63ff0042005-10-28 22:30:33 +020083#define CONFIG_MII 1
Stefan Roese5e4b3362005-08-22 17:51:53 +020084#if 0 /* test-only !!! */
85#define CONFIG_NET_MULTI 1
86#define CONFIG_EEPRO100 1
87#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
88#define CONFIG_NS8382X 1
89#endif
Stefan Roese5e4b3362005-08-22 17:51:53 +020090#endif
91
92/* Partitions */
93#define CONFIG_MAC_PARTITION
94#define CONFIG_DOS_PARTITION
95
96/* USB */
97#if 0
98#define CONFIG_USB_OHCI
Stefan Roese5e4b3362005-08-22 17:51:53 +020099#define CONFIG_USB_STORAGE
Stefan Roese5e4b3362005-08-22 17:51:53 +0200100#endif
101
Stefan Roese5e4b3362005-08-22 17:51:53 +0200102
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500103/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500104 * BOOTP options
105 */
106#define CONFIG_BOOTP_BOOTFILESIZE
107#define CONFIG_BOOTP_BOOTPATH
108#define CONFIG_BOOTP_GATEWAY
109#define CONFIG_BOOTP_HOSTNAME
110
111
112/*
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500113 * Command line configuration.
114 */
115#include <config_cmd_default.h>
116
117#define CONFIG_CMD_BSP
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500118#define CONFIG_CMD_EEPROM
119#define CONFIG_CMD_ELF
120#define CONFIG_CMD_FAT
121#define CONFIG_CMD_I2C
122#define CONFIG_CMD_IDE
123
Jon Loeliger079a1362007-07-10 10:12:10 -0500124#ifdef CONFIG_MPC5200
125#define CONFIG_CMD_PCI
126#endif
127
Stefan Roese5e4b3362005-08-22 17:51:53 +0200128
129#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
130# define CFG_LOWBOOT 1
131# define CFG_LOWBOOT16 1
132#endif
133#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
134# define CFG_LOWBOOT 1
135# define CFG_LOWBOOT08 1
136#endif
137
138/*
139 * Autobooting
140 */
141#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
142
143#define CONFIG_PREBOOT "echo;" \
144 "echo Welcome to ParaFinder pf5200;" \
145 "echo"
146
147#undef CONFIG_BOOTARGS
148
149#define CONFIG_EXTRA_ENV_SETTINGS \
150 "netdev=eth0\0" \
151 "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
152 "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100153 "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
154 "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
155 "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
Stefan Roese5e4b3362005-08-22 17:51:53 +0200156 "loadaddr=01000000\0" \
157 "serverip=192.168.2.99\0" \
158 "gatewayip=10.0.0.79\0" \
159 "user=mu\0" \
160 "target=pf5200.esd\0" \
161 "script=pf5200.bat\0" \
162 "image=/tftpboot/vxWorks_pf5200\0" \
163 "ipaddr=10.0.13.196\0" \
164 "netmask=255.255.0.0\0" \
165 ""
166
167#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
168
169#if defined(CONFIG_MPC5200)
170/*
171 * IPB Bus clocking configuration.
172 */
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200173#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200174#endif
175/*
176 * I2C configuration
177 */
178#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
179#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
180
181#define CFG_I2C_SPEED 86000 /* 100 kHz */
182#define CFG_I2C_SLAVE 0x7F
183
184/*
185 * EEPROM configuration
186 */
187#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
188#define CFG_I2C_EEPROM_ADDR_LEN 2
189#define CFG_EEPROM_PAGE_WRITE_BITS 5
190#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
191#define CFG_I2C_MULTI_EEPROMS 1
192/*
193 * Flash configuration
194 */
195#define CFG_FLASH_BASE 0xFE000000
196#define CFG_FLASH_SIZE 0x02000000
197#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000)
198#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
199#define CFG_MAX_FLASH_SECT 512
200
201#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
202#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
203
204/*
205 * Environment settings
206 */
207#if 1 /* test-only */
208#define CFG_ENV_IS_IN_FLASH 0
209#define CFG_ENV_SIZE 0x10000
210#define CFG_ENV_SECT_SIZE 0x10000
211#define CONFIG_ENV_OVERWRITE 1
212#else
213#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
214#define CFG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
215#define CFG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */
216 /* total size of a CAT24WC32 is 8192 bytes */
217#define CONFIG_ENV_OVERWRITE 1
218#endif
219
220/*
221 * Memory map
222 */
223#define CFG_MBAR 0xF0000000
224#define CFG_SDRAM_BASE 0x00000000
225#define CFG_DEFAULT_MBAR 0x80000000
226
227/* Use SRAM until RAM will be available */
228#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
229#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
230
231#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
232#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
233#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
234
235#define CFG_MONITOR_BASE TEXT_BASE
236#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
237# define CFG_RAMBOOT 1
238#endif
239
240#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
241#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
242#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
243
244/*
245 * Ethernet configuration
246 */
247#define CONFIG_MPC5xxx_FEC 1
248/*
249 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
250 */
251/* #define CONFIG_FEC_10MBIT 1 */
252#define CONFIG_PHY_ADDR 0x00
253#define CONFIG_UDP_CHECKSUM 1
254
255/*
256 * GPIO configuration
257 */
258#define CFG_GPS_PORT_CONFIG 0x01052444
259
260/*
261 * Miscellaneous configurable options
262 */
263#define CFG_LONGHELP /* undef to save memory */
264#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500265#if defined(CONFIG_CMD_KGDB)
Stefan Roese5e4b3362005-08-22 17:51:53 +0200266#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
267#else
268#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
269#endif
270#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
271#define CFG_MAXARGS 16 /* max number of command args */
272#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
273
274#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
275#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
276
277#define CFG_LOAD_ADDR 0x100000 /* default load address */
278
279#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
280
281#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
282
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500283#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
284#if defined(CONFIG_CMD_KGDB)
285# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
286#endif
287
Stefan Roese5e4b3362005-08-22 17:51:53 +0200288/*
289 * Various low-level settings
290 */
291#if defined(CONFIG_MPC5200)
292#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
293#define CFG_HID0_FINAL HID0_ICE
294#else
295#define CFG_HID0_INIT 0
296#define CFG_HID0_FINAL 0
297#endif
298
299#define CFG_BOOTCS_START CFG_FLASH_BASE
300#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
301#define CFG_BOOTCS_CFG 0x0004DD00
302
303#define CFG_CS0_START CFG_FLASH_BASE
304#define CFG_CS0_SIZE CFG_FLASH_SIZE
305
306#define CFG_CS1_START 0xfd000000
307#define CFG_CS1_SIZE 0x00010000
308#define CFG_CS1_CFG 0x10101410
309
310#define CFG_CS_BURST 0x00000000
311#define CFG_CS_DEADCYCLE 0x33333333
312
313#define CFG_RESET_ADDRESS 0xff000000
314
315/*-----------------------------------------------------------------------
316 * USB stuff
317 *-----------------------------------------------------------------------
318 */
319#define CONFIG_USB_CLOCK 0x0001BBBB
320#define CONFIG_USB_CONFIG 0x00001000
321
322/*-----------------------------------------------------------------------
323 * IDE/ATA stuff Supports IDE harddisk
324 *-----------------------------------------------------------------------
325 */
326
327#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
328
329#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
330#undef CONFIG_IDE_LED /* LED for ide not supported */
331
332#define CONFIG_IDE_RESET /* reset for ide supported */
333#define CONFIG_IDE_PREINIT
334
335#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
336#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
337
338#define CFG_ATA_IDE0_OFFSET 0x0000
339
340#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
341
342/* Offset for data I/O */
343#define CFG_ATA_DATA_OFFSET (0x0060)
344
345/* Offset for normal register accesses */
346#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
347
348/* Offset for alternate registers */
349#define CFG_ATA_ALT_OFFSET (0x005C)
350
351/* Interval between registers */
352#define CFG_ATA_STRIDE 4
353
354/*-----------------------------------------------------------------------
355 * CPLD stuff
356 */
357#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
358#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
359
360/* CPLD program pin configuration */
361#define CFG_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */
362#define CFG_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */
363#define CFG_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */
364#define CFG_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */
365
366#define JTAG_GPIO_ADDR_TMS (CFG_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */
367#define JTAG_GPIO_ADDR_TCK (CFG_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */
368#define JTAG_GPIO_ADDR_TDI (CFG_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */
369#define JTAG_GPIO_ADDR_TDO (CFG_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */
370
371#define JTAG_GPIO_ADDR_CFG (CFG_MBAR + 0xB00)
372#define JTAG_GPIO_CFG_SET 0x00000000
373#define JTAG_GPIO_CFG_RESET 0x00F00000
374
375#define JTAG_GPIO_ADDR_EN_TMS (CFG_MBAR + 0xB04)
376#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */
377#define JTAG_GPIO_TMS_EN_RESET 0x00000000
378#define JTAG_GPIO_ADDR_DDR_TMS (CFG_MBAR + 0xB0C)
379#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */
380#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
381
382#define JTAG_GPIO_ADDR_EN_TCK (CFG_MBAR + 0xC00)
383#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */
384#define JTAG_GPIO_TCK_EN_RESET 0x00000000
385#define JTAG_GPIO_ADDR_DDR_TCK (CFG_MBAR + 0xC08)
386#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */
387#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
388
389#define JTAG_GPIO_ADDR_EN_TDI (CFG_MBAR + 0xC00)
390#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */
391#define JTAG_GPIO_TDI_EN_RESET 0x00000000
392#define JTAG_GPIO_ADDR_DDR_TDI (CFG_MBAR + 0xC08)
393#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */
394#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
395
396#define JTAG_GPIO_ADDR_EN_TDO (CFG_MBAR + 0xB04)
397#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */
398#define JTAG_GPIO_TDO_EN_RESET 0x00000000
399#define JTAG_GPIO_ADDR_DDR_TDO (CFG_MBAR + 0xB0C)
400#define JTAG_GPIO_TDO_DDR_SET 0x00000000
401#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */
402
403#endif /* __CONFIG_H */