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Kumar Gala58e5e9a2008-08-26 15:01:29 -05001/*
York Suna4c66502012-08-17 08:22:39 +00002 * Copyright 2008-2012 Freescale Semiconductor, Inc.
Kumar Gala58e5e9a2008-08-26 15:01:29 -05003 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9#include <common.h>
10#include <asm/fsl_law.h>
Kyle Moffette820a132011-03-15 11:23:47 -040011#include <div64.h>
Kumar Gala58e5e9a2008-08-26 15:01:29 -050012
York Sun5614e712013-09-30 09:22:09 -070013#include <fsl_ddr.h>
14#include <asm/io.h>
Kumar Gala58e5e9a2008-08-26 15:01:29 -050015
Kyle Moffette820a132011-03-15 11:23:47 -040016/* To avoid 64-bit full-divides, we factor this here */
Kyle Moffetta2879632011-04-14 13:39:30 -040017#define ULL_2E12 2000000000000ULL
18#define UL_5POW12 244140625UL
19#define UL_2POW13 (1UL << 13)
Kyle Moffette820a132011-03-15 11:23:47 -040020
Kyle Moffetta2879632011-04-14 13:39:30 -040021#define ULL_8FS 0xFFFFFFFFULL
Kyle Moffette820a132011-03-15 11:23:47 -040022
Kumar Gala58e5e9a2008-08-26 15:01:29 -050023/*
York Sun905acde2011-08-26 11:32:42 -070024 * Round up mclk_ps to nearest 1 ps in memory controller code
25 * if the error is 0.5ps or more.
Kumar Gala58e5e9a2008-08-26 15:01:29 -050026 *
27 * If an imprecise data rate is too high due to rounding error
28 * propagation, compute a suitably rounded mclk_ps to compute
29 * a working memory controller configuration.
30 */
31unsigned int get_memory_clk_period_ps(void)
32{
Kyle Moffette820a132011-03-15 11:23:47 -040033 unsigned int data_rate = get_ddr_freq(0);
34 unsigned int result;
Kumar Gala58e5e9a2008-08-26 15:01:29 -050035
Kyle Moffette820a132011-03-15 11:23:47 -040036 /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
York Sun905acde2011-08-26 11:32:42 -070037 unsigned long long rem, mclk_ps = ULL_2E12;
Kyle Moffette820a132011-03-15 11:23:47 -040038
39 /* Now perform the big divide, the result fits in 32-bits */
York Sun905acde2011-08-26 11:32:42 -070040 rem = do_div(mclk_ps, data_rate);
41 result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
Kyle Moffette820a132011-03-15 11:23:47 -040042
York Sun905acde2011-08-26 11:32:42 -070043 return result;
Kumar Gala58e5e9a2008-08-26 15:01:29 -050044}
45
46/* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
47unsigned int picos_to_mclk(unsigned int picos)
48{
Kyle Moffette820a132011-03-15 11:23:47 -040049 unsigned long long clks, clks_rem;
York Sun905acde2011-08-26 11:32:42 -070050 unsigned long data_rate = get_ddr_freq(0);
Kumar Gala58e5e9a2008-08-26 15:01:29 -050051
Kyle Moffette820a132011-03-15 11:23:47 -040052 /* Short circuit for zero picos */
Kumar Gala58e5e9a2008-08-26 15:01:29 -050053 if (!picos)
54 return 0;
55
Kyle Moffette820a132011-03-15 11:23:47 -040056 /* First multiply the time by the data rate (32x32 => 64) */
York Sun905acde2011-08-26 11:32:42 -070057 clks = picos * (unsigned long long)data_rate;
Kyle Moffette820a132011-03-15 11:23:47 -040058 /*
59 * Now divide by 5^12 and track the 32-bit remainder, then divide
60 * by 2*(2^12) using shifts (and updating the remainder).
61 */
Kyle Moffetta2879632011-04-14 13:39:30 -040062 clks_rem = do_div(clks, UL_5POW12);
York Sun905acde2011-08-26 11:32:42 -070063 clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12;
Kyle Moffette820a132011-03-15 11:23:47 -040064 clks >>= 13;
65
York Sun905acde2011-08-26 11:32:42 -070066 /* If we had a remainder greater than the 1ps error, then round up */
67 if (clks_rem > data_rate)
Kumar Gala58e5e9a2008-08-26 15:01:29 -050068 clks++;
Kumar Gala58e5e9a2008-08-26 15:01:29 -050069
Kyle Moffette820a132011-03-15 11:23:47 -040070 /* Clamp to the maximum representable value */
Kyle Moffetta2879632011-04-14 13:39:30 -040071 if (clks > ULL_8FS)
72 clks = ULL_8FS;
Kumar Gala58e5e9a2008-08-26 15:01:29 -050073 return (unsigned int) clks;
74}
75
76unsigned int mclk_to_picos(unsigned int mclk)
77{
78 return get_memory_clk_period_ps() * mclk;
79}
80
81void
82__fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
York Suna4c66502012-08-17 08:22:39 +000083 unsigned int law_memctl,
Kumar Gala58e5e9a2008-08-26 15:01:29 -050084 unsigned int ctrl_num)
85{
Kumar Galae7563af2009-06-11 23:42:35 -050086 unsigned long long base = memctl_common_params->base_address;
87 unsigned long long size = memctl_common_params->total_mem;
88
Kumar Gala58e5e9a2008-08-26 15:01:29 -050089 /*
90 * If no DIMMs on this controller, do not proceed any further.
91 */
92 if (!memctl_common_params->ndimms_present) {
93 return;
94 }
95
Kumar Galae7563af2009-06-11 23:42:35 -050096#if !defined(CONFIG_PHYS_64BIT)
97 if (base >= CONFIG_MAX_MEM_MAPPED)
98 return;
99 if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
100 size = CONFIG_MAX_MEM_MAPPED - base;
101#endif
York Suna4c66502012-08-17 08:22:39 +0000102 if (set_ddr_laws(base, size, law_memctl) < 0) {
103 printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num,
104 law_memctl);
105 return ;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500106 }
York Suna4c66502012-08-17 08:22:39 +0000107 debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n",
108 base, size, law_memctl);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500109}
110
111__attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
112fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
113 unsigned int memctl_interleaved,
114 unsigned int ctrl_num);
Peter Tyserd9c147f2009-07-17 10:14:48 -0500115
York Suna4c66502012-08-17 08:22:39 +0000116void fsl_ddr_set_intl3r(const unsigned int granule_size)
117{
118#ifdef CONFIG_E6500
119 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
120 *mcintl3r = 0x80000000 | (granule_size & 0x1f);
121 debug("Enable MCINTL3R with granule size 0x%x\n", granule_size);
122#endif
123}
124
York Suneb539412012-10-08 07:44:25 +0000125u32 fsl_ddr_get_intl3r(void)
126{
127 u32 val = 0;
128#ifdef CONFIG_E6500
129 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
130 val = *mcintl3r;
131#endif
132 return val;
133}
134
Peter Tyserd9c147f2009-07-17 10:14:48 -0500135void board_add_ram_info(int use_default)
136{
York Sun5614e712013-09-30 09:22:09 -0700137 ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
Andy Fleminge76cd5d2012-10-23 19:03:46 -0500138
York Suna4c66502012-08-17 08:22:39 +0000139#if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
140 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
141#endif
Peter Tyserd9c147f2009-07-17 10:14:48 -0500142#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
143 uint32_t cs0_config = in_be32(&ddr->cs0_config);
144#endif
145 uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg);
146 int cas_lat;
147
York Sun123922b2012-10-08 07:44:23 +0000148#if CONFIG_NUM_DDR_CONTROLLERS >= 2
149 if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
York Sun5614e712013-09-30 09:22:09 -0700150 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
York Sun123922b2012-10-08 07:44:23 +0000151 sdram_cfg = in_be32(&ddr->sdram_cfg);
152 }
153#endif
154#if CONFIG_NUM_DDR_CONTROLLERS >= 3
155 if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
York Sun5614e712013-09-30 09:22:09 -0700156 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
York Sun123922b2012-10-08 07:44:23 +0000157 sdram_cfg = in_be32(&ddr->sdram_cfg);
158 }
159#endif
Peter Tyserd9c147f2009-07-17 10:14:48 -0500160 puts(" (DDR");
161 switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
162 SDRAM_CFG_SDRAM_TYPE_SHIFT) {
163 case SDRAM_TYPE_DDR1:
164 puts("1");
165 break;
166 case SDRAM_TYPE_DDR2:
167 puts("2");
168 break;
169 case SDRAM_TYPE_DDR3:
170 puts("3");
171 break;
172 default:
173 puts("?");
174 break;
175 }
176
177 if (sdram_cfg & SDRAM_CFG_32_BE)
178 puts(", 32-bit");
Poonam Aggrwal0b3b1762011-02-07 15:09:51 +0530179 else if (sdram_cfg & SDRAM_CFG_16_BE)
180 puts(", 16-bit");
Peter Tyserd9c147f2009-07-17 10:14:48 -0500181 else
182 puts(", 64-bit");
183
184 /* Calculate CAS latency based on timing cfg values */
185 cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
186 if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1)
187 cas_lat += (8 << 1);
188 printf(", CL=%d", cas_lat >> 1);
189 if (cas_lat & 0x1)
190 puts(".5");
191
192 if (sdram_cfg & SDRAM_CFG_ECC_EN)
193 puts(", ECC on)");
194 else
195 puts(", ECC off)");
196
York Suna4c66502012-08-17 08:22:39 +0000197#if (CONFIG_NUM_DDR_CONTROLLERS == 3)
198#ifdef CONFIG_E6500
199 if (*mcintl3r & 0x80000000) {
200 puts("\n");
201 puts(" DDR Controller Interleaving Mode: ");
202 switch (*mcintl3r & 0x1f) {
203 case FSL_DDR_3WAY_1KB_INTERLEAVING:
204 puts("3-way 1KB");
205 break;
206 case FSL_DDR_3WAY_4KB_INTERLEAVING:
207 puts("3-way 4KB");
208 break;
209 case FSL_DDR_3WAY_8KB_INTERLEAVING:
210 puts("3-way 8KB");
211 break;
212 default:
213 puts("3-way UNKNOWN");
214 break;
215 }
216 }
217#endif
218#endif
219#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
Peter Tyserd9c147f2009-07-17 10:14:48 -0500220 if (cs0_config & 0x20000000) {
221 puts("\n");
222 puts(" DDR Controller Interleaving Mode: ");
223
224 switch ((cs0_config >> 24) & 0xf) {
225 case FSL_DDR_CACHE_LINE_INTERLEAVING:
226 puts("cache line");
227 break;
228 case FSL_DDR_PAGE_INTERLEAVING:
229 puts("page");
230 break;
231 case FSL_DDR_BANK_INTERLEAVING:
232 puts("bank");
233 break;
234 case FSL_DDR_SUPERBANK_INTERLEAVING:
235 puts("super-bank");
236 break;
237 default:
238 puts("invalid");
239 break;
240 }
241 }
242#endif
243
244 if ((sdram_cfg >> 8) & 0x7f) {
245 puts("\n");
246 puts(" DDR Chip-Select Interleaving Mode: ");
247 switch(sdram_cfg >> 8 & 0x7f) {
248 case FSL_DDR_CS0_CS1_CS2_CS3:
249 puts("CS0+CS1+CS2+CS3");
250 break;
251 case FSL_DDR_CS0_CS1:
252 puts("CS0+CS1");
253 break;
254 case FSL_DDR_CS2_CS3:
255 puts("CS2+CS3");
256 break;
257 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
258 puts("CS0+CS1 and CS2+CS3");
259 break;
260 default:
261 puts("invalid");
262 break;
263 }
264 }
265}