TsiChungLiew | 570c018 | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de> |
| 3 | * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com> |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <config.h> |
| 25 | #include "version.h" |
| 26 | |
| 27 | #ifndef CONFIG_IDENT_STRING |
| 28 | #define CONFIG_IDENT_STRING "" |
| 29 | #endif |
| 30 | |
| 31 | /* last three long word reserved for cache status */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 32 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4) |
| 33 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8) |
| 34 | #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12) |
TsiChungLiew | 570c018 | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 35 | |
| 36 | #define _START _start |
| 37 | #define _FAULT _fault |
| 38 | |
| 39 | #define SAVE_ALL \ |
| 40 | move.w #0x2700,%sr; /* disable intrs */ \ |
| 41 | subl #60,%sp; /* space for 15 regs */ \ |
| 42 | moveml %d0-%d7/%a0-%a6,%sp@; |
| 43 | |
| 44 | #define RESTORE_ALL \ |
| 45 | moveml %sp@,%d0-%d7/%a0-%a6; \ |
| 46 | addl #60,%sp; /* space for 15 regs */ \ |
| 47 | rte; |
| 48 | |
| 49 | .text |
| 50 | /* |
| 51 | * Vector table. This is used for initial platform startup. |
| 52 | * These vectors are to catch any un-intended traps. |
| 53 | */ |
| 54 | _vectors: |
| 55 | |
| 56 | INITSP: .long 0x00000000 /* Initial SP */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 57 | INITPC: .long _START /* Initial PC */ |
TsiChungLiew | 570c018 | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 58 | vector02: .long _FAULT /* Access Error */ |
| 59 | vector03: .long _FAULT /* Address Error */ |
| 60 | vector04: .long _FAULT /* Illegal Instruction */ |
| 61 | vector05: .long _FAULT /* Reserved */ |
| 62 | vector06: .long _FAULT /* Reserved */ |
| 63 | vector07: .long _FAULT /* Reserved */ |
| 64 | vector08: .long _FAULT /* Privilege Violation */ |
| 65 | vector09: .long _FAULT /* Trace */ |
| 66 | vector0A: .long _FAULT /* Unimplemented A-Line */ |
| 67 | vector0B: .long _FAULT /* Unimplemented F-Line */ |
| 68 | vector0C: .long _FAULT /* Debug Interrupt */ |
| 69 | vector0D: .long _FAULT /* Reserved */ |
| 70 | vector0E: .long _FAULT /* Format Error */ |
| 71 | vector0F: .long _FAULT /* Unitialized Int. */ |
| 72 | |
| 73 | /* Reserved */ |
| 74 | vector10_17: |
| 75 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 76 | |
| 77 | vector18: .long _FAULT /* Spurious Interrupt */ |
| 78 | vector19: .long _FAULT /* Autovector Level 1 */ |
| 79 | vector1A: .long _FAULT /* Autovector Level 2 */ |
| 80 | vector1B: .long _FAULT /* Autovector Level 3 */ |
| 81 | vector1C: .long _FAULT /* Autovector Level 4 */ |
| 82 | vector1D: .long _FAULT /* Autovector Level 5 */ |
| 83 | vector1E: .long _FAULT /* Autovector Level 6 */ |
| 84 | vector1F: .long _FAULT /* Autovector Level 7 */ |
| 85 | |
| 86 | /* TRAP #0 - #15 */ |
| 87 | vector20_2F: |
| 88 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 89 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 90 | |
| 91 | /* Reserved */ |
| 92 | vector30_3F: |
| 93 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 94 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 95 | |
| 96 | vector64_127: |
| 97 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 98 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 99 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 100 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 101 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 102 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 103 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 104 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 105 | |
| 106 | vector128_191: |
| 107 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 108 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 109 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 110 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 111 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 112 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 113 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 114 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 115 | |
| 116 | vector192_255: |
| 117 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 118 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 119 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 120 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 121 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 122 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 123 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 124 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 125 | |
| 126 | .text |
| 127 | |
| 128 | .globl _start |
| 129 | _start: |
| 130 | nop |
| 131 | nop |
| 132 | move.w #0x2700,%sr /* Mask off Interrupt */ |
| 133 | |
| 134 | /* Set vector base register at the beginning of the Flash */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 135 | move.l #CONFIG_SYS_FLASH_BASE, %d0 |
TsiChungLiew | 570c018 | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 136 | movec %d0, %VBR |
| 137 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 138 | move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 |
TsiChungLiew | 570c018 | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 139 | movec %d0, %RAMBAR0 |
| 140 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 141 | move.l #(CONFIG_SYS_INIT_RAM1_ADDR + CONFIG_SYS_INIT_RAM1_CTRL), %d0 |
TsiChungLiew | 570c018 | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 142 | movec %d0, %RAMBAR1 |
| 143 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 144 | move.l #CONFIG_SYS_MBAR, %d0 /* set MBAR address */ |
TsiChungLiew | 570c018 | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 145 | move.c %d0, %MBAR |
| 146 | |
| 147 | /* invalidate and disable cache */ |
| 148 | move.l #0x01040100, %d0 /* Invalidate cache cmd */ |
| 149 | movec %d0, %CACR /* Invalidate cache */ |
| 150 | move.l #0, %d0 |
| 151 | movec %d0, %ACR0 |
| 152 | movec %d0, %ACR1 |
| 153 | movec %d0, %ACR2 |
| 154 | movec %d0, %ACR3 |
| 155 | |
| 156 | /* initialize general use internal ram */ |
| 157 | move.l #0, %d0 |
| 158 | move.l #(ICACHE_STATUS), %a1 /* icache */ |
| 159 | move.l #(DCACHE_STATUS), %a2 /* icache */ |
| 160 | move.l #(CACR_STATUS), %a3 /* CACR */ |
| 161 | move.l %d0, (%a1) |
| 162 | move.l %d0, (%a2) |
| 163 | move.l %d0, (%a3) |
| 164 | |
| 165 | /* set stackpointer to end of internal ram to get some stackspace for the |
| 166 | first c-code */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 167 | move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp |
TsiChungLiew | 570c018 | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 168 | clr.l %sp@- |
| 169 | |
| 170 | move.l #__got_start, %a5 /* put relocation table address to a5 */ |
| 171 | |
| 172 | bsr cpu_init_f /* run low-level CPU init code (from flash) */ |
| 173 | bsr board_init_f /* run low-level board init code (from flash) */ |
| 174 | |
| 175 | /* board_init_f() does not return */ |
| 176 | |
| 177 | /*------------------------------------------------------------------------------*/ |
| 178 | |
| 179 | /* |
| 180 | * void relocate_code (addr_sp, gd, addr_moni) |
| 181 | * |
| 182 | * This "function" does not return, instead it continues in RAM |
| 183 | * after relocating the monitor code. |
| 184 | * |
| 185 | * r3 = dest |
| 186 | * r4 = src |
| 187 | * r5 = length in bytes |
| 188 | * r6 = cachelinesize |
| 189 | */ |
| 190 | .globl relocate_code |
| 191 | relocate_code: |
| 192 | link.w %a6,#0 |
| 193 | move.l 8(%a6), %sp /* set new stack pointer */ |
| 194 | |
| 195 | move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ |
| 196 | move.l 16(%a6), %a0 /* Save copy of Destination Address */ |
| 197 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 198 | move.l #CONFIG_SYS_MONITOR_BASE, %a1 |
TsiChungLiew | 570c018 | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 199 | move.l #__init_end, %a2 |
| 200 | move.l %a0, %a3 |
| 201 | |
| 202 | /* copy the code to RAM */ |
| 203 | 1: |
| 204 | move.l (%a1)+, (%a3)+ |
| 205 | cmp.l %a1,%a2 |
| 206 | bgt.s 1b |
| 207 | |
| 208 | /* |
| 209 | * We are done. Do not return, instead branch to second part of board |
| 210 | * initialization, now running from RAM. |
| 211 | */ |
| 212 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 213 | add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 |
TsiChungLiew | 570c018 | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 214 | jmp (%a1) |
| 215 | |
| 216 | in_ram: |
| 217 | |
| 218 | clear_bss: |
| 219 | /* |
| 220 | * Now clear BSS segment |
| 221 | */ |
| 222 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 223 | add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 |
TsiChungLiew | 570c018 | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 224 | move.l %a0, %d1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 225 | add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 |
TsiChungLiew | 570c018 | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 226 | 6: |
| 227 | clr.l (%a1)+ |
| 228 | cmp.l %a1,%d1 |
| 229 | bgt.s 6b |
| 230 | |
| 231 | /* |
| 232 | * fix got table in RAM |
| 233 | */ |
| 234 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 235 | add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 |
TsiChungLiew | 570c018 | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 236 | move.l %a1,%a5 /* * fix got pointer register a5 */ |
| 237 | |
| 238 | move.l %a0, %a2 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 239 | add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 |
TsiChungLiew | 570c018 | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 240 | |
| 241 | 7: |
| 242 | move.l (%a1),%d1 |
| 243 | sub.l #_start,%d1 |
| 244 | add.l %a0,%d1 |
| 245 | move.l %d1,(%a1)+ |
| 246 | cmp.l %a2, %a1 |
| 247 | bne 7b |
| 248 | |
| 249 | /* calculate relative jump to board_init_r in ram */ |
| 250 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 251 | add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 |
TsiChungLiew | 570c018 | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 252 | |
| 253 | /* set parameters for board_init_r */ |
| 254 | move.l %a0,-(%sp) /* dest_addr */ |
| 255 | move.l %d0,-(%sp) /* gd */ |
| 256 | jsr (%a1) |
| 257 | |
| 258 | /*------------------------------------------------------------------------------*/ |
| 259 | /* exception code */ |
| 260 | .globl _fault |
| 261 | _fault: |
TsiChung Liew | 3b1e8ac | 2008-06-18 19:12:13 -0500 | [diff] [blame] | 262 | bra _fault |
TsiChungLiew | 570c018 | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 263 | .globl _exc_handler |
| 264 | |
| 265 | _exc_handler: |
| 266 | SAVE_ALL |
| 267 | movel %sp,%sp@- |
| 268 | bsr exc_handler |
| 269 | addql #4,%sp |
| 270 | RESTORE_ALL |
| 271 | |
| 272 | .globl _int_handler |
| 273 | _int_handler: |
| 274 | SAVE_ALL |
| 275 | movel %sp,%sp@- |
| 276 | bsr int_handler |
| 277 | addql #4,%sp |
| 278 | RESTORE_ALL |
| 279 | |
| 280 | /*------------------------------------------------------------------------------*/ |
| 281 | /* cache functions */ |
| 282 | .globl icache_enable |
| 283 | icache_enable: |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 284 | move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 |
TsiChungLiew | 570c018 | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 285 | movec %d0, %ACR2 /* Enable cache */ |
| 286 | |
| 287 | move.l #0x020C8100, %d0 /* Setup cache mask */ |
| 288 | movec %d0, %CACR /* Enable cache */ |
| 289 | nop |
| 290 | |
| 291 | move.l #(ICACHE_STATUS), %a1 |
| 292 | moveq #1, %d0 |
| 293 | move.l %d0, (%a1) |
| 294 | rts |
| 295 | |
| 296 | .globl icache_disable |
| 297 | icache_disable: |
| 298 | move.l #0x000C8100, %d0 /* Setup cache mask */ |
| 299 | movec %d0, %CACR /* Disable cache */ |
| 300 | clr.l %d0 /* Setup cache mask */ |
| 301 | movec %d0, %ACR2 |
| 302 | movec %d0, %ACR3 |
| 303 | |
| 304 | move.l #(ICACHE_STATUS), %a1 |
| 305 | moveq #0, %d0 |
| 306 | move.l %d0, (%a1) |
| 307 | rts |
| 308 | |
| 309 | .globl icache_invalid |
| 310 | icache_invalid: |
| 311 | move.l #0x000C8100, %d0 /* Setup cache mask */ |
| 312 | movec %d0, %CACR /* Enable cache */ |
| 313 | rts |
| 314 | |
| 315 | .globl icache_status |
| 316 | icache_status: |
| 317 | move.l #(ICACHE_STATUS), %a1 |
| 318 | move.l (%a1), %d0 |
| 319 | rts |
| 320 | |
| 321 | .globl dcache_enable |
| 322 | dcache_enable: |
| 323 | bsr icache_disable |
| 324 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 325 | move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 |
TsiChungLiew | 570c018 | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 326 | movec %d0, %ACR0 /* Enable cache */ |
| 327 | |
| 328 | move.l #0xA30C8100, %d0 /* Invalidate cache cmd */ |
| 329 | movec %d0, %CACR /* Invalidate cache */ |
| 330 | |
| 331 | move.l #(DCACHE_STATUS), %a1 |
| 332 | moveq #1, %d0 |
| 333 | move.l %d0, (%a1) |
| 334 | rts |
| 335 | |
| 336 | .globl dcache_disable |
| 337 | dcache_disable: |
| 338 | move.l #0xA30C8100, %d0 /* Setup cache mask */ |
| 339 | movec %d0, %CACR /* Disable cache */ |
| 340 | clr.l %d0 /* Setup cache mask */ |
| 341 | movec %d0, %ACR0 |
| 342 | movec %d0, %ACR1 |
| 343 | |
| 344 | move.l #(DCACHE_STATUS), %a1 |
| 345 | moveq #0, %d0 |
| 346 | move.l %d0, (%a1) |
| 347 | rts |
| 348 | |
| 349 | .globl dcache_status |
| 350 | dcache_status: |
| 351 | move.l #(DCACHE_STATUS), %a1 |
| 352 | move.l (%a1), %d0 |
| 353 | rts |
| 354 | |
| 355 | /*------------------------------------------------------------------------------*/ |
| 356 | |
| 357 | .globl version_string |
| 358 | version_string: |
| 359 | .ascii U_BOOT_VERSION |
| 360 | .ascii " (", __DATE__, " - ", __TIME__, ")" |
| 361 | .ascii CONFIG_IDENT_STRING, "\0" |
TsiChung Liew | 9b46432 | 2008-03-28 08:47:45 -0500 | [diff] [blame] | 362 | .align 4 |