blob: 408c88498e5ad8f3c66fa577263e2cb4a571d132 [file] [log] [blame]
wdenkea8015b2002-10-26 16:43:06 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26
27ulong myflush(void);
28
29
30#define FLASH_BANK_SIZE 0x800000
31#define MAIN_SECT_SIZE 0x20000
32#define PARAM_SECT_SIZE 0x4000
33
34/* puzzle magic for lart
35 * data_*_flash are def'd in flashasm.S
36 */
37
38extern u32 data_from_flash(u32);
39extern u32 data_to_flash(u32);
40
41#define PUZZLE_FROM_FLASH(x) data_from_flash((x))
42#define PUZZLE_TO_FLASH(x) data_to_flash((x))
43
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
wdenkea8015b2002-10-26 16:43:06 +000045
46
47#define CMD_READ_ARRAY 0x00FF00FF
48#define CMD_IDENTIFY 0x00900090
49#define CMD_ERASE_SETUP 0x00200020
50#define CMD_ERASE_CONFIRM 0x00D000D0
51#define CMD_PROGRAM 0x00400040
52#define CMD_RESUME 0x00D000D0
53#define CMD_SUSPEND 0x00B000B0
54#define CMD_STATUS_READ 0x00700070
55#define CMD_STATUS_RESET 0x00500050
56
57#define BIT_BUSY 0x00800080
58#define BIT_ERASE_SUSPEND 0x00400040
59#define BIT_ERASE_ERROR 0x00200020
60#define BIT_PROGRAM_ERROR 0x00100010
61#define BIT_VPP_RANGE_ERROR 0x00080008
62#define BIT_PROGRAM_SUSPEND 0x00040004
63#define BIT_PROTECT_ERROR 0x00020002
64#define BIT_UNDEFINED 0x00010001
65
66#define BIT_SEQUENCE_ERROR 0x00300030
67#define BIT_TIMEOUT 0x80000000
68
69/*-----------------------------------------------------------------------
70 */
71
72ulong flash_init(void)
73{
74 int i, j;
75 ulong size = 0;
76
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
wdenkea8015b2002-10-26 16:43:06 +000078 {
79 ulong flashbase = 0;
80 flash_info[i].flash_id =
81 (INTEL_MANUFACT & FLASH_VENDMASK) |
82 (INTEL_ID_28F160F3B & FLASH_TYPEMASK);
83 flash_info[i].size = FLASH_BANK_SIZE;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084 flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
85 memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
wdenkea8015b2002-10-26 16:43:06 +000086 if (i == 0)
87 flashbase = PHYS_FLASH_1;
88 else
wdenk5f535fe2003-09-18 09:21:33 +000089 panic("configured too many flash banks!\n");
wdenkea8015b2002-10-26 16:43:06 +000090 for (j = 0; j < flash_info[i].sector_count; j++)
91 {
92 if (j <= 7)
93 {
94 flash_info[i].start[j] = flashbase + j * PARAM_SECT_SIZE;
95 }
96 else
97 {
98 flash_info[i].start[j] = flashbase + (j - 7)*MAIN_SECT_SIZE;
99 }
100 }
101 size += flash_info[i].size;
102 }
103
104 /* Protect monitor and environment sectors
105 */
106 flash_protect(FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107 CONFIG_SYS_FLASH_BASE,
108 CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
wdenkea8015b2002-10-26 16:43:06 +0000109 &flash_info[0]);
110
111 flash_protect(FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200112 CONFIG_ENV_ADDR,
113 CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
wdenkea8015b2002-10-26 16:43:06 +0000114 &flash_info[0]);
115
116 return size;
117}
118
119/*-----------------------------------------------------------------------
120 */
121void flash_print_info (flash_info_t *info)
122{
123 int i;
124
125 switch (info->flash_id & FLASH_VENDMASK)
126 {
127 case (INTEL_MANUFACT & FLASH_VENDMASK):
128 printf("Intel: ");
129 break;
130 default:
131 printf("Unknown Vendor ");
132 break;
133 }
134
135 switch (info->flash_id & FLASH_TYPEMASK)
136 {
137 case (INTEL_ID_28F160F3B & FLASH_TYPEMASK):
138 printf("2x 28F160F3B (16Mbit)\n");
139 break;
140 default:
141 printf("Unknown Chip Type\n");
142 goto Done;
143 break;
144 }
145
146 printf(" Size: %ld MB in %d Sectors\n",
147 info->size >> 20, info->sector_count);
148
149 printf(" Sector Start Addresses:");
150 for (i = 0; i < info->sector_count; i++)
151 {
152 if ((i % 5) == 0)
153 {
154 printf ("\n ");
155 }
156 printf (" %08lX%s", info->start[i],
157 info->protect[i] ? " (RO)" : " ");
158 }
159 printf ("\n");
160
161Done:
wdenke86e5a02004-10-17 21:12:06 +0000162 ;
wdenkea8015b2002-10-26 16:43:06 +0000163}
164
165/*-----------------------------------------------------------------------
166 */
167
168int flash_error (ulong code)
169{
170 /* Check bit patterns */
171 /* SR.7=0 is busy, SR.7=1 is ready */
172 /* all other flags indicate error on 1 */
173 /* SR.0 is undefined */
174 /* Timeout is our faked flag */
175
176 /* sequence is described in Intel 290644-005 document */
177
178 /* check Timeout */
179 if (code & BIT_TIMEOUT)
180 {
181 printf ("Timeout\n");
182 return ERR_TIMOUT;
183 }
184
185 /* check Busy, SR.7 */
186 if (~code & BIT_BUSY)
187 {
188 printf ("Busy\n");
189 return ERR_PROG_ERROR;
190 }
191
192 /* check Vpp low, SR.3 */
193 if (code & BIT_VPP_RANGE_ERROR)
194 {
195 printf ("Vpp range error\n");
196 return ERR_PROG_ERROR;
197 }
198
199 /* check Device Protect Error, SR.1 */
200 if (code & BIT_PROTECT_ERROR)
201 {
202 printf ("Device protect error\n");
203 return ERR_PROG_ERROR;
204 }
205
206 /* check Command Seq Error, SR.4 & SR.5 */
207 if (code & BIT_SEQUENCE_ERROR)
208 {
209 printf ("Command seqence error\n");
210 return ERR_PROG_ERROR;
211 }
212
213 /* check Block Erase Error, SR.5 */
214 if (code & BIT_ERASE_ERROR)
215 {
216 printf ("Block erase error\n");
217 return ERR_PROG_ERROR;
218 }
219
220 /* check Program Error, SR.4 */
221 if (code & BIT_PROGRAM_ERROR)
222 {
223 printf ("Program error\n");
224 return ERR_PROG_ERROR;
225 }
226
227 /* check Block Erase Suspended, SR.6 */
228 if (code & BIT_ERASE_SUSPEND)
229 {
230 printf ("Block erase suspended\n");
231 return ERR_PROG_ERROR;
232 }
233
234 /* check Program Suspended, SR.2 */
235 if (code & BIT_PROGRAM_SUSPEND)
236 {
237 printf ("Program suspended\n");
238 return ERR_PROG_ERROR;
239 }
240
241 /* OK, no error */
242 return ERR_OK;
243}
244
245/*-----------------------------------------------------------------------
246 */
247
248int flash_erase (flash_info_t *info, int s_first, int s_last)
249{
250 ulong result;
251 int iflag, cflag, prot, sect;
252 int rc = ERR_OK;
Graeme Russa60d1e52011-07-15 23:31:37 +0000253 ulong start;
wdenkea8015b2002-10-26 16:43:06 +0000254
255 /* first look for protection bits */
256
257 if (info->flash_id == FLASH_UNKNOWN)
258 return ERR_UNKNOWN_FLASH_TYPE;
259
260 if ((s_first < 0) || (s_first > s_last)) {
261 return ERR_INVAL;
262 }
263
264 if ((info->flash_id & FLASH_VENDMASK) !=
265 (INTEL_MANUFACT & FLASH_VENDMASK)) {
266 return ERR_UNKNOWN_FLASH_VENDOR;
267 }
268
269 prot = 0;
270 for (sect=s_first; sect<=s_last; ++sect) {
271 if (info->protect[sect]) {
272 prot++;
273 }
274 }
275 if (prot)
276 return ERR_PROTECTED;
277
278 /*
279 * Disable interrupts which might cause a timeout
280 * here. Remember that our exception vectors are
281 * at address 0 in the flash, and we don't want a
282 * (ticker) exception to happen while the flash
283 * chip is in programming mode.
284 */
285 cflag = icache_status();
286 icache_disable();
287 iflag = disable_interrupts();
288
289 /* Start erase on unprotected sectors */
290 for (sect = s_first; sect<=s_last && !ctrlc(); sect++)
291 {
292 printf("Erasing sector %2d ... ", sect);
293
294 /* arm simple, non interrupt dependent timer */
Graeme Russa60d1e52011-07-15 23:31:37 +0000295 start = get_timer(0);
wdenkea8015b2002-10-26 16:43:06 +0000296
297 if (info->protect[sect] == 0)
298 { /* not protected */
299 vu_long *addr = (vu_long *)(info->start[sect]);
300
301 *addr = PUZZLE_TO_FLASH(CMD_STATUS_RESET);
302 *addr = PUZZLE_TO_FLASH(CMD_ERASE_SETUP);
303 *addr = PUZZLE_TO_FLASH(CMD_ERASE_CONFIRM);
304
305 /* wait until flash is ready */
306 do
307 {
308 /* check timeout */
Graeme Russa60d1e52011-07-15 23:31:37 +0000309 if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT)
wdenkea8015b2002-10-26 16:43:06 +0000310 {
311 *addr = PUZZLE_TO_FLASH(CMD_SUSPEND);
312 result = BIT_TIMEOUT;
313 break;
314 }
315
316 result = PUZZLE_FROM_FLASH(*addr);
317 } while (~result & BIT_BUSY);
318
319 *addr = PUZZLE_TO_FLASH(CMD_READ_ARRAY);
320
321 if ((rc = flash_error(result)) != ERR_OK)
wdenk8bde7f72003-06-27 21:31:46 +0000322 goto outahere;
wdenkea8015b2002-10-26 16:43:06 +0000323
324 printf("ok.\n");
325 }
326 else /* it was protected */
327 {
328 printf("protected!\n");
329 }
330 }
331
332 if (ctrlc())
333 printf("User Interrupt!\n");
334
335outahere:
336 /* allow flash to settle - wait 10 ms */
337 udelay_masked(10000);
338
339 if (iflag)
340 enable_interrupts();
341
342 if (cflag)
343 icache_enable();
344
345 return rc;
346}
347
348/*-----------------------------------------------------------------------
349 * Copy memory to flash
350 */
351
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100352static int write_word (flash_info_t *info, ulong dest, ulong data)
wdenkea8015b2002-10-26 16:43:06 +0000353{
354 vu_long *addr = (vu_long *)dest;
355 ulong result;
356 int rc = ERR_OK;
357 int cflag, iflag;
Graeme Russa60d1e52011-07-15 23:31:37 +0000358 ulong start;
wdenkea8015b2002-10-26 16:43:06 +0000359
360 /* Check if Flash is (sufficiently) erased
361 */
362 result = PUZZLE_FROM_FLASH(*addr);
363 if ((result & data) != data)
wdenk8bde7f72003-06-27 21:31:46 +0000364 return ERR_NOT_ERASED;
wdenkea8015b2002-10-26 16:43:06 +0000365
366 /*
367 * Disable interrupts which might cause a timeout
368 * here. Remember that our exception vectors are
369 * at address 0 in the flash, and we don't want a
370 * (ticker) exception to happen while the flash
371 * chip is in programming mode.
372 */
373 cflag = icache_status();
374 icache_disable();
375 iflag = disable_interrupts();
376
377 *addr = PUZZLE_TO_FLASH(CMD_STATUS_RESET);
378 *addr = PUZZLE_TO_FLASH(CMD_PROGRAM);
379 *addr = data;
380
381 /* arm simple, non interrupt dependent timer */
Graeme Russa60d1e52011-07-15 23:31:37 +0000382 start = get_timer(0);
wdenkea8015b2002-10-26 16:43:06 +0000383
384 /* wait until flash is ready */
385 do
386 {
387 /* check timeout */
Graeme Russa60d1e52011-07-15 23:31:37 +0000388 if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT)
wdenkea8015b2002-10-26 16:43:06 +0000389 {
390 *addr = PUZZLE_TO_FLASH(CMD_SUSPEND);
391 result = BIT_TIMEOUT;
392 break;
393 }
394
395 result = PUZZLE_FROM_FLASH(*addr);
396 } while (~result & BIT_BUSY);
397
398 *addr = PUZZLE_TO_FLASH(CMD_READ_ARRAY);
399
400 rc = flash_error(result);
401
402 if (iflag)
403 enable_interrupts();
404
405 if (cflag)
406 icache_enable();
407
408 return rc;
409}
410
411/*-----------------------------------------------------------------------
412 * Copy memory to flash.
413 */
414
415int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
416{
417 ulong cp, wp, data;
418 int l;
419 int i, rc;
420
421 wp = (addr & ~3); /* get lower word aligned address */
422
423 /*
424 * handle unaligned start bytes
425 */
426 if ((l = addr - wp) != 0) {
427 data = 0;
428 for (i=0, cp=wp; i<l; ++i, ++cp) {
429 data = (data >> 8) | (*(uchar *)cp << 24);
430 }
431 for (; i<4 && cnt>0; ++i) {
432 data = (data >> 8) | (*src++ << 24);
433 --cnt;
434 ++cp;
435 }
436 for (; cnt==0 && i<4; ++i, ++cp) {
437 data = (data >> 8) | (*(uchar *)cp << 24);
438 }
439
440 if ((rc = write_word(info, wp, data)) != 0) {
441 return (rc);
442 }
443 wp += 4;
444 }
445
446 /*
447 * handle word aligned part
448 */
449 while (cnt >= 4) {
450 data = *((vu_long*)src);
451 if ((rc = write_word(info, wp, data)) != 0) {
452 return (rc);
453 }
454 src += 4;
455 wp += 4;
456 cnt -= 4;
457 }
458
459 if (cnt == 0) {
460 return ERR_OK;
461 }
462
463 /*
464 * handle unaligned tail bytes
465 */
466 data = 0;
467 for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
468 data = (data >> 8) | (*src++ << 24);
469 --cnt;
470 }
471 for (; i<4; ++i, ++cp) {
472 data = (data >> 8) | (*(uchar *)cp << 24);
473 }
474
475 return write_word(info, wp, data);
476}