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Green Wan2113c002021-05-27 06:52:11 -07001// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * (C) Copyright 2020-2021 SiFive, Inc
4 */
5
6#include <dt-bindings/reset/sifive-fu740-prci.h>
7
8/ {
9 cpus {
10 assigned-clocks = <&prci PRCI_CLK_COREPLL>;
11 assigned-clock-rates = <1200000000>;
12 u-boot,dm-spl;
13 cpu0: cpu@0 {
14 clocks = <&prci PRCI_CLK_COREPLL>;
15 u-boot,dm-spl;
16 status = "okay";
17 cpu0_intc: interrupt-controller {
18 u-boot,dm-spl;
19 };
20 };
21 cpu1: cpu@1 {
22 clocks = <&prci PRCI_CLK_COREPLL>;
23 u-boot,dm-spl;
24 cpu1_intc: interrupt-controller {
25 u-boot,dm-spl;
26 };
27 };
28 cpu2: cpu@2 {
29 clocks = <&prci PRCI_CLK_COREPLL>;
30 u-boot,dm-spl;
31 cpu2_intc: interrupt-controller {
32 u-boot,dm-spl;
33 };
34 };
35 cpu3: cpu@3 {
36 clocks = <&prci PRCI_CLK_COREPLL>;
37 u-boot,dm-spl;
38 cpu3_intc: interrupt-controller {
39 u-boot,dm-spl;
40 };
41 };
42 cpu4: cpu@4 {
43 clocks = <&prci PRCI_CLK_COREPLL>;
44 u-boot,dm-spl;
45 cpu4_intc: interrupt-controller {
46 u-boot,dm-spl;
47 };
48 };
49 };
50
51 soc {
52 u-boot,dm-spl;
53 clint: clint@2000000 {
54 compatible = "riscv,clint0";
55 interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
56 &cpu1_intc 3 &cpu1_intc 7
57 &cpu2_intc 3 &cpu2_intc 7
58 &cpu3_intc 3 &cpu3_intc 7
59 &cpu4_intc 3 &cpu4_intc 7>;
60 reg = <0x0 0x2000000 0x0 0x10000>;
61 u-boot,dm-spl;
62 };
63 prci: clock-controller@10000000 {
64 #reset-cells = <1>;
65 resets = <&prci PRCI_RST_DDR_CTRL_N>,
66 <&prci PRCI_RST_DDR_AXI_N>,
67 <&prci PRCI_RST_DDR_AHB_N>,
68 <&prci PRCI_RST_DDR_PHY_N>,
69 <&prci PRCI_RST_GEMGXL_N>,
70 <&prci PRCI_RST_CLTX_N>;
71 reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb",
72 "ddr_phy", "gemgxl_reset", "cltx_reset";
73 };
74 dmc: dmc@100b0000 {
75 compatible = "sifive,fu740-c000-ddr";
76 reg = <0x0 0x100b0000 0x0 0x0800
77 0x0 0x100b2000 0x0 0x2000
78 0x0 0x100b8000 0x0 0x1000>;
79 clocks = <&prci PRCI_CLK_DDRPLL>;
80 clock-frequency = <933333324>;
81 u-boot,dm-spl;
82 };
83 };
84};
85
86&prci {
87 u-boot,dm-spl;
88};
89
90&uart0 {
91 u-boot,dm-spl;
92};
93
94&spi0 {
95 u-boot,dm-spl;
96};
97
Zong Li564d6302021-06-30 23:23:47 +080098&i2c0 {
99 u-boot,dm-spl;
100};
101
Green Wan2113c002021-05-27 06:52:11 -0700102&eth0 {
103 assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
104 assigned-clock-rates = <125125000>;
105};
106
107&ccache {
108 status = "okay";
109};