| Ashok Reddy Soma | 3c53ebd | 2022-11-16 07:11:53 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * dts file for Xilinx Versal Mini QSPI Configuration |
| 4 | * |
| 5 | * (C) Copyright 2018-2019, Xilinx, Inc. |
| 6 | * |
| 7 | * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> |
| 8 | * Michal Simek <michal.simek@xilinx.com> |
| 9 | */ |
| 10 | |
| 11 | /dts-v1/; |
| 12 | |
| 13 | / { |
| 14 | compatible = "xlnx,versal"; |
| 15 | #address-cells = <2>; |
| 16 | #size-cells = <2>; |
| 17 | model = "Xilinx Versal MINI QSPI"; |
| 18 | |
| 19 | clk150: clk150 { |
| 20 | compatible = "fixed-clock"; |
| 21 | #clock-cells = <0x0>; |
| 22 | clock-frequency = <150000000>; |
| 23 | }; |
| 24 | |
| 25 | dcc: dcc { |
| 26 | compatible = "arm,dcc"; |
| 27 | status = "okay"; |
| 28 | u-boot,dm-pre-reloc; |
| 29 | }; |
| 30 | |
| 31 | amba: amba { |
| 32 | u-boot,dm-pre-reloc; |
| 33 | compatible = "simple-bus"; |
| 34 | #address-cells = <0x2>; |
| 35 | #size-cells = <0x2>; |
| 36 | ranges; |
| 37 | |
| 38 | qspi: spi@f1030000 { |
| 39 | compatible = "xlnx,versal-qspi-1.0"; |
| 40 | status = "okay"; |
| 41 | clock-names = "ref_clk", "pclk"; |
| 42 | num-cs = <0x1>; |
| 43 | reg = <0x0 0xf1030000 0x0 0x1000>; |
| 44 | #address-cells = <1>; |
| 45 | #size-cells = <0>; |
| 46 | clocks = <&clk150 &clk150>; |
| 47 | |
| 48 | flash0: flash@0 { |
| 49 | compatible = "n25q512a", "micron,m25p80", |
| 50 | "jedec,spi-nor"; |
| 51 | reg = <0x0>; |
| 52 | spi-tx-bus-width = <4>; |
| 53 | spi-rx-bus-width = <4>; |
| 54 | spi-max-frequency = <20000000>; |
| 55 | }; |
| 56 | }; |
| 57 | }; |
| 58 | |
| 59 | aliases { |
| 60 | serial0 = &dcc; |
| 61 | spi0 = &qspi; |
| 62 | }; |
| 63 | |
| 64 | chosen { |
| 65 | stdout-path = "serial0:115200"; |
| 66 | }; |
| 67 | |
| 68 | memory@fffc0000 { |
| 69 | device_type = "memory"; |
| 70 | reg = <0x0 0xfffc0000 0x0 0x40000>; |
| 71 | }; |
| 72 | }; |