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wdenk2d24a3a2004-06-09 21:50:45 +00001/*
Wolfgang Denk5797b822006-03-12 01:43:03 +01002 * Copyright (C) 2004-2005 Arabella Software Ltd.
wdenk2d24a3a2004-06-09 21:50:45 +00003 * Yuli Barcohen <yuli@arabellasw.com>
4 *
5 * Support for Analogue&Micro Adder boards family.
6 * Tested on AdderII and Adder87x.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29#if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T)
30#define CONFIG_MPC875
31#endif
32
33#define CONFIG_ADDER /* Analogue&Micro Adder board */
34
35#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
36#define CONFIG_BAUDRATE 38400
37
Wolfgang Denk5797b822006-03-12 01:43:03 +010038#define CONFIG_ETHER_ON_FEC1
39#define CONFIG_ETHER_ON_FEC2
40
41#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
wdenk2d24a3a2004-06-09 21:50:45 +000042#define CFG_DISCOVER_PHY
43#define FEC_ENET
Wolfgang Denk5797b822006-03-12 01:43:03 +010044#endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */
wdenk2d24a3a2004-06-09 21:50:45 +000045
wdenk66ca92a2004-09-28 17:59:53 +000046#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
47#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
48#define CFG_8xx_CPUCLK_MIN 40000000
49#ifdef CONFIG_MPC852T
50#define CFG_8xx_CPUCLK_MAX 50000000
51#else
Wolfgang Denk5797b822006-03-12 01:43:03 +010052#define CFG_8xx_CPUCLK_MAX 133000000
wdenk66ca92a2004-09-28 17:59:53 +000053#endif /* CONFIG_MPC852T */
wdenk2d24a3a2004-06-09 21:50:45 +000054
55#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
56 | CFG_CMD_DHCP \
57 | CFG_CMD_IMMAP \
58 | CFG_CMD_MII \
59 | CFG_CMD_PING \
60 )
61
62/* This must be included AFTER the definition of CONFIG_COMMANDS */
63#include <cmd_confdefs.h>
64
65#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
66#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */
Wolfgang Denk5797b822006-03-12 01:43:03 +010067#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)"
wdenk2d24a3a2004-06-09 21:50:45 +000068
69#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
70#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
71
72/*-----------------------------------------------------------------------
73 * Miscellaneous configurable options
74 */
75#define CFG_PROMPT "=> " /* Monitor Command Prompt */
76#define CFG_HUSH_PARSER
77#define CFG_PROMPT_HUSH_PS2 "> "
78#define CFG_LONGHELP /* #undef to save memory */
79#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
80#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
81#define CFG_MAXARGS 16 /* Max number of command args */
82#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
83
Wolfgang Denk5797b822006-03-12 01:43:03 +010084#define CFG_LOAD_ADDR 0x400000 /* Default load address */
wdenk2d24a3a2004-06-09 21:50:45 +000085
86#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
87
88#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
89
90/*-----------------------------------------------------------------------
91 * RAM configuration (note that CFG_SDRAM_BASE must be zero)
92 */
93#define CFG_SDRAM_BASE 0x00000000
Wolfgang Denk5797b822006-03-12 01:43:03 +010094#define CFG_SDRAM_MAX_SIZE 0x01000000 /* Up to 16 Mbyte */
wdenk2d24a3a2004-06-09 21:50:45 +000095
Wolfgang Denk5797b822006-03-12 01:43:03 +010096#define CFG_MAMR 0x00002114
wdenk2d24a3a2004-06-09 21:50:45 +000097
wdenk66ca92a2004-09-28 17:59:53 +000098/*
Wolfgang Denk5797b822006-03-12 01:43:03 +010099 * 4096 Up to 4096 SDRAM rows
wdenk66ca92a2004-09-28 17:59:53 +0000100 * 1000 factor s -> ms
Wolfgang Denk5797b822006-03-12 01:43:03 +0100101 * 32 PTP (pre-divider from MPTPR)
wdenk66ca92a2004-09-28 17:59:53 +0000102 * 4 Number of refresh cycles per period
103 * 64 Refresh cycle in ms per number of rows
104 */
Wolfgang Denk5797b822006-03-12 01:43:03 +0100105#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
wdenk66ca92a2004-09-28 17:59:53 +0000106
wdenk2d24a3a2004-06-09 21:50:45 +0000107#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
Wolfgang Denk5797b822006-03-12 01:43:03 +0100108#define CFG_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */
wdenk2d24a3a2004-06-09 21:50:45 +0000109
110#define CFG_RESET_ADDRESS 0x09900000
111
112/*-----------------------------------------------------------------------
113 * For booting Linux, the board info and command line data
114 * have to be in the first 8 MB of memory, since this is
115 * the maximum mapped by the Linux kernel during initialization.
116 */
117#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
118
119#define CFG_MONITOR_BASE TEXT_BASE
120#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 KB for Monitor */
121#ifdef CONFIG_BZIP2
122#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
123#else
124#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
125#endif /* CONFIG_BZIP2 */
126
127/*-----------------------------------------------------------------------
128 * Flash organisation
129 */
130#define CFG_FLASH_BASE 0xFE000000
131#define CFG_FLASH_CFI /* The flash is CFI compatible */
132#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
133#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
134#define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
135
136/* Environment is in flash */
137#define CFG_ENV_IS_IN_FLASH
138#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
139#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
140
Wolfgang Denk5797b822006-03-12 01:43:03 +0100141#define CONFIG_ENV_OVERWRITE
142
wdenk2d24a3a2004-06-09 21:50:45 +0000143#define CFG_OR0_PRELIM 0xFF000774
144#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V)
145
wdenk26238132004-07-09 22:51:01 +0000146#define CFG_DIRECT_FLASH_TFTP
147
wdenk2d24a3a2004-06-09 21:50:45 +0000148/*-----------------------------------------------------------------------
149 * Internal Memory Map Register
150 */
151#define CFG_IMMR 0xFF000000
152
153/*-----------------------------------------------------------------------
154 * Definitions for initial stack pointer and data area (in DPRAM)
155 */
156#define CFG_INIT_RAM_ADDR CFG_IMMR
157#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
158#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */
159#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
160#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
161
162/*-----------------------------------------------------------------------
163 * Configuration registers
164 */
165#ifdef CONFIG_WATCHDOG
166#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
167 SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \
168 SYPCR_SWP)
169#else
170#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
171 SYPCR_SWF | SYPCR_SWP)
172#endif /* CONFIG_WATCHDOG */
173
174#define CFG_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11)
175
176/* TBSCR - Time Base Status and Control Register */
177#define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE)
178
179/* PISCR - Periodic Interrupt Status and Control */
180#define CFG_PISCR (PISCR_PS | PISCR_PITF)
181
182/* PLPRCR - PLL, Low-Power, and Reset Control Register */
183/* #define CFG_PLPRCR PLPRCR_TEXPS */
184
185/* SCCR - System Clock and reset Control Register */
186#define SCCR_MASK SCCR_EBDF11
187#define CFG_SCCR SCCR_RTSEL
188
189#define CFG_DER 0
190
191/*-----------------------------------------------------------------------
192 * Cache Configuration
193 */
194#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx chips */
195
196/*-----------------------------------------------------------------------
197 * Internal Definitions
198 *
199 * Boot Flags
200 */
201#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */
202#define BOOTFLAG_WARM 0x02 /* Software reboot */
203
204#endif /* __CONFIG_H */