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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * ML2.h: ML2 specific config options
3 *
4 * Copyright 2002 Mind NV
5 *
6 * http://www.mind.be/
7 *
8 * Author : Peter De Schrijver (p2@mind.be)
9 *
10 * Derived from : other configuration header files in this tree
11 *
12 * This software may be used and distributed according to the terms of
13 * the GNU General Public License (GPL) version 2, incorporated herein by
14 * reference. Drivers based on or derived from this code fall under the GPL
15 * and must retain the authorship, copyright and this license notice. This
16 * file is not a complete program and may only be used when the entire
17 * program is licensed under the GPL.
18 *
19 */
20
21#ifndef __CONFIG_H
22#define __CONFIG_H
23
24/*
25 * High Level Configuration Options
26 * (easy to change)
27 */
28
29#define CONFIG_405 1 /* This is a PPC405 CPU */
30#define CONFIG_4xx 1 /* ...member of PPC4xx family */
31#define CONFIG_ML2 1 /* ...on a ML2 board */
32
33
34#define CFG_ENV_IS_IN_FLASH 1
35
36#ifdef CFG_ENV_IS_IN_NVRAM
37#undef CFG_ENV_IS_IN_FLASH
38#else
39#ifdef CFG_ENV_IS_IN_FLASH
40#undef CFG_ENV_IS_IN_NVRAM
41#endif
42#endif
43
44#define CONFIG_BAUDRATE 9600
45#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
46
47#if 1
48#define CONFIG_BOOTCOMMAND "bootm" /* autoboot command */
49#else
50#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
51#endif
52
53#define CONFIG_PREBOOT "fsload 0x00100000 /boot/image"
54
55/* Size (bytes) of interrupt driven serial port buffer.
56 * Set to 0 to use polling instead of interrupts.
57 * Setting to 0 will also disable RTS/CTS handshaking.
58 */
59#if 0
60#define CONFIG_SERIAL_SOFTWARE_FIFO 4000
61#else
62#undef CONFIG_SERIAL_SOFTWARE_FIFO
63#endif
64
65#if 0
66#define CONFIG_BOOTARGS "root=/dev/nfs " \
67 "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
68 "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
69#else
70#define CONFIG_BOOTARGS "root=/dev/mtdblock2 " \
71 "console=ttyS0 console=tty"
72
73#endif
74
75#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
76#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
77
78
wdenkeedcd072004-09-08 22:03:11 +000079#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & \
80 ~( CFG_CMD_NET | \
81 CFG_CMD_RTC | \
82 CFG_CMD_PCI | \
83 CFG_CMD_I2C \
84 ) ) | \
wdenkfe8c2802002-11-03 00:38:21 +000085 CFG_CMD_IRQ | \
86 CFG_CMD_KGDB | \
87 CFG_CMD_BEDBUG | \
wdenkeedcd072004-09-08 22:03:11 +000088 CFG_CMD_ELF | \
89 CFG_CMD_JFFS2 )
wdenkfe8c2802002-11-03 00:38:21 +000090
91/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
92#include <cmd_confdefs.h>
93
94#undef CONFIG_WATCHDOG /* watchdog disabled */
95
96#define CONFIG_SYS_CLK_FREQ 50000000
97
98#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
99
100/*
101 * Miscellaneous configurable options
102 */
103#define CFG_LONGHELP /* undef to save memory */
104#define CFG_PROMPT "=> " /* Monitor Command Prompt */
105#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
106#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
107#else
108#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
109#endif
110#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
111#define CFG_MAXARGS 16 /* max number of command args */
112#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
113
114#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
115#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
116
117/*
118 * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
119 * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
120 * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
121 * The Linux BASE_BAUD define should match this configuration.
122 * baseBaud = cpuClock/(uartDivisor*16)
123 * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
124 * set Linux BASE_BAUD to 403200.
125 */
126#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
127#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
128
129#define CFG_BASE_BAUD (3125000*16)
130#define CFG_NS16550_CLK CFG_BASE_BAUD
131#define CFG_DUART_CHAN 0
132#define CFG_NS16550_COM1 0xa0001003
133#define CFG_NS16550_COM2 0xa0011003
134#define CFG_NS16550_REG_SIZE -4
135#define CFG_NS16550 1
136#define CFG_INIT_CHAN1 1
137#define CFG_INIT_CHAN2 1
138
139/* The following table includes the supported baudrates */
140#define CFG_BAUDRATE_TABLE \
141 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
142
143#define CFG_LOAD_ADDR 0x100000 /* default load address */
144#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
145
146#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
147
148
wdenkfe8c2802002-11-03 00:38:21 +0000149/*-----------------------------------------------------------------------
150 * Start addresses for the final memory configuration
151 * (Set up by the startup code)
152 * Please note that CFG_SDRAM_BASE _must_ start at 0
153 */
154#define CFG_SDRAM_BASE 0x00000000
155#define CFG_FLASH_BASE 0x18000000
156#define CFG_MONITOR_BASE CFG_FLASH_BASE
157#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
158#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
159
160/*
161 * For booting Linux, the board info and command line data
162 * have to be in the first 8 MB of memory, since this is
163 * the maximum mapped by the Linux kernel during initialization.
164 */
165#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
166/*-----------------------------------------------------------------------
167 * FLASH organization
168 */
169#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
170#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
171
172#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
173#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
174
175/* BEG ENVIRONNEMENT FLASH */
176#ifdef CFG_ENV_IS_IN_FLASH
177#define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */
178#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
179#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
180#endif
181/* END ENVIRONNEMENT FLASH */
182/*-----------------------------------------------------------------------
183 * NVRAM organization
184 */
185#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
186#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
187
188#ifdef CFG_ENV_IS_IN_NVRAM
189#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
190#define CFG_ENV_ADDR \
191 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
192#endif
193/*-----------------------------------------------------------------------
194 * Cache Configuration
195 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200196#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
wdenkfe8c2802002-11-03 00:38:21 +0000197#define CFG_CACHELINE_SIZE 32 /* ... */
198#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
199#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
200#endif
201
202/*
203 * Init Memory Controller:
204 *
205 * BR0/1 and OR0/1 (FLASH)
206 */
207
208#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
209#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
210
211
212/* Configuration Port location */
213#define CONFIG_PORT_ADDR 0xF0000500
214
215/*-----------------------------------------------------------------------
216 * Definitions for initial stack pointer and data area (in DPRAM)
217 */
218
219#define CFG_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */
220#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
221#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
222#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
223#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
224
225/*-----------------------------------------------------------------------
226 * Definitions for Serial Presence Detect EEPROM address
227 * (to get SDRAM settings)
228 */
229#define SPD_EEPROM_ADDRESS 0x50
230
231/*
232 * Internal Definitions
233 *
234 * Boot Flags
235 */
236#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
237#define BOOTFLAG_WARM 0x02 /* Software reboot */
238
239#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
240#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
241#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
242#endif
243
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200244/*
245 * JFFS2 partitions
246 *
247 */
248/* No command line, one static partition, whole device */
249#undef CONFIG_JFFS2_CMDLINE
250#define CONFIG_JFFS2_DEV "nor0"
251#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
252#define CONFIG_JFFS2_PART_OFFSET 0x00080000
wdenkfe8c2802002-11-03 00:38:21 +0000253
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200254/* mtdparts command line support */
255/* Note: fake mtd_id used, no linux mtd map file */
256/*
257#define CONFIG_JFFS2_CMDLINE
258#define MTDIDS_DEFAULT "nor0=ml2-0"
259#define MTDPARTS_DEFAULT "mtdparts=ml2-0:-@512k(jffs2)"
260*/
261
wdenkfe8c2802002-11-03 00:38:21 +0000262#endif /* __CONFIG_H */