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wdenk5b1d7132002-11-03 00:07:02 +00001/*
2 * (C) Copyright 2000, 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
29 * U-Boot port on RPXlite board
30 */
31
32#ifndef __CONFIG_H
33#define __CONFIG_H
34
35#define RPXClassic_50MHz
36
37/*
38 * High Level Configuration Options
39 * (easy to change)
40 */
41
42#define CONFIG_MPC860 1
43#define CONFIG_RPXCLASSIC 1
44
45#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
46#undef CONFIG_8xx_CONS_SMC2
47#undef CONFIG_8xx_CONS_NONE
48#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
49
wdenk5b1d7132002-11-03 00:07:02 +000050/* Define CONFIG_FEC_ENET to use Fast ethernet instead of ethernet on SCC1 */
wdenka6c7ad22002-12-03 21:28:10 +000051#define CONFIG_FEC_ENET
wdenk5b1d7132002-11-03 00:07:02 +000052#ifdef CONFIG_FEC_ENET
53#define CFG_DISCOVER_PHY 1
wdenka6c7ad22002-12-03 21:28:10 +000054#define CONFIG_MII 1
wdenk5b1d7132002-11-03 00:07:02 +000055#endif /* CONFIG_FEC_ENET */
56
wdenka6c7ad22002-12-03 21:28:10 +000057/* Video console (graphic: Epson SED13806 on ECCX board, no keyboard */
58#if 1
59#define CONFIG_VIDEO_SED13806
60#define CONFIG_NEC_NL6448BC20
61#define CONFIG_VIDEO_SED13806_16BPP
62
63#define CONFIG_CFB_CONSOLE
64#define CONFIG_VIDEO_LOGO
65#define CONFIG_VIDEO_BMP_LOGO
66#define CONFIG_CONSOLE_EXTRA_INFO
67#define CONFIG_VGA_AS_SINGLE_DEVICE
68#define CONFIG_VIDEO_SW_CURSOR
69#endif
70
wdenk5b1d7132002-11-03 00:07:02 +000071#if 0
72#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
73#else
74#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
75#endif
76
77#define CONFIG_ZERO_BOOTDELAY_CHECK 1
78
79#undef CONFIG_BOOTARGS
80#define CONFIG_BOOTCOMMAND \
81 "tftpboot; " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010082 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
83 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk5b1d7132002-11-03 00:07:02 +000084 "bootm"
85
86#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
87#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
88
89#undef CONFIG_WATCHDOG /* watchdog disabled */
90
91#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
92
93#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
94
95
wdenk48abe7b2004-06-09 10:15:00 +000096#define CONFIG_COMMANDS ((CFG_CMD_ALL & ~CFG_CMD_NONSTD) | CFG_CMD_ELF)
wdenk5b1d7132002-11-03 00:07:02 +000097
98/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
99#include <cmd_confdefs.h>
100
101/*
102 * Miscellaneous configurable options
103 */
104#define CFG_RESET_ADDRESS 0x80000000
105#define CFG_LONGHELP /* undef to save memory */
106#define CFG_PROMPT "=> " /* Monitor Command Prompt */
107#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
108#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
109#else
110#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
111#endif
112#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
113#define CFG_MAXARGS 16 /* max number of command args */
114#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
115
116#define CFG_MEMTEST_START 0x0040000 /* memtest works on */
117#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
118
119#define CFG_LOAD_ADDR 0x100000 /* default load address */
120
121#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
122
123#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
124
125/*
126 * Low Level Configuration Settings
127 * (address mappings, register initial values, etc.)
128 * You should know what you are doing if you make changes here.
129 */
130/*-----------------------------------------------------------------------
131 * Internal Memory Mapped Register
132 */
133#define CFG_IMMR 0xFA200000
134
135/*-----------------------------------------------------------------------------
136 * I2C Configuration
137 *-----------------------------------------------------------------------------
138 */
139#define CONFIG_I2C 1
140#define CFG_I2C_SPEED 50000
141#define CFG_I2C_SLAVE 0x34
142
143
144/* enable I2C and select the hardware/software driver */
145#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
146#undef CONFIG_SOFT_I2C /* I2C bit-banged */
147/*
148 * Software (bit-bang) I2C driver configuration
149 */
150#define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */
151#define I2C_ACTIVE (iop->pdir |= 0x00000010)
152#define I2C_TRISTATE (iop->pdir &= ~0x00000010)
153#define I2C_READ ((iop->pdat & 0x00000010) != 0)
154#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \
155 else iop->pdat &= ~0x00000010
156#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \
157 else iop->pdat &= ~0x00000020
158#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
159
160
161# define CFG_I2C_SPEED 50000
162# define CFG_I2C_SLAVE 0x34
163# define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */
164# define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
165/* mask of address bits that overflow into the "EEPROM chip address" */
166#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
167
168/*-----------------------------------------------------------------------
169 * Definitions for initial stack pointer and data area (in DPRAM)
170 */
171#define CFG_INIT_RAM_ADDR CFG_IMMR
172#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
173#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
174#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
175#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
176
177/*-----------------------------------------------------------------------
178 * Start addresses for the final memory configuration
179 * (Set up by the startup code)
180 * Please note that CFG_SDRAM_BASE _must_ start at 0
181 */
182#define CFG_SDRAM_BASE 0x00000000
183#define CFG_FLASH_BASE 0xFF000000
184
wdenk8bde7f72003-06-27 21:31:46 +0000185#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || (CONFIG_COMMANDS & CFG_CMD_IDE)
wdenk5b1d7132002-11-03 00:07:02 +0000186#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
187#else
188#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
189#endif
190#define CFG_MONITOR_BASE 0xFF000000
191/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */
192#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
193
194/*
195 * For booting Linux, the board info and command line data
196 * have to be in the first 8 MB of memory, since this is
197 * the maximum mapped by the Linux kernel during initialization.
198 */
199#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
200
201/*-----------------------------------------------------------------------
202 * FLASH organization
203 */
204#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
205#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
206
207#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
208#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
209
210#if 0
211#define CFG_ENV_IS_IN_FLASH 1
212#define CFG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */
wdenka6c7ad22002-12-03 21:28:10 +0000213#define CFG_ENV_SECT_SIZE 0x8000
214#define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
wdenk5b1d7132002-11-03 00:07:02 +0000215#else
216#define CFG_ENV_IS_IN_NVRAM 1
217#define CFG_ENV_ADDR 0xfa000100
218#define CFG_ENV_SIZE 0x1000
219#endif
220
221/*-----------------------------------------------------------------------
222 * Cache Configuration
223 */
224#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
225#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
226#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
227#endif
228
229/*-----------------------------------------------------------------------
230 * SYPCR - System Protection Control 11-9
231 * SYPCR can only be written once after reset!
232 *-----------------------------------------------------------------------
233 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
234 */
235#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
236 SYPCR_SWP)
237
238/*-----------------------------------------------------------------------
239 * SIUMCR - SIU Module Configuration 11-6
240 *-----------------------------------------------------------------------
241 * PCMCIA config., multi-function pin tri-state
242 */
243#define CFG_SIUMCR (SIUMCR_MLRC10)
244
245/*-----------------------------------------------------------------------
246 * TBSCR - Time Base Status and Control 11-26
247 *-----------------------------------------------------------------------
248 * Clear Reference Interrupt Status, Timebase freezing enabled
249 */
250#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
251
252/*-----------------------------------------------------------------------
253 * RTCSC - Real-Time Clock Status and Control Register 11-27
254 *-----------------------------------------------------------------------
255 */
256/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
257#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE)
258
259/*-----------------------------------------------------------------------
260 * PISCR - Periodic Interrupt Status and Control 11-31
261 *-----------------------------------------------------------------------
262 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
263 */
264#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
265
266/*-----------------------------------------------------------------------
267 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
268 *-----------------------------------------------------------------------
269 * Reset PLL lock status sticky bit, timer expired status bit and timer
270 * interrupt status bit
271 *
272 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
273 */
274/* up to 50 MHz we use a 1:1 clock */
275#define CFG_PLPRCR ( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST)
276
277/*-----------------------------------------------------------------------
278 * SCCR - System Clock and reset Control Register 15-27
279 *-----------------------------------------------------------------------
280 * Set clock output, timebase and RTC source and divider,
281 * power management and some other internal clocks
282 */
283#define SCCR_MASK SCCR_EBDF00
284/* up to 50 MHz we use a 1:1 clock */
285#define CFG_SCCR (SCCR_COM00 | SCCR_TBS)
286
287/*-----------------------------------------------------------------------
288 * PCMCIA stuff
289 *-----------------------------------------------------------------------
290 *
291 */
292#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
293#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
294#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
295#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
296#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
297#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
298#define CFG_PCMCIA_IO_ADDR (0xEC000000)
299#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
300
301/*-----------------------------------------------------------------------
302 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
303 *-----------------------------------------------------------------------
304 */
305
306#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
307
308#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
309#undef CONFIG_IDE_LED /* LED for ide not supported */
310#undef CONFIG_IDE_RESET /* reset for ide not supported */
311
312#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
313#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
314
315#define CFG_ATA_IDE0_OFFSET 0x0000
316
317#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
318
319/* Offset for data I/O */
320#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
321
322/* Offset for normal register accesses */
323#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
324
325/* Offset for alternate registers */
326#define CFG_ATA_ALT_OFFSET 0x0100
327
328/*-----------------------------------------------------------------------
329 *
330 *-----------------------------------------------------------------------
331 *
332 */
333/* #define CFG_DER 0x2002000F */
wdenk2535d602003-07-17 23:16:40 +0000334#define CFG_DER 0
wdenk5b1d7132002-11-03 00:07:02 +0000335
336/*
337 * Init Memory Controller:
338 *
339 * BR0 and OR0 (FLASH)
340 */
341
342#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
343#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
344
345/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
346#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
347
348#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
349#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
350
351/*
352 * BR1 and OR1 (SDRAM)
353 *
354 */
355#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
356#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
357
358/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
359#define CFG_OR_TIMING_SDRAM 0x00000E00
360
361#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
362#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
363
364/* RPXLITE mem setting */
365#define CFG_BR3_PRELIM 0xFA400001 /* BCSR */
366#define CFG_OR3_PRELIM 0xff7f8970
367#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
368#define CFG_OR4_PRELIM 0xFFF80970
369
wdenka6c7ad22002-12-03 21:28:10 +0000370/* ECCX CS settings */
371#define SED13806_OR 0xFFC00108 /* - 4 Mo
wdenk8bde7f72003-06-27 21:31:46 +0000372 - Burst inhibit
373 - external TA */
wdenka6c7ad22002-12-03 21:28:10 +0000374#define SED13806_REG_ADDR 0xa0000000
375#define SED13806_ACCES 0x801 /* 16 bit access */
376
377
378/* Global definitions for the ECCX board */
379#define ECCX_CSR_ADDR (0xfac00000)
380#define ECCX_CSR8_OFFSET (0x8)
381#define ECCX_CSR11_OFFSET (0xB)
382#define ECCX_CSR12_OFFSET (0xC)
383
384#define ECCX_CSR8 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR8_OFFSET)
385#define ECCX_CSR11 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR11_OFFSET)
386#define ECCX_CSR12 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR12_OFFSET)
387
388
389#define REG_GPIO_CTRL 0x008
390
391/* Definitions for CSR8 */
392#define ECCX_ENEPSON 0x80 /* Bit 0:
wdenk8bde7f72003-06-27 21:31:46 +0000393 0= disable and reset SED1386
394 1= enable SED1386 */
wdenka6c7ad22002-12-03 21:28:10 +0000395/* Bit 1: 0= SED1386 in Big Endian mode */
396/* 1= SED1386 in little endian mode */
397#define ECCX_LE 0x40
398#define ECCX_BE 0x00
399
400/* Bit 2,3: Selection */
401/* 00 = Disabled */
402/* 01 = CS2 is used for the SED1386 */
403/* 10 = CS5 is used for the SED1386 */
404/* 11 = reserved */
405#define ECCX_CS2 0x10
406#define ECCX_CS5 0x20
407
408/* Definitions for CSR12 */
409#define ECCX_ID 0x02
410#define ECCX_860 0x01
411
wdenk5b1d7132002-11-03 00:07:02 +0000412/*
413 * Memory Periodic Timer Prescaler
414 */
415
416/* periodic timer for refresh */
417#define CFG_MAMR_PTA 58
418
419/*
420 * Refresh clock Prescalar
421 */
422#define CFG_MPTPR MPTPR_PTP_DIV8
423
424/*
425 * MAMR settings for SDRAM
426 */
427
428/* 10 column SDRAM */
429#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
430 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
431 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
432
433/*
434 * Internal Definitions
435 *
436 * Boot Flags
437 */
438#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
439#define BOOTFLAG_WARM 0x02 /* Software reboot */
440
441
442/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
443/* Configuration variable added by yooth. */
444/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
445
446/*
447 * BCSRx
448 *
449 * Board Status and Control Registers
450 *
451 */
452
453#define BCSR0 0xFA400000
454#define BCSR1 0xFA400001
455#define BCSR2 0xFA400002
456#define BCSR3 0xFA400003
457
458#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
459#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
460#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
461#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
462#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
463#define BCSR0_COLTEST 0x20
464#define BCSR0_ETHLPBK 0x40
465#define BCSR0_ETHEN 0x80
466
467#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
468#define BCSR1_PCVCTL6 0x02
469#define BCSR1_PCVCTL5 0x04
470#define BCSR1_PCVCTL4 0x08
471#define BCSR1_IPB5SEL 0x10
472
473#define BCSR2_MIIRST 0x80
474#define BCSR2_MIIPWRDWN 0x40
475#define BCSR2_MIICTL 0x08
476
477#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
478#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
479#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
480#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
481#define BCSR3_D27 0x10 /* Dip Switch settings */
482#define BCSR3_D26 0x20
483#define BCSR3_D25 0x40
484#define BCSR3_D24 0x80
485
486
487/*
488 * Environment setting
489 */
490
491/* #define CONFIG_ETHADDR 00:10:EC:00:2C:A2 */
492/* #define CONFIG_IPADDR 10.10.106.1 */
493/* #define CONFIG_SERVERIP 10.10.104.11 */
494
495#endif /* __CONFIG_H */