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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
2 * (C) Copyright 2000, 2001
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00006 */
7
8/*
9 * FPGA support
10 */
11#include <common.h>
12#include <command.h>
wdenk8bde7f72003-06-27 21:31:46 +000013#include <fpga.h>
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053014#include <fs.h>
wdenkc3d2b4b2005-01-22 18:13:04 +000015#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000016
wdenk4a9cbbe2002-08-27 09:48:53 +000017/* Local functions */
Michal Simekfc598412013-04-26 13:10:07 +020018static int fpga_get_op(char *opstr);
wdenk4a9cbbe2002-08-27 09:48:53 +000019
20/* Local defines */
Michal Simek5cf22282017-01-06 11:20:54 +010021enum {
22 FPGA_NONE = -1,
23 FPGA_INFO,
24 FPGA_LOAD,
25 FPGA_LOADB,
26 FPGA_DUMP,
27 FPGA_LOADMK,
28 FPGA_LOADP,
29 FPGA_LOADBP,
30 FPGA_LOADFS,
31};
wdenk4a9cbbe2002-08-27 09:48:53 +000032
33/* ------------------------------------------------------------------------- */
34/* command form:
35 * fpga <op> <device number> <data addr> <datasize>
36 * where op is 'load', 'dump', or 'info'
37 * If there is no device number field, the fpga environment variable is used.
38 * If there is no data addr field, the fpgadata environment variable is used.
39 * The info command requires no data address field.
40 */
Michal Simekfc598412013-04-26 13:10:07 +020041int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +000042{
wdenkd4ca31c2004-01-02 14:00:00 +000043 int op, dev = FPGA_INVALID_DEVICE;
44 size_t data_size = 0;
45 void *fpga_data = NULL;
Simon Glass00caae62017-08-03 12:22:12 -060046 char *devstr = env_get("fpga");
47 char *datastr = env_get("fpgadata");
wdenkd4ca31c2004-01-02 14:00:00 +000048 int rc = FPGA_FAIL;
Stefano Babica790b5b2010-10-19 09:22:52 +020049 int wrong_parms = 0;
Michal Simekfc598412013-04-26 13:10:07 +020050#if defined(CONFIG_FIT)
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010051 const char *fit_uname = NULL;
52 ulong fit_addr;
53#endif
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053054#if defined(CONFIG_CMD_FPGA_LOADFS)
55 fpga_fs_info fpga_fsinfo;
56 fpga_fsinfo.fstype = FS_TYPE_ANY;
57#endif
wdenk4a9cbbe2002-08-27 09:48:53 +000058
wdenkd4ca31c2004-01-02 14:00:00 +000059 if (devstr)
Michal Simekfc598412013-04-26 13:10:07 +020060 dev = (int) simple_strtoul(devstr, NULL, 16);
wdenkd4ca31c2004-01-02 14:00:00 +000061 if (datastr)
Michal Simekfc598412013-04-26 13:10:07 +020062 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
wdenk4a9cbbe2002-08-27 09:48:53 +000063
wdenkd4ca31c2004-01-02 14:00:00 +000064 switch (argc) {
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053065#if defined(CONFIG_CMD_FPGA_LOADFS)
66 case 9:
67 fpga_fsinfo.blocksize = (unsigned int)
68 simple_strtoul(argv[5], NULL, 16);
69 fpga_fsinfo.interface = argv[6];
70 fpga_fsinfo.dev_part = argv[7];
71 fpga_fsinfo.filename = argv[8];
72#endif
wdenkd4ca31c2004-01-02 14:00:00 +000073 case 5: /* fpga <op> <dev> <data> <datasize> */
Michal Simekfc598412013-04-26 13:10:07 +020074 data_size = simple_strtoul(argv[4], NULL, 16);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010075
wdenkd4ca31c2004-01-02 14:00:00 +000076 case 4: /* fpga <op> <dev> <data> */
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010077#if defined(CONFIG_FIT)
Michal Simekfc598412013-04-26 13:10:07 +020078 if (fit_parse_subimage(argv[3], (ulong)fpga_data,
79 &fit_addr, &fit_uname)) {
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010080 fpga_data = (void *)fit_addr;
Michal Simekfc598412013-04-26 13:10:07 +020081 debug("* fpga: subimage '%s' from FIT image ",
82 fit_uname);
83 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010084 } else
85#endif
86 {
Michal Simekfc598412013-04-26 13:10:07 +020087 fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
Stefano Babic06297db2011-12-28 06:47:01 +000088 debug("* fpga: cmdline image address = 0x%08lx\n",
Michal Simekfc598412013-04-26 13:10:07 +020089 (ulong)fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010090 }
Michal Simek455ad582016-01-05 13:51:48 +010091 debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010092
wdenkd4ca31c2004-01-02 14:00:00 +000093 case 3: /* fpga <op> <dev | data addr> */
Michal Simekfc598412013-04-26 13:10:07 +020094 dev = (int)simple_strtoul(argv[2], NULL, 16);
Stefano Babic06297db2011-12-28 06:47:01 +000095 debug("%s: device = %d\n", __func__, dev);
wdenkd4ca31c2004-01-02 14:00:00 +000096 /* FIXME - this is a really weak test */
Michal Simekfc598412013-04-26 13:10:07 +020097 if ((argc == 3) && (dev > fpga_count())) {
98 /* must be buffer ptr */
Stefano Babic06297db2011-12-28 06:47:01 +000099 debug("%s: Assuming buffer pointer in arg 3\n",
Michal Simekfc598412013-04-26 13:10:07 +0200100 __func__);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100101
102#if defined(CONFIG_FIT)
Michal Simekfc598412013-04-26 13:10:07 +0200103 if (fit_parse_subimage(argv[2], (ulong)fpga_data,
104 &fit_addr, &fit_uname)) {
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100105 fpga_data = (void *)fit_addr;
Michal Simekfc598412013-04-26 13:10:07 +0200106 debug("* fpga: subimage '%s' from FIT image ",
107 fit_uname);
108 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100109 } else
110#endif
111 {
Michal Simek455ad582016-01-05 13:51:48 +0100112 fpga_data = (void *)(uintptr_t)dev;
Michal Simekfc598412013-04-26 13:10:07 +0200113 debug("* fpga: cmdline image addr = 0x%08lx\n",
114 (ulong)fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100115 }
116
Michal Simek455ad582016-01-05 13:51:48 +0100117 debug("%s: fpga_data = 0x%lx\n",
118 __func__, (ulong)fpga_data);
wdenkd4ca31c2004-01-02 14:00:00 +0000119 dev = FPGA_INVALID_DEVICE; /* reset device num */
120 }
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100121
wdenkd4ca31c2004-01-02 14:00:00 +0000122 case 2: /* fpga <op> */
Michal Simekfc598412013-04-26 13:10:07 +0200123 op = (int)fpga_get_op(argv[1]);
wdenkd4ca31c2004-01-02 14:00:00 +0000124 break;
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100125
wdenkd4ca31c2004-01-02 14:00:00 +0000126 default:
Michal Simekfc598412013-04-26 13:10:07 +0200127 debug("%s: Too many or too few args (%d)\n", __func__, argc);
wdenkd4ca31c2004-01-02 14:00:00 +0000128 op = FPGA_NONE; /* force usage display */
129 break;
130 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000131
Stefano Babica790b5b2010-10-19 09:22:52 +0200132 if (dev == FPGA_INVALID_DEVICE) {
133 puts("FPGA device not specified\n");
134 op = FPGA_NONE;
135 }
136
137 switch (op) {
138 case FPGA_NONE:
139 case FPGA_INFO:
140 break;
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530141#if defined(CONFIG_CMD_FPGA_LOADFS)
142 case FPGA_LOADFS:
143 /* Blocksize can be zero */
144 if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part ||
145 !fpga_fsinfo.filename)
146 wrong_parms = 1;
147#endif
Stefano Babica790b5b2010-10-19 09:22:52 +0200148 case FPGA_LOAD:
Michal Simek67193862014-05-02 13:43:39 +0200149 case FPGA_LOADP:
Stefano Babica790b5b2010-10-19 09:22:52 +0200150 case FPGA_LOADB:
Michal Simek67193862014-05-02 13:43:39 +0200151 case FPGA_LOADBP:
Stefano Babica790b5b2010-10-19 09:22:52 +0200152 case FPGA_DUMP:
153 if (!fpga_data || !data_size)
154 wrong_parms = 1;
155 break;
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530156#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefano Babica790b5b2010-10-19 09:22:52 +0200157 case FPGA_LOADMK:
158 if (!fpga_data)
159 wrong_parms = 1;
160 break;
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530161#endif
Stefano Babica790b5b2010-10-19 09:22:52 +0200162 }
163
164 if (wrong_parms) {
165 puts("Wrong parameters for FPGA request\n");
166 op = FPGA_NONE;
167 }
168
wdenkd4ca31c2004-01-02 14:00:00 +0000169 switch (op) {
170 case FPGA_NONE:
Simon Glass4c12eeb2011-12-10 08:44:01 +0000171 return CMD_RET_USAGE;
wdenk4a9cbbe2002-08-27 09:48:53 +0000172
wdenkd4ca31c2004-01-02 14:00:00 +0000173 case FPGA_INFO:
Michal Simekfc598412013-04-26 13:10:07 +0200174 rc = fpga_info(dev);
wdenkd4ca31c2004-01-02 14:00:00 +0000175 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000176
wdenkd4ca31c2004-01-02 14:00:00 +0000177 case FPGA_LOAD:
Michal Simek7a78bd22014-05-02 14:09:30 +0200178 rc = fpga_load(dev, fpga_data, data_size, BIT_FULL);
wdenkd4ca31c2004-01-02 14:00:00 +0000179 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000180
Michal Simek67193862014-05-02 13:43:39 +0200181#if defined(CONFIG_CMD_FPGA_LOADP)
182 case FPGA_LOADP:
183 rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL);
184 break;
185#endif
186
wdenk30ce5ab2005-01-09 18:12:51 +0000187 case FPGA_LOADB:
Michal Simek7a78bd22014-05-02 14:09:30 +0200188 rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL);
wdenk30ce5ab2005-01-09 18:12:51 +0000189 break;
190
Michal Simek67193862014-05-02 13:43:39 +0200191#if defined(CONFIG_CMD_FPGA_LOADBP)
192 case FPGA_LOADBP:
193 rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL);
194 break;
195#endif
196
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530197#if defined(CONFIG_CMD_FPGA_LOADFS)
198 case FPGA_LOADFS:
199 rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo);
200 break;
201#endif
202
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530203#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefan Roesef0ff4692006-08-15 14:15:51 +0200204 case FPGA_LOADMK:
Michal Simekfc598412013-04-26 13:10:07 +0200205 switch (genimg_get_format(fpga_data)) {
Heiko Schocher21d29f72014-05-28 11:33:33 +0200206#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100207 case IMAGE_FORMAT_LEGACY:
208 {
Michal Simekfc598412013-04-26 13:10:07 +0200209 image_header_t *hdr =
210 (image_header_t *)fpga_data;
211 ulong data;
Michal Simek32d7cdd2013-10-04 10:51:01 +0200212 uint8_t comp;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200213
Michal Simek32d7cdd2013-10-04 10:51:01 +0200214 comp = image_get_comp(hdr);
215 if (comp == IH_COMP_GZIP) {
Michal Simek1b63aaa2014-07-16 10:30:50 +0200216#if defined(CONFIG_GZIP)
Michal Simek32d7cdd2013-10-04 10:51:01 +0200217 ulong image_buf = image_get_data(hdr);
218 data = image_get_load(hdr);
219 ulong image_size = ~0UL;
220
221 if (gunzip((void *)data, ~0UL,
222 (void *)image_buf,
223 &image_size) != 0) {
224 puts("GUNZIP: error\n");
225 return 1;
226 }
227 data_size = image_size;
Michal Simek1b63aaa2014-07-16 10:30:50 +0200228#else
229 puts("Gunzip image is not supported\n");
230 return 1;
231#endif
Michal Simek32d7cdd2013-10-04 10:51:01 +0200232 } else {
233 data = (ulong)image_get_data(hdr);
234 data_size = image_get_data_size(hdr);
235 }
Michal Simek7a78bd22014-05-02 14:09:30 +0200236 rc = fpga_load(dev, (void *)data, data_size,
237 BIT_FULL);
Stefan Roesef0ff4692006-08-15 14:15:51 +0200238 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100239 break;
Heiko Schocher21d29f72014-05-28 11:33:33 +0200240#endif
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100241#if defined(CONFIG_FIT)
242 case IMAGE_FORMAT_FIT:
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100243 {
244 const void *fit_hdr = (const void *)fpga_data;
245 int noffset;
Wolfgang Denke6a857d2011-07-30 13:33:49 +0000246 const void *fit_data;
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100247
248 if (fit_uname == NULL) {
Michal Simekfc598412013-04-26 13:10:07 +0200249 puts("No FIT subimage unit name\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100250 return 1;
251 }
252
Michal Simekfc598412013-04-26 13:10:07 +0200253 if (!fit_check_format(fit_hdr)) {
254 puts("Bad FIT image format\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100255 return 1;
256 }
257
258 /* get fpga component image node offset */
Michal Simekfc598412013-04-26 13:10:07 +0200259 noffset = fit_image_get_node(fit_hdr,
260 fit_uname);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100261 if (noffset < 0) {
Michal Simekfc598412013-04-26 13:10:07 +0200262 printf("Can't find '%s' FIT subimage\n",
263 fit_uname);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100264 return 1;
265 }
266
267 /* verify integrity */
Simon Glassb8da8362013-05-07 06:11:57 +0000268 if (!fit_image_verify(fit_hdr, noffset)) {
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100269 puts ("Bad Data Hash\n");
270 return 1;
271 }
272
273 /* get fpga subimage data address and length */
Michal Simekfc598412013-04-26 13:10:07 +0200274 if (fit_image_get_data(fit_hdr, noffset,
275 &fit_data, &data_size)) {
276 puts("Fpga subimage data not found\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100277 return 1;
278 }
279
Michal Simek7a78bd22014-05-02 14:09:30 +0200280 rc = fpga_load(dev, fit_data, data_size,
281 BIT_FULL);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100282 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100283 break;
284#endif
285 default:
Michal Simekfc598412013-04-26 13:10:07 +0200286 puts("** Unknown image type\n");
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100287 rc = FPGA_FAIL;
288 break;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200289 }
290 break;
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530291#endif
Stefan Roesef0ff4692006-08-15 14:15:51 +0200292
wdenkd4ca31c2004-01-02 14:00:00 +0000293 case FPGA_DUMP:
Michal Simekfc598412013-04-26 13:10:07 +0200294 rc = fpga_dump(dev, fpga_data, data_size);
wdenkd4ca31c2004-01-02 14:00:00 +0000295 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000296
wdenkd4ca31c2004-01-02 14:00:00 +0000297 default:
Michal Simekfc598412013-04-26 13:10:07 +0200298 printf("Unknown operation\n");
Simon Glass4c12eeb2011-12-10 08:44:01 +0000299 return CMD_RET_USAGE;
wdenkd4ca31c2004-01-02 14:00:00 +0000300 }
Michal Simekfc598412013-04-26 13:10:07 +0200301 return rc;
wdenk4a9cbbe2002-08-27 09:48:53 +0000302}
303
wdenk4a9cbbe2002-08-27 09:48:53 +0000304/*
305 * Map op to supported operations. We don't use a table since we
306 * would just have to relocate it from flash anyway.
307 */
Michal Simekfc598412013-04-26 13:10:07 +0200308static int fpga_get_op(char *opstr)
wdenk4a9cbbe2002-08-27 09:48:53 +0000309{
310 int op = FPGA_NONE;
311
Michal Simekfc598412013-04-26 13:10:07 +0200312 if (!strcmp("info", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000313 op = FPGA_INFO;
Michal Simekfc598412013-04-26 13:10:07 +0200314 else if (!strcmp("loadb", opstr))
wdenk30ce5ab2005-01-09 18:12:51 +0000315 op = FPGA_LOADB;
Michal Simekfc598412013-04-26 13:10:07 +0200316 else if (!strcmp("load", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000317 op = FPGA_LOAD;
Michal Simek67193862014-05-02 13:43:39 +0200318#if defined(CONFIG_CMD_FPGA_LOADP)
319 else if (!strcmp("loadp", opstr))
320 op = FPGA_LOADP;
321#endif
322#if defined(CONFIG_CMD_FPGA_LOADBP)
323 else if (!strcmp("loadbp", opstr))
324 op = FPGA_LOADBP;
325#endif
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530326#if defined(CONFIG_CMD_FPGA_LOADFS)
327 else if (!strcmp("loadfs", opstr))
328 op = FPGA_LOADFS;
329#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530330#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simekfc598412013-04-26 13:10:07 +0200331 else if (!strcmp("loadmk", opstr))
Stefan Roesef0ff4692006-08-15 14:15:51 +0200332 op = FPGA_LOADMK;
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530333#endif
Michal Simekfc598412013-04-26 13:10:07 +0200334 else if (!strcmp("dump", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000335 op = FPGA_DUMP;
wdenk4a9cbbe2002-08-27 09:48:53 +0000336
Michal Simekfc598412013-04-26 13:10:07 +0200337 if (op == FPGA_NONE)
338 printf("Unknown fpga operation \"%s\"\n", opstr);
339
wdenk4a9cbbe2002-08-27 09:48:53 +0000340 return op;
341}
342
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530343#if defined(CONFIG_CMD_FPGA_LOADFS)
344U_BOOT_CMD(fpga, 9, 1, do_fpga,
345#else
Michal Simekfc598412013-04-26 13:10:07 +0200346U_BOOT_CMD(fpga, 6, 1, do_fpga,
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530347#endif
Michal Simekfc598412013-04-26 13:10:07 +0200348 "loadable FPGA image support",
349 "[operation type] [device number] [image address] [image size]\n"
350 "fpga operations:\n"
Michal Simek2d73f0d2015-01-26 08:52:27 +0100351 " dump\t[dev] [address] [size]\tLoad device to memory buffer\n"
Michal Simekfc598412013-04-26 13:10:07 +0200352 " info\t[dev]\t\t\tlist known device information\n"
353 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
Michal Simek67193862014-05-02 13:43:39 +0200354#if defined(CONFIG_CMD_FPGA_LOADP)
355 " loadp\t[dev] [address] [size]\t"
356 "Load device from memory buffer with partial bitstream\n"
357#endif
Michal Simekfc598412013-04-26 13:10:07 +0200358 " loadb\t[dev] [address] [size]\t"
359 "Load device from bitstream buffer (Xilinx only)\n"
Michal Simek67193862014-05-02 13:43:39 +0200360#if defined(CONFIG_CMD_FPGA_LOADBP)
361 " loadbp\t[dev] [address] [size]\t"
362 "Load device from bitstream buffer with partial bitstream"
363 "(Xilinx only)\n"
364#endif
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530365#if defined(CONFIG_CMD_FPGA_LOADFS)
366 "Load device from filesystem (FAT by default) (Xilinx only)\n"
367 " loadfs [dev] [address] [image size] [blocksize] <interface>\n"
368 " [<dev[:part]>] <filename>\n"
369#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530370#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simekfc598412013-04-26 13:10:07 +0200371 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100372#if defined(CONFIG_FIT)
Michal Simekfc598412013-04-26 13:10:07 +0200373 "\n"
374 "\tFor loadmk operating on FIT format uImage address must include\n"
375 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100376#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530377#endif
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100378);