blob: 84187fbb4d7c77c8d97fe404cf33012523631647 [file] [log] [blame]
wdenk0f8c9762002-08-19 11:57:05 +00001 /*
2 * A collection of structures, addresses, and values associated with
3 * the Motorola 860T FADS board. Copied from the MBX stuff.
4 * Magnus Damm added defines for 8xxrom and extended bd_info.
5 * Helmut Buchsbaum added bitvalues for BCSRx
6 *
7 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
8 */
9
10/*
11 * 1999-nov-26: The FADS is using the following physical memorymap:
12 *
13 * ff020000 -> ff02ffff : pcmcia
14 * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxrom
15 * ff000000 -> ff00ffff : IMAP internal in the cpu
16 * fe000000 -> ffnnnnnn : flash connected to CS0, setup by 8xxrom
17 * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
18 */
19
20/* ------------------------------------------------------------------------- */
21
22/*
23 * board/config.h - configuration options, board specific
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
30 * High Level Configuration Options
31 * (easy to change)
32 */
wdenk0f8c9762002-08-19 11:57:05 +000033#define CONFIG_MPC850 1
34#define CONFIG_MPC850SAR 1
35#define CONFIG_FADS 1
36
37#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
38#undef CONFIG_8xx_CONS_SMC2
39#undef CONFIG_8xx_CONS_NONE
40#define CONFIG_BAUDRATE 9600
41
42#if 0
43#define MPC8XX_FACT 10 /* Multiply by 10 */
44#define MPC8XX_XIN 50000000 /* 50 MHz in */
45#else
46#define MPC8XX_FACT 12 /* Multiply by 12 */
47#define MPC8XX_XIN 4000000 /* 4 MHz in */
48#endif
49#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
50
51#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
52
53#if 1
54#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
55#else
56#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
57#endif
58
59#define CONFIG_BOOTCOMMAND "bootm 02880000" /* autoboot command */
60#define CONFIG_BOOTARGS " "
61
62#undef CONFIG_WATCHDOG /* watchdog disabled */
63
Jon Loeliger60a08762007-07-07 21:04:26 -050064
65/*
Jon Loeliger11799432007-07-10 09:02:57 -050066 * BOOTP options
67 */
68#define CONFIG_BOOTP_BOOTFILESIZE
69#define CONFIG_BOOTP_BOOTPATH
70#define CONFIG_BOOTP_GATEWAY
71#define CONFIG_BOOTP_HOSTNAME
72
73
74/*
Jon Loeliger60a08762007-07-07 21:04:26 -050075 * Command line configuration.
76 */
77#include <config_cmd_default.h>
78
wdenk0f8c9762002-08-19 11:57:05 +000079
80/*
81 * Miscellaneous configurable options
82 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#undef CONFIG_SYS_LONGHELP /* undef to save memory */
84#define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */
Jon Loeliger60a08762007-07-07 21:04:26 -050085#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +000087#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +000089#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
91#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
92#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +000093
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
95#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */
wdenk0f8c9762002-08-19 11:57:05 +000096
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
wdenk0f8c9762002-08-19 11:57:05 +000098
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk0f8c9762002-08-19 11:57:05 +0000100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk0f8c9762002-08-19 11:57:05 +0000102
103/*
104 * Low Level Configuration Settings
105 * (address mappings, register initial values, etc.)
106 * You should know what you are doing if you make changes here.
107 */
108/*-----------------------------------------------------------------------
109 * Internal Memory Mapped Register
110 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_IMMR 0xFF000000
112#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024))
wdenk0f8c9762002-08-19 11:57:05 +0000113
114/*-----------------------------------------------------------------------
115 * Definitions for initial stack pointer and data area (in DPRAM)
116 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
118#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
119#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
120#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
121#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk0f8c9762002-08-19 11:57:05 +0000122
123/*-----------------------------------------------------------------------
124 * Start addresses for the final memory configuration
125 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk0f8c9762002-08-19 11:57:05 +0000127 * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
128 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_SDRAM_BASE 0x00000000
130#define CONFIG_SYS_SDRAM_SIZE (4<<20) /* standard FADS has 4M */
131#define CONFIG_SYS_FLASH_BASE 0x02800000
132#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
wdenk0f8c9762002-08-19 11:57:05 +0000133#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */
wdenk0f8c9762002-08-19 11:57:05 +0000135#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
wdenk0f8c9762002-08-19 11:57:05 +0000137#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
139#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
wdenk0f8c9762002-08-19 11:57:05 +0000140
141/*
142 * For booting Linux, the board info and command line data
143 * have to be in the first 8 MB of memory, since this is
144 * the maximum mapped by the Linux kernel during initialization.
145 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk0f8c9762002-08-19 11:57:05 +0000147/*-----------------------------------------------------------------------
148 * FLASH organization
149 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
151#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
wdenk0f8c9762002-08-19 11:57:05 +0000152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
154#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk0f8c9762002-08-19 11:57:05 +0000155
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200156#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200157#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
158#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
wdenk0f8c9762002-08-19 11:57:05 +0000160
161/*-----------------------------------------------------------------------
162 * Cache Configuration
163 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger60a08762007-07-07 21:04:26 -0500165#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk0f8c9762002-08-19 11:57:05 +0000167#endif
168
169/*-----------------------------------------------------------------------
170 * SYPCR - System Protection Control 11-9
171 * SYPCR can only be written once after reset!
172 *-----------------------------------------------------------------------
173 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
174 */
175#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk0f8c9762002-08-19 11:57:05 +0000177 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
178#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk0f8c9762002-08-19 11:57:05 +0000180#endif
181
182/*-----------------------------------------------------------------------
183 * SIUMCR - SIU Module Configuration 11-6
184 *-----------------------------------------------------------------------
185 * PCMCIA config., multi-function pin tri-state
186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenk0f8c9762002-08-19 11:57:05 +0000188
189/*-----------------------------------------------------------------------
190 * TBSCR - Time Base Status and Control 11-26
191 *-----------------------------------------------------------------------
192 * Clear Reference Interrupt Status, Timebase freezing enabled
193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
wdenk0f8c9762002-08-19 11:57:05 +0000195
196/*-----------------------------------------------------------------------
197 * PISCR - Periodic Interrupt Status and Control 11-31
198 *-----------------------------------------------------------------------
199 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
200 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk0f8c9762002-08-19 11:57:05 +0000202
203/*-----------------------------------------------------------------------
204 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
205 *-----------------------------------------------------------------------
206 * Reset PLL lock status sticky bit, timer expired status bit and timer *
207 * interrupt status bit - leave PLL multiplication factor unchanged !
208 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << 20) | \
wdenk0f8c9762002-08-19 11:57:05 +0000210 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
211
212/*-----------------------------------------------------------------------
213 * SCCR - System Clock and reset Control Register 15-27
214 *-----------------------------------------------------------------------
215 * Set clock output, timebase and RTC source and divider,
216 * power management and some other internal clocks
217 */
218#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_SCCR (SCCR_TBS | \
wdenk0f8c9762002-08-19 11:57:05 +0000220 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
221 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
222 SCCR_DFALCD00)
223
224 /*-----------------------------------------------------------------------
225 *
226 *-----------------------------------------------------------------------
227 *
228 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_DER 0
wdenk0f8c9762002-08-19 11:57:05 +0000230
231/* Because of the way the 860 starts up and assigns CS0 the
232* entire address space, we have to set the memory controller
233* differently. Normally, you write the option register
234* first, and then enable the chip select by writing the
235* base register. For CS0, you must write the base register
236* first, followed by the option register.
237*/
238
239/*
240 * Init Memory Controller:
241 *
242 * BR0/1 and OR0/1 (FLASH)
243 */
244/* the other CS:s are determined by looking at parameters in BCSRx */
245
246
247#define BCSR_ADDR ((uint) 0x02100000)
248#define BCSR_SIZE ((uint)(64 * 1024))
249
250#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
251#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */
252
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
254#define CONFIG_SYS_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */
wdenk0f8c9762002-08-19 11:57:05 +0000255
256/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
wdenk0f8c9762002-08-19 11:57:05 +0000258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
260#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
261#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenk0f8c9762002-08-19 11:57:05 +0000262
263/* BCSRx - Board Control and Status Registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
265#define CONFIG_SYS_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
266#define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V )
wdenk0f8c9762002-08-19 11:57:05 +0000267
268
269/*
270 * Memory Periodic Timer Prescaler
271 */
272
273/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
wdenk0f8c9762002-08-19 11:57:05 +0000275
276/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
278#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenk0f8c9762002-08-19 11:57:05 +0000279
280/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
282#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk0f8c9762002-08-19 11:57:05 +0000283
284/*
285 * MAMR settings for SDRAM
286 */
287
288/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk0f8c9762002-08-19 11:57:05 +0000290 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
291 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
292/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk0f8c9762002-08-19 11:57:05 +0000294 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
295 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
296
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_MAMR 0x13a01114
wdenk0f8c9762002-08-19 11:57:05 +0000298/*
299 * Internal Definitions
300 *
301 * Boot Flags
302 */
303#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
304#define BOOTFLAG_WARM 0x02 /* Software reboot */
305
306
307/* values according to the manual */
308
309
310#define PCMCIA_MEM_ADDR ((uint)0xff020000)
311#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
312
313#define BCSR0 ((uint) (BCSR_ADDR + 00))
314#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
315#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
316#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
317#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
318
319/* FADS bitvalues by Helmut Buchsbaum
320 * see MPC8xxADS User's Manual for a proper description
321 * of the following structures
322 */
323
324#define BCSR0_ERB ((uint)0x80000000)
325#define BCSR0_IP ((uint)0x40000000)
326#define BCSR0_BDIS ((uint)0x10000000)
327#define BCSR0_BPS_MASK ((uint)0x0C000000)
328#define BCSR0_ISB_MASK ((uint)0x01800000)
329#define BCSR0_DBGC_MASK ((uint)0x00600000)
330#define BCSR0_DBPC_MASK ((uint)0x00180000)
331#define BCSR0_EBDF_MASK ((uint)0x00060000)
332
333#define BCSR1_FLASH_EN ((uint)0x80000000)
334#define BCSR1_DRAM_EN ((uint)0x40000000)
335#define BCSR1_ETHEN ((uint)0x20000000)
336#define BCSR1_IRDEN ((uint)0x10000000)
337#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
338#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
339#define BCSR1_BCSR_EN ((uint)0x02000000)
340#define BCSR1_RS232EN_1 ((uint)0x01000000)
341#define BCSR1_PCCEN ((uint)0x00800000)
342#define BCSR1_PCCVCC0 ((uint)0x00400000)
343#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
344#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
345#define BCSR1_RS232EN_2 ((uint)0x00040000)
346#define BCSR1_SDRAM_EN ((uint)0x00020000)
347#define BCSR1_PCCVCC1 ((uint)0x00010000)
348
349#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
wdenkb54d32b2004-06-10 21:34:36 +0000350#define BCSR2_FLASH_PD_SHIFT 28
wdenk0f8c9762002-08-19 11:57:05 +0000351#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
wdenkb54d32b2004-06-10 21:34:36 +0000352#define BCSR2_DRAM_PD_SHIFT 23
wdenk0f8c9762002-08-19 11:57:05 +0000353#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
354#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
355
356#define BCSR3_DBID_MASK ((ushort)0x3800)
357#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
358#define BCSR3_BREVNR0 ((ushort)0x0080)
359#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
360#define BCSR3_BREVN1 ((ushort)0x0008)
361#define BCSR3_BREVN2_MASK ((ushort)0x0003)
362
363#define BCSR4_ETHLOOP ((uint)0x80000000)
364#define BCSR4_TFPLDL ((uint)0x40000000)
365#define BCSR4_TPSQEL ((uint)0x20000000)
366#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
367#ifdef CONFIG_MPC823
368#define BCSR4_USB_EN ((uint)0x08000000)
369#endif /* CONFIG_MPC823 */
370#ifdef CONFIG_MPC860SAR
371#define BCSR4_UTOPIA_EN ((uint)0x08000000)
372#endif /* CONFIG_MPC860SAR */
373#ifdef CONFIG_MPC860T
374#define BCSR4_FETH_EN ((uint)0x08000000)
375#endif /* CONFIG_MPC860T */
376#ifdef CONFIG_MPC823
377#define BCSR4_USB_SPEED ((uint)0x04000000)
378#endif /* CONFIG_MPC823 */
379#ifdef CONFIG_MPC860T
380#define BCSR4_FETHCFG0 ((uint)0x04000000)
381#endif /* CONFIG_MPC860T */
382#ifdef CONFIG_MPC823
383#define BCSR4_VCCO ((uint)0x02000000)
384#endif /* CONFIG_MPC823 */
385#ifdef CONFIG_MPC860T
386#define BCSR4_FETHFDE ((uint)0x02000000)
387#endif /* CONFIG_MPC860T */
388#ifdef CONFIG_MPC823
389#define BCSR4_VIDEO_ON ((uint)0x00800000)
390#endif /* CONFIG_MPC823 */
391#ifdef CONFIG_MPC823
392#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
393#endif /* CONFIG_MPC823 */
394#ifdef CONFIG_MPC860T
395#define BCSR4_FETHCFG1 ((uint)0x00400000)
396#endif /* CONFIG_MPC860T */
397#ifdef CONFIG_MPC823
398#define BCSR4_VIDEO_RST ((uint)0x00200000)
399#endif /* CONFIG_MPC823 */
400#ifdef CONFIG_MPC860T
401#define BCSR4_FETHRST ((uint)0x00200000)
402#endif /* CONFIG_MPC860T */
403#define BCSR4_MODEM_EN ((uint)0x00100000)
404#define BCSR4_DATA_VOICE ((uint)0x00080000)
405
406#define CONFIG_DRAM_50MHZ 1
407#define CONFIG_SDRAM_50MHZ
408
wdenk0f8c9762002-08-19 11:57:05 +0000409/* We don't use the 8259.
410*/
411#define NR_8259_INTS 0
412
wdenk0f8c9762002-08-19 11:57:05 +0000413#define CONFIG_DISK_SPINUP_TIME 1000000
414
415
416/* PCMCIA configuration */
417
418#define PCMCIA_MAX_SLOTS 2
419
420#ifdef CONFIG_MPC860
421#define PCMCIA_SLOT_A 1
422#endif
423
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#define CONFIG_SYS_DAUGHTERBOARD
wdenk180d3f72004-01-04 16:28:35 +0000425
wdenk0f8c9762002-08-19 11:57:05 +0000426#endif /* __CONFIG_H */