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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 575205c9cc91e5914aa8b2ec884c78dc7d359b7c / . / arch / arm / dts / ast2600.dtsi
blob: f121f547e6d47bb5e3118a41cdb4b790c50d140b [file] [log] [blame]
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2#include <dt-bindings/interrupt-controller/arm-gic.h>
3#include "skeleton.dtsi"
4
5/ {
6 model = "Aspeed BMC";
7 compatible = "aspeed,ast2600";
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&gic>;
11
12 aliases {
13 i2c0 = &i2c0;
14 i2c1 = &i2c1;
15 i2c2 = &i2c2;
16 i2c3 = &i2c3;
17 i2c4 = &i2c4;
18 i2c5 = &i2c5;
19 i2c6 = &i2c6;
20 i2c7 = &i2c7;
21 i2c8 = &i2c8;
22 i2c9 = &i2c9;
23 i2c10 = &i2c10;
24 i2c11 = &i2c11;
25 i2c12 = &i2c12;
26 i2c13 = &i2c13;
27 i2c14 = &i2c14;
28 i2c15 = &i2c15;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 serial6 = &uart7;
36 serial7 = &uart8;
37 serial8 = &uart9;
38 serial9 = &uart10;
39 serial10 = &uart11;
40 serial11 = &uart12;
41 serial12 = &uart13;
42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47 enable-method = "aspeed,ast2600-smp";
48
49 cpu@0 {
50 compatible = "arm,cortex-a7";
51 device_type = "cpu";
52 reg = <0xf00>;
53 };
54
55 cpu@1 {
56 compatible = "arm,cortex-a7";
57 device_type = "cpu";
58 reg = <0xf01>;
59 };
60
61 };
62
63 timer {
64 compatible = "arm,armv7-timer";
65 interrupt-parent = <&gic>;
66 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
67 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
68 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
69 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
70 };
71
72 reserved-memory {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
76
77 gfx_memory: framebuffer {
78 size = <0x01000000>;
79 alignment = <0x01000000>;
80 compatible = "shared-dma-pool";
81 reusable;
82 };
83
84 video_memory: video {
85 size = <0x04000000>;
86 alignment = <0x01000000>;
87 compatible = "shared-dma-pool";
88 no-map;
89 };
90 };
91
92 ahb {
93 compatible = "simple-bus";
94 #address-cells = <1>;
95 #size-cells = <1>;
96 device_type = "soc";
97 ranges;
98
99 gic: interrupt-controller@40461000 {
100 compatible = "arm,cortex-a7-gic";
101 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
102 #interrupt-cells = <3>;
103 interrupt-controller;
104 interrupt-parent = <&gic>;
105 reg = <0x40461000 0x1000>,
106 <0x40462000 0x1000>,
107 <0x40464000 0x2000>,
108 <0x40466000 0x2000>;
109 };
110
111 ahbc: ahbc@1e600000 {
112 compatible = "aspeed,aspeed-ahbc";
113 reg = < 0x1e600000 0x100>;
114 };
115
116 fmc: flash-controller@1e620000 {
117 reg = < 0x1e620000 0xc4
118 0x20000000 0x10000000 >;
119 #address-cells = <1>;
120 #size-cells = <0>;
121 compatible = "aspeed,ast2600-fmc";
122 status = "disabled";
123 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&scu ASPEED_CLK_AHB>;
125 num-cs = <3>;
126 flash@0 {
127 reg = < 0 >;
128 compatible = "jedec,spi-nor";
129 status = "disabled";
130 };
131 flash@1 {
132 reg = < 1 >;
133 compatible = "jedec,spi-nor";
134 status = "disabled";
135 };
136 flash@2 {
137 reg = < 2 >;
138 compatible = "jedec,spi-nor";
139 status = "disabled";
140 };
141 };
142
143 spi1: flash-controller@1e630000 {
144 reg = < 0x1e630000 0xc4
145 0x30000000 0x08000000 >;
146 #address-cells = <1>;
147 #size-cells = <0>;
148 compatible = "aspeed,ast2600-spi";
149 clocks = <&scu ASPEED_CLK_AHB>;
150 num-cs = <2>;
151 status = "disabled";
152 flash@0 {
153 reg = < 0 >;
154 compatible = "jedec,spi-nor";
155 status = "disabled";
156 };
157 flash@1 {
158 reg = < 1 >;
159 compatible = "jedec,spi-nor";
160 status = "disabled";
161 };
162 };
163
164 spi2: flash-controller@1e631000 {
165 reg = < 0x1e631000 0xc4
166 0x50000000 0x08000000 >;
167 #address-cells = <1>;
168 #size-cells = <0>;
169 compatible = "aspeed,ast2600-spi";
170 clocks = <&scu ASPEED_CLK_AHB>;
171 num-cs = <3>;
172 status = "disabled";
173 flash@0 {
174 reg = < 0 >;
175 compatible = "jedec,spi-nor";
176 status = "disabled";
177 };
178 flash@1 {
179 reg = < 1 >;
180 compatible = "jedec,spi-nor";
181 status = "disabled";
182 };
183 flash@2 {
184 reg = < 2 >;
185 compatible = "jedec,spi-nor";
186 status = "disabled";
187 };
188 };
189
190 edac: sdram@1e6e0000 {
191 compatible = "aspeed,ast2600-sdram-edac";
192 reg = <0x1e6e0000 0x174>;
193 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
194 };
195
196 mdio: ethernet@1e650000 {
197 compatible = "aspeed,aspeed-mdio";
198 reg = <0x1e650000 0x40>;
199 resets = <&rst ASPEED_RESET_MII>;
200 status = "disabled";
201 };
202
203 mac0: ftgmac@1e660000 {
204 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
205 reg = <0x1e660000 0x180>, <0x1e650000 0x4>;
206 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>;
208 status = "disabled";
209 };
210
211 mac1: ftgmac@1e680000 {
212 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
213 reg = <0x1e680000 0x180>, <0x1e650008 0x4>;
214 #address-cells = <1>;
215 #size-cells = <0>;
216 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>;
218 status = "disabled";
219 };
220
221 mac2: ftgmac@1e670000 {
222 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
223 reg = <0x1e670000 0x180>, <0x1e650010 0x4>;
224 #address-cells = <1>;
225 #size-cells = <0>;
226 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>;
228 status = "disabled";
229 };
230
231 mac3: ftgmac@1e690000 {
232 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
233 reg = <0x1e690000 0x180>, <0x1e650018 0x4>;
234 #address-cells = <1>;
235 #size-cells = <0>;
236 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>;
238 status = "disabled";
239 };
240
241 ehci0: usb@1e6a1000 {
242 compatible = "aspeed,aspeed-ehci", "usb-ehci";
243 reg = <0x1e6a1000 0x100>;
244 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&scu ASPEED_CLK_GATE_USBPORT1CLK>;
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_usb2ah_default>;
248 status = "disabled";
249 };
250
251 ehci1: usb@1e6a3000 {
252 compatible = "aspeed,aspeed-ehci", "usb-ehci";
253 reg = <0x1e6a3000 0x100>;
254 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&scu ASPEED_CLK_GATE_USBPORT2CLK>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_usb2bh_default>;
258 status = "disabled";
259 };
260
261 apb {
262 compatible = "simple-bus";
263 #address-cells = <1>;
264 #size-cells = <1>;
265 ranges;
266
267 syscon: syscon@1e6e2000 {
268 compatible = "aspeed,g6-scu", "syscon", "simple-mfd";
269 reg = <0x1e6e2000 0x1000>;
270 #address-cells = <1>;
271 #size-cells = <1>;
272 #clock-cells = <1>;
273 #reset-cells = <1>;
274 ranges = <0 0x1e6e2000 0x1000>;
275
276 pinctrl: pinctrl {
277 compatible = "aspeed,g6-pinctrl";
278 aspeed,external-nodes = <&gfx &lhc>;
279
280 };
281
282 vga_scratch: scratch {
283 compatible = "aspeed,bmc-misc";
284 };
285
286 scu_ic0: interrupt-controller@0 {
287 #interrupt-cells = <1>;
288 compatible = "aspeed,ast2600-scu-ic";
289 reg = <0x560 0x10>;
290 interrupt-parent = <&gic>;
291 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
292 interrupt-controller;
293 };
294
295 scu_ic1: interrupt-controller@1 {
296 #interrupt-cells = <1>;
297 compatible = "aspeed,ast2600-scu-ic";
298 reg = <0x570 0x10>;
299 interrupt-parent = <&gic>;
300 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
301 interrupt-controller;
302 };
303
304 };
305
306 smp-memram@0 {
307 compatible = "aspeed,ast2600-smpmem", "syscon";
308 reg = <0x1e6e2180 0x40>;
309 };
310
311 gfx: display@1e6e6000 {
312 compatible = "aspeed,ast2500-gfx", "syscon";
313 reg = <0x1e6e6000 0x1000>;
314 reg-io-width = <4>;
315 };
316
317 pcie_bridge0: pcie@1e6ed000 {
318 compatible = "aspeed,ast2600-pcie";
319 #address-cells = <3>;
320 #size-cells = <2>;
321 reg = <0x1e6ed000 0x100>;
322 ranges = <0x81000000 0x0 0x0 0x0 0x0 0x10000>,
323 <0x82000000 0x0 0x60000000 0x60000000 0x0 0x10000000>;
324 device_type = "pci";
325 bus-range = <0x00 0xff>;
326 resets = <&rst ASPEED_RESET_PCIE_DEV_O>;
327 cfg-handle = <&pcie_cfg0>;
328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_pcie0rc_default>;
330
331 status = "disabled";
332 };
333
334 pcie_bridge1: pcie@1e6ed200 {
335 compatible = "aspeed,ast2600-pcie";
336 #address-cells = <3>;
337 #size-cells = <2>;
338 reg = <0x1e6ed200 0x100>;
339 ranges = <0x81000000 0x0 0x0 0x10000 0x00 0x10000>,
340 <0x82000000 0x0 0x70000000 0x70000000 0x0 0x10000000>;
341 device_type = "pci";
342 bus-range = <0x00 0xff>;
343 resets = <&rst ASPEED_RESET_PCIE_RC_O>;
344 cfg-handle = <&pcie_cfg1>;
345 pinctrl-names = "default";
346 pinctrl-0 = <&pinctrl_pcie1rc_default>;
347
348 status = "disabled";
349 };
350
351 sdhci: sdhci@1e740000 {
352 #interrupt-cells = <1>;
353 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd";
354 reg = <0x1e740000 0x1000>;
355 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
356 interrupt-controller;
357 clocks = <&scu ASPEED_CLK_GATE_SDCLK>,
358 <&scu ASPEED_CLK_GATE_SDEXTCLK>;
359 clock-names = "ctrlclk", "extclk";
360 #address-cells = <1>;
361 #size-cells = <1>;
362 ranges = <0x0 0x1e740000 0x1000>;
363
364 sdhci_slot0: sdhci_slot0@100 {
365 compatible = "aspeed,sdhci-ast2600";
366 reg = <0x100 0x100>;
367 interrupts = <0>;
368 interrupt-parent = <&sdhci>;
369 sdhci,auto-cmd12;
370 clocks = <&scu ASPEED_CLK_SDIO>;
371 status = "disabled";
372 };
373
374 sdhci_slot1: sdhci_slot1@200 {
375 compatible = "aspeed,sdhci-ast2600";
376 reg = <0x200 0x100>;
377 interrupts = <1>;
378 interrupt-parent = <&sdhci>;
379 sdhci,auto-cmd12;
380 clocks = <&scu ASPEED_CLK_SDIO>;
381 status = "disabled";
382 };
383 };
384
385 emmc: emmc@1e750000 {
386 #interrupt-cells = <1>;
387 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd";
388 reg = <0x1e750000 0x1000>;
389 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
390 interrupt-controller;
391 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>,
392 <&scu ASPEED_CLK_GATE_EMMCEXTCLK>;
393 clock-names = "ctrlclk", "extclk";
394 #address-cells = <1>;
395 #size-cells = <1>;
396 ranges = <0x0 0x1e750000 0x1000>;
397
398 emmc_slot0: emmc_slot0@100 {
399 compatible = "aspeed,emmc-ast2600";
400 reg = <0x100 0x100>;
401 interrupts = <0>;
402 interrupt-parent = <&emmc>;
403 clocks = <&scu ASPEED_CLK_EMMC>;
404 status = "disabled";
405 };
406 };
407
408 h2x: h2x@1e770000 {
409 compatible = "aspeed,ast2600-h2x";
410 reg = <0x1e770000 0x100>;
411 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
412 resets = <&rst ASPEED_RESET_H2X>;
413 #address-cells = <1>;
414 #size-cells = <1>;
415 ranges = <0x0 0x1e770000 0x100>;
416
417 status = "disabled";
418
419 pcie_cfg0: cfg0@80 {
420 reg = <0x80 0x80>;
421 compatible = "aspeed,ast2600-pcie-cfg";
422 };
423
424 pcie_cfg1: cfg1@C0 {
425 compatible = "aspeed,ast2600-pcie-cfg";
426 reg = <0xC0 0x80>;
427 };
428 };
429
430 gpio0: gpio@1e780000 {
431 compatible = "aspeed,ast2600-gpio";
432 reg = <0x1e780000 0x1000>;
433 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
434 #gpio-cells = <2>;
435 gpio-controller;
436 interrupt-controller;
437 gpio-ranges = <&pinctrl 0 0 220>;
438 ngpios = <208>;
439 };
440
441 gpio1: gpio@1e780800 {
442 compatible = "aspeed,ast2600-gpio";
443 reg = <0x1e780800 0x800>;
444 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
445 #gpio-cells = <2>;
446 gpio-controller;
447 interrupt-controller;
448 gpio-ranges = <&pinctrl 0 0 208>;
449 ngpios = <36>;
450 };
451
452 uart1: serial@1e783000 {
453 compatible = "ns16550a";
454 reg = <0x1e783000 0x20>;
455 reg-shift = <2>;
456 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
458 clock-frequency = <1846154>;
459 no-loopback-test;
460 status = "disabled";
461 };
462
463 uart5: serial@1e784000 {
464 compatible = "ns16550a";
465 reg = <0x1e784000 0x1000>;
466 reg-shift = <2>;
467 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
469 clock-frequency = <1846154>;
470 no-loopback-test;
471 status = "disabled";
472 };
473
474 wdt1: watchdog@1e785000 {
475 compatible = "aspeed,ast2600-wdt";
476 reg = <0x1e785000 0x40>;
Chia-Wei Wang8e1ebdc2021-09-16 14:10:09 +0800[diff] [blame]477 status = "disabled";
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]478 };
479
480 wdt2: watchdog@1e785040 {
481 compatible = "aspeed,ast2600-wdt";
482 reg = <0x1e785040 0x40>;
Chia-Wei Wang8e1ebdc2021-09-16 14:10:09 +0800[diff] [blame]483 status = "disabled";
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]484 };
485
486 wdt3: watchdog@1e785080 {
487 compatible = "aspeed,ast2600-wdt";
488 reg = <0x1e785080 0x40>;
Chia-Wei Wang8e1ebdc2021-09-16 14:10:09 +0800[diff] [blame]489 status = "disabled";
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]490 };
491
492 wdt4: watchdog@1e7850C0 {
493 compatible = "aspeed,ast2600-wdt";
494 reg = <0x1e7850C0 0x40>;
Chia-Wei Wang8e1ebdc2021-09-16 14:10:09 +0800[diff] [blame]495 status = "disabled";
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]496 };
497
498 lpc: lpc@1e789000 {
499 compatible = "aspeed,ast2600-lpc", "simple-mfd", "syscon";
500 reg = <0x1e789000 0x1000>;
501
502 #address-cells = <1>;
503 #size-cells = <1>;
504 ranges = <0x0 0x1e789000 0x1000>;
505
506 kcs1: kcs1@0 {
507 compatible = "aspeed,ast2600-kcs-bmc";
508 reg = <0x0 0x80>;
509 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
510 kcs_chan = <1>;
511 kcs_addr = <0xCA0>;
512 status = "disabled";
513 };
514
515 kcs2: kcs2@0 {
516 compatible = "aspeed,ast2600-kcs-bmc";
517 reg = <0x0 0x80>;
518 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
519 kcs_chan = <2>;
520 kcs_addr = <0xCA8>;
521 status = "disabled";
522 };
523
524 kcs3: kcs3@0 {
525 compatible = "aspeed,ast2600-kcs-bmc";
526 reg = <0x0 0x80>;
527 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
528 kcs_chan = <3>;
529 kcs_addr = <0xCA2>;
530 };
531
532 kcs4: kcs4@0 {
533 compatible = "aspeed,ast2600-kcs-bmc";
534 reg = <0x0 0x120>;
535 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
536 kcs_chan = <4>;
537 kcs_addr = <0xCA4>;
538 status = "disabled";
539 };
540
541 lpc_ctrl: lpc-ctrl@80 {
542 compatible = "aspeed,ast2600-lpc-ctrl";
543 reg = <0x80 0x80>;
544 status = "disabled";
545 };
546
547 lpc_snoop: lpc-snoop@80 {
548 compatible = "aspeed,ast2600-lpc-snoop";
549 reg = <0x80 0x80>;
550 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
551 status = "disabled";
552 };
553
554 lhc: lhc@a0 {
555 compatible = "aspeed,ast2600-lhc";
556 reg = <0xa0 0x24 0xc8 0x8>;
557 };
558
559 lpc_reset: reset-controller@98 {
560 compatible = "aspeed,ast2600-lpc-reset";
561 reg = <0x98 0x4>;
562 #reset-cells = <1>;
563 status = "disabled";
564 };
565
566 ibt: ibt@140 {
567 compatible = "aspeed,ast2600-ibt-bmc";
568 reg = <0x140 0x18>;
569 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
570 status = "disabled";
571 };
572
573 sio_regs: regs {
574 compatible = "aspeed,bmc-misc";
575 };
576
577 mbox: mbox@200 {
578 compatible = "aspeed,ast2600-mbox";
579 reg = <0x200 0x5c>;
580 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
581 #mbox-cells = <1>;
582 status = "disabled";
583 };
584 };
585
586 uart2: serial@1e78d000 {
587 compatible = "ns16550a";
588 reg = <0x1e78d000 0x20>;
589 reg-shift = <2>;
590 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
592 clock-frequency = <1846154>;
593 no-loopback-test;
594 status = "disabled";
595 };
596
597 uart3: serial@1e78e000 {
598 compatible = "ns16550a";
599 reg = <0x1e78e000 0x20>;
600 reg-shift = <2>;
601 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
603 clock-frequency = <1846154>;
604 no-loopback-test;
605 status = "disabled";
606 };
607
608 uart4: serial@1e78f000 {
609 compatible = "ns16550a";
610 reg = <0x1e78f000 0x20>;
611 reg-shift = <2>;
612 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
614 clock-frequency = <1846154>;
615 no-loopback-test;
616 status = "disabled";
617 };
618
619 i2c: bus@1e78a000 {
620 compatible = "simple-bus";
621 #address-cells = <1>;
622 #size-cells = <1>;
623 ranges = <0 0x1e78a000 0x1000>;
624 };
625
626 fsim0: fsi@1e79b000 {
627 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
628 reg = <0x1e79b000 0x94>;
629 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
630 pinctrl-names = "default";
631 pinctrl-0 = <&pinctrl_fsi1_default>;
632 clocks = <&scu ASPEED_CLK_GATE_FSICLK>;
633 status = "disabled";
634 };
635
636 fsim1: fsi@1e79b100 {
637 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
638 reg = <0x1e79b100 0x94>;
639 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
640 pinctrl-names = "default";
641 pinctrl-0 = <&pinctrl_fsi2_default>;
642 clocks = <&scu ASPEED_CLK_GATE_FSICLK>;
643 status = "disabled";
644 };
645
646 uart6: serial@1e790000 {
647 compatible = "ns16550a";
648 reg = <0x1e790000 0x20>;
649 reg-shift = <2>;
650 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>;
652 clock-frequency = <1846154>;
653 no-loopback-test;
654 status = "disabled";
655 };
656
657 uart7: serial@1e790100 {
658 compatible = "ns16550a";
659 reg = <0x1e790100 0x20>;
660 reg-shift = <2>;
661 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>;
663 clock-frequency = <1846154>;
664 no-loopback-test;
665 status = "disabled";
666 };
667
668 uart8: serial@1e790200 {
669 compatible = "ns16550a";
670 reg = <0x1e790200 0x20>;
671 reg-shift = <2>;
672 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>;
674 clock-frequency = <1846154>;
675 no-loopback-test;
676 status = "disabled";
677 };
678
679 uart9: serial@1e790300 {
680 compatible = "ns16550a";
681 reg = <0x1e790300 0x20>;
682 reg-shift = <2>;
683 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>;
685 clock-frequency = <1846154>;
686 no-loopback-test;
687 status = "disabled";
688 };
689
690 uart10: serial@1e790400 {
691 compatible = "ns16550a";
692 reg = <0x1e790400 0x20>;
693 reg-shift = <2>;
694 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>;
696 clock-frequency = <1846154>;
697 no-loopback-test;
698 status = "disabled";
699 };
700
701 uart11: serial@1e790500 {
702 compatible = "ns16550a";
703 reg = <0x1e790400 0x20>;
704 reg-shift = <2>;
705 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>;
707 clock-frequency = <1846154>;
708 no-loopback-test;
709 status = "disabled";
710 };
711
712 uart12: serial@1e790600 {
713 compatible = "ns16550a";
714 reg = <0x1e790600 0x20>;
715 reg-shift = <2>;
716 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>;
718 clock-frequency = <1846154>;
719 no-loopback-test;
720 status = "disabled";
721 };
722
723 uart13: serial@1e790700 {
724 compatible = "ns16550a";
725 reg = <0x1e790700 0x20>;
726 reg-shift = <2>;
727 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>;
729 clock-frequency = <1846154>;
730 no-loopback-test;
731 status = "disabled";
732 };
733
734 display_port: dp@1e6eb000 {
735 compatible = "aspeed,ast2600-displayport";
736 reg = <0x1e6eb000 0x200>;
737 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
738 resets = <&rst ASPEED_RESET_DP> ,<&rst ASPEED_RESET_DP_MCU>;
739 status = "disabled";
740 };
741
742 };
743
744 };
745
746};
747
748&i2c {
749 i2cglobal: i2cg@00 {
750 compatible = "aspeed,ast2600-i2c-global";
751 reg = <0x0 0x40>;
752 resets = <&rst ASPEED_RESET_I2C>;
753#if 0
754 new-mode;
755#endif
756 };
757
758 i2c0: i2c@80 {
759 #address-cells = <1>;
760 #size-cells = <0>;
761 #interrupt-cells = <1>;
762
763 reg = <0x80 0x80 0xC00 0x20>;
764 compatible = "aspeed,ast2600-i2c-bus";
765 bus-frequency = <100000>;
766 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
767 clocks = <&scu ASPEED_CLK_APB2>;
768 status = "disabled";
769 };
770
771 i2c1: i2c@100 {
772 #address-cells = <1>;
773 #size-cells = <0>;
774 #interrupt-cells = <1>;
775
776 reg = <0x100 0x80 0xC20 0x20>;
777 compatible = "aspeed,ast2600-i2c-bus";
778 bus-frequency = <100000>;
779 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&scu ASPEED_CLK_APB2>;
781 status = "disabled";
782 };
783
784 i2c2: i2c@180 {
785 #address-cells = <1>;
786 #size-cells = <0>;
787 #interrupt-cells = <1>;
788
789 reg = <0x180 0x80 0xC40 0x20>;
790 compatible = "aspeed,ast2600-i2c-bus";
791 bus-frequency = <100000>;
792 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&scu ASPEED_CLK_APB2>;
794 };
795
796 i2c3: i2c@200 {
797 #address-cells = <1>;
798 #size-cells = <0>;
799 #interrupt-cells = <1>;
800
801 reg = <0x200 0x40 0xC60 0x20>;
802 compatible = "aspeed,ast2600-i2c-bus";
803 bus-frequency = <100000>;
804 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&scu ASPEED_CLK_APB2>;
806 };
807
808 i2c4: i2c@280 {
809 #address-cells = <1>;
810 #size-cells = <0>;
811 #interrupt-cells = <1>;
812
813 reg = <0x280 0x80 0xC80 0x20>;
814 compatible = "aspeed,ast2600-i2c-bus";
815 bus-frequency = <100000>;
816 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
817 clocks = <&scu ASPEED_CLK_APB2>;
818 };
819
820 i2c5: i2c@300 {
821 #address-cells = <1>;
822 #size-cells = <0>;
823 #interrupt-cells = <1>;
824
825 reg = <0x300 0x40 0xCA0 0x20>;
826 compatible = "aspeed,ast2600-i2c-bus";
827 bus-frequency = <100000>;
828 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&scu ASPEED_CLK_APB2>;
830 };
831
832 i2c6: i2c@380 {
833 #address-cells = <1>;
834 #size-cells = <0>;
835 #interrupt-cells = <1>;
836
837 reg = <0x380 0x80 0xCC0 0x20>;
838 compatible = "aspeed,ast2600-i2c-bus";
839 bus-frequency = <100000>;
840 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
841 clocks = <&scu ASPEED_CLK_APB2>;
842 };
843
844 i2c7: i2c@400 {
845 #address-cells = <1>;
846 #size-cells = <0>;
847 #interrupt-cells = <1>;
848
849 reg = <0x400 0x80 0xCE0 0x20>;
850 compatible = "aspeed,ast2600-i2c-bus";
851 bus-frequency = <100000>;
852 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
853 clocks = <&scu ASPEED_CLK_APB2>;
854 };
855
856 i2c8: i2c@480 {
857 #address-cells = <1>;
858 #size-cells = <0>;
859 #interrupt-cells = <1>;
860
861 reg = <0x480 0x80 0xD00 0x20>;
862 compatible = "aspeed,ast2600-i2c-bus";
863 bus-frequency = <100000>;
864 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&scu ASPEED_CLK_APB2>;
866 };
867
868 i2c9: i2c@500 {
869 #address-cells = <1>;
870 #size-cells = <0>;
871 #interrupt-cells = <1>;
872
873 reg = <0x500 0x80 0xD20 0x20>;
874 compatible = "aspeed,ast2600-i2c-bus";
875 bus-frequency = <100000>;
876 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
877 clocks = <&scu ASPEED_CLK_APB2>;
878 status = "disabled";
879 };
880
881 i2c10: i2c@580 {
882 #address-cells = <1>;
883 #size-cells = <0>;
884 #interrupt-cells = <1>;
885
886 reg = <0x580 0x80 0xD40 0x20>;
887 compatible = "aspeed,ast2600-i2c-bus";
888 bus-frequency = <100000>;
889 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
890 clocks = <&scu ASPEED_CLK_APB2>;
891 status = "disabled";
892 };
893
894 i2c11: i2c@600 {
895 #address-cells = <1>;
896 #size-cells = <0>;
897 #interrupt-cells = <1>;
898
899 reg = <0x600 0x80 0xD60 0x20>;
900 compatible = "aspeed,ast2600-i2c-bus";
901 bus-frequency = <100000>;
902 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
903 clocks = <&scu ASPEED_CLK_APB2>;
904 status = "disabled";
905 };
906
907 i2c12: i2c@680 {
908 #address-cells = <1>;
909 #size-cells = <0>;
910 #interrupt-cells = <1>;
911
912 reg = <0x680 0x80 0xD80 0x20>;
913 compatible = "aspeed,ast2600-i2c-bus";
914 bus-frequency = <100000>;
915 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
916 clocks = <&scu ASPEED_CLK_APB2>;
917 status = "disabled";
918 };
919
920 i2c13: i2c@700 {
921 #address-cells = <1>;
922 #size-cells = <0>;
923 #interrupt-cells = <1>;
924
925 reg = <0x700 0x80 0xDA0 0x20>;
926 compatible = "aspeed,ast2600-i2c-bus";
927 bus-frequency = <100000>;
928 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&scu ASPEED_CLK_APB2>;
930 status = "disabled";
931 };
932
933 i2c14: i2c@780 {
934 #address-cells = <1>;
935 #size-cells = <0>;
936 #interrupt-cells = <1>;
937
938 reg = <0x780 0x80 0xDC0 0x20>;
939 compatible = "aspeed,ast2600-i2c-bus";
940 bus-frequency = <100000>;
941 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
942 clocks = <&scu ASPEED_CLK_APB2>;
943 status = "disabled";
944 };
945
946 i2c15: i2c@800 {
947 #address-cells = <1>;
948 #size-cells = <0>;
949 #interrupt-cells = <1>;
950
951 reg = <0x800 0x80 0xDE0 0x20>;
952 compatible = "aspeed,ast2600-i2c-bus";
953 bus-frequency = <100000>;
954 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
955 clocks = <&scu ASPEED_CLK_APB2>;
956 status = "disabled";
957 };
958
959};
960
961&pinctrl {
962 pinctrl_fmcquad_default: fmcquad_default {
963 function = "FMCQUAD";
964 groups = "FMCQUAD";
965 };
966
967 pinctrl_spi1_default: spi1_default {
968 function = "SPI1";
969 groups = "SPI1";
970 };
971
972 pinctrl_spi1abr_default: spi1abr_default {
973 function = "SPI1ABR";
974 groups = "SPI1ABR";
975 };
976
977 pinctrl_spi1cs1_default: spi1cs1_default {
978 function = "SPI1CS1";
979 groups = "SPI1CS1";
980 };
981
982 pinctrl_spi1wp_default: spi1wp_default {
983 function = "SPI1WP";
984 groups = "SPI1WP";
985 };
986
987 pinctrl_spi1quad_default: spi1quad_default {
988 function = "SPI1QUAD";
989 groups = "SPI1QUAD";
990 };
991
992 pinctrl_spi2_default: spi2_default {
993 function = "SPI2";
994 groups = "SPI2";
995 };
996
997 pinctrl_spi2cs1_default: spi2cs1_default {
998 function = "SPI2CS1";
999 groups = "SPI2CS1";
1000 };
1001
1002 pinctrl_spi2cs2_default: spi2cs2_default {
1003 function = "SPI2CS2";
1004 groups = "SPI2CS2";
1005 };
1006
1007 pinctrl_spi2quad_default: spi2quad_default {
1008 function = "SPI2QUAD";
1009 groups = "SPI2QUAD";
1010 };
1011
1012 pinctrl_acpi_default: acpi_default {
1013 function = "ACPI";
1014 groups = "ACPI";
1015 };
1016
1017 pinctrl_adc0_default: adc0_default {
1018 function = "ADC0";
1019 groups = "ADC0";
1020 };
1021
1022 pinctrl_adc1_default: adc1_default {
1023 function = "ADC1";
1024 groups = "ADC1";
1025 };
1026
1027 pinctrl_adc10_default: adc10_default {
1028 function = "ADC10";
1029 groups = "ADC10";
1030 };
1031
1032 pinctrl_adc11_default: adc11_default {
1033 function = "ADC11";
1034 groups = "ADC11";
1035 };
1036
1037 pinctrl_adc12_default: adc12_default {
1038 function = "ADC12";
1039 groups = "ADC12";
1040 };
1041
1042 pinctrl_adc13_default: adc13_default {
1043 function = "ADC13";
1044 groups = "ADC13";
1045 };
1046
1047 pinctrl_adc14_default: adc14_default {
1048 function = "ADC14";
1049 groups = "ADC14";
1050 };
1051
1052 pinctrl_adc15_default: adc15_default {
1053 function = "ADC15";
1054 groups = "ADC15";
1055 };
1056
1057 pinctrl_adc2_default: adc2_default {
1058 function = "ADC2";
1059 groups = "ADC2";
1060 };
1061
1062 pinctrl_adc3_default: adc3_default {
1063 function = "ADC3";
1064 groups = "ADC3";
1065 };
1066
1067 pinctrl_adc4_default: adc4_default {
1068 function = "ADC4";
1069 groups = "ADC4";
1070 };
1071
1072 pinctrl_adc5_default: adc5_default {
1073 function = "ADC5";
1074 groups = "ADC5";
1075 };
1076
1077 pinctrl_adc6_default: adc6_default {
1078 function = "ADC6";
1079 groups = "ADC6";
1080 };
1081
1082 pinctrl_adc7_default: adc7_default {
1083 function = "ADC7";
1084 groups = "ADC7";
1085 };
1086
1087 pinctrl_adc8_default: adc8_default {
1088 function = "ADC8";
1089 groups = "ADC8";
1090 };
1091
1092 pinctrl_adc9_default: adc9_default {
1093 function = "ADC9";
1094 groups = "ADC9";
1095 };
1096
1097 pinctrl_bmcint_default: bmcint_default {
1098 function = "BMCINT";
1099 groups = "BMCINT";
1100 };
1101
1102 pinctrl_ddcclk_default: ddcclk_default {
1103 function = "DDCCLK";
1104 groups = "DDCCLK";
1105 };
1106
1107 pinctrl_ddcdat_default: ddcdat_default {
1108 function = "DDCDAT";
1109 groups = "DDCDAT";
1110 };
1111
1112 pinctrl_espi_default: espi_default {
1113 function = "ESPI";
1114 groups = "ESPI";
1115 };
1116
1117 pinctrl_fsi1_default: fsi1_default {
1118 function = "FSI1";
1119 groups = "FSI1";
1120 };
1121
1122 pinctrl_fsi2_default: fsi2_default {
1123 function = "FSI2";
1124 groups = "FSI2";
1125 };
1126
1127 pinctrl_fwspics1_default: fwspics1_default {
1128 function = "FWSPICS1";
1129 groups = "FWSPICS1";
1130 };
1131
1132 pinctrl_fwspics2_default: fwspics2_default {
1133 function = "FWSPICS2";
1134 groups = "FWSPICS2";
1135 };
1136
1137 pinctrl_gpid0_default: gpid0_default {
1138 function = "GPID0";
1139 groups = "GPID0";
1140 };
1141
1142 pinctrl_gpid2_default: gpid2_default {
1143 function = "GPID2";
1144 groups = "GPID2";
1145 };
1146
1147 pinctrl_gpid4_default: gpid4_default {
1148 function = "GPID4";
1149 groups = "GPID4";
1150 };
1151
1152 pinctrl_gpid6_default: gpid6_default {
1153 function = "GPID6";
1154 groups = "GPID6";
1155 };
1156
1157 pinctrl_gpie0_default: gpie0_default {
1158 function = "GPIE0";
1159 groups = "GPIE0";
1160 };
1161
1162 pinctrl_gpie2_default: gpie2_default {
1163 function = "GPIE2";
1164 groups = "GPIE2";
1165 };
1166
1167 pinctrl_gpie4_default: gpie4_default {
1168 function = "GPIE4";
1169 groups = "GPIE4";
1170 };
1171
1172 pinctrl_gpie6_default: gpie6_default {
1173 function = "GPIE6";
1174 groups = "GPIE6";
1175 };
1176
1177 pinctrl_i2c1_default: i2c1_default {
1178 function = "I2C1";
1179 groups = "I2C1";
1180 };
1181 pinctrl_i2c2_default: i2c2_default {
1182 function = "I2C2";
1183 groups = "I2C2";
1184 };
1185
1186 pinctrl_i2c3_default: i2c3_default {
1187 function = "I2C3";
1188 groups = "I2C3";
1189 };
1190
1191 pinctrl_i2c4_default: i2c4_default {
1192 function = "I2C4";
1193 groups = "I2C4";
1194 };
1195
1196 pinctrl_i2c5_default: i2c5_default {
1197 function = "I2C5";
1198 groups = "I2C5";
1199 };
1200
1201 pinctrl_i2c6_default: i2c6_default {
1202 function = "I2C6";
1203 groups = "I2C6";
1204 };
1205
1206 pinctrl_i2c7_default: i2c7_default {
1207 function = "I2C7";
1208 groups = "I2C7";
1209 };
1210
1211 pinctrl_i2c8_default: i2c8_default {
1212 function = "I2C8";
1213 groups = "I2C8";
1214 };
1215
1216 pinctrl_i2c9_default: i2c9_default {
1217 function = "I2C9";
1218 groups = "I2C9";
1219 };
1220
1221 pinctrl_i2c10_default: i2c10_default {
1222 function = "I2C10";
1223 groups = "I2C10";
1224 };
1225
1226 pinctrl_i2c11_default: i2c11_default {
1227 function = "I2C11";
1228 groups = "I2C11";
1229 };
1230
1231 pinctrl_i2c12_default: i2c12_default {
1232 function = "I2C12";
1233 groups = "I2C12";
1234 };
1235
1236 pinctrl_i2c13_default: i2c13_default {
1237 function = "I2C13";
1238 groups = "I2C13";
1239 };
1240
1241 pinctrl_i2c14_default: i2c14_default {
1242 function = "I2C14";
1243 groups = "I2C14";
1244 };
1245
1246 pinctrl_i2c15_default: i2c15_default {
1247 function = "I2C15";
1248 groups = "I2C15";
1249 };
1250
1251 pinctrl_i2c16_default: i2c16_default {
1252 function = "I2C16";
1253 groups = "I2C16";
1254 };
1255
1256 pinctrl_lad0_default: lad0_default {
1257 function = "LAD0";
1258 groups = "LAD0";
1259 };
1260
1261 pinctrl_lad1_default: lad1_default {
1262 function = "LAD1";
1263 groups = "LAD1";
1264 };
1265
1266 pinctrl_lad2_default: lad2_default {
1267 function = "LAD2";
1268 groups = "LAD2";
1269 };
1270
1271 pinctrl_lad3_default: lad3_default {
1272 function = "LAD3";
1273 groups = "LAD3";
1274 };
1275
1276 pinctrl_lclk_default: lclk_default {
1277 function = "LCLK";
1278 groups = "LCLK";
1279 };
1280
1281 pinctrl_lframe_default: lframe_default {
1282 function = "LFRAME";
1283 groups = "LFRAME";
1284 };
1285
1286 pinctrl_lpchc_default: lpchc_default {
1287 function = "LPCHC";
1288 groups = "LPCHC";
1289 };
1290
1291 pinctrl_lpcpd_default: lpcpd_default {
1292 function = "LPCPD";
1293 groups = "LPCPD";
1294 };
1295
1296 pinctrl_lpcplus_default: lpcplus_default {
1297 function = "LPCPLUS";
1298 groups = "LPCPLUS";
1299 };
1300
1301 pinctrl_lpcpme_default: lpcpme_default {
1302 function = "LPCPME";
1303 groups = "LPCPME";
1304 };
1305
1306 pinctrl_lpcrst_default: lpcrst_default {
1307 function = "LPCRST";
1308 groups = "LPCRST";
1309 };
1310
1311 pinctrl_lpcsmi_default: lpcsmi_default {
1312 function = "LPCSMI";
1313 groups = "LPCSMI";
1314 };
1315
1316 pinctrl_lsirq_default: lsirq_default {
1317 function = "LSIRQ";
1318 groups = "LSIRQ";
1319 };
1320
1321 pinctrl_mac1link_default: mac1link_default {
1322 function = "MAC1LINK";
1323 groups = "MAC1LINK";
1324 };
1325
1326 pinctrl_mac2link_default: mac2link_default {
1327 function = "MAC2LINK";
1328 groups = "MAC2LINK";
1329 };
1330
1331 pinctrl_mac3link_default: mac3link_default {
1332 function = "MAC3LINK";
1333 groups = "MAC3LINK";
1334 };
1335
1336 pinctrl_mac4link_default: mac4link_default {
1337 function = "MAC4LINK";
1338 groups = "MAC4LINK";
1339 };
1340
1341 pinctrl_mdio1_default: mdio1_default {
1342 function = "MDIO1";
1343 groups = "MDIO1";
1344 };
1345
1346 pinctrl_mdio2_default: mdio2_default {
1347 function = "MDIO2";
1348 groups = "MDIO2";
1349 };
1350
1351 pinctrl_mdio3_default: mdio3_default {
1352 function = "MDIO3";
1353 groups = "MDIO3";
1354 };
1355
1356 pinctrl_mdio4_default: mdio4_default {
1357 function = "MDIO4";
1358 groups = "MDIO4";
1359 };
1360
1361 pinctrl_rmii1_default: rmii1_default {
1362 function = "RMII1";
1363 groups = "RMII1";
1364 };
1365
1366 pinctrl_rmii2_default: rmii2_default {
1367 function = "RMII2";
1368 groups = "RMII2";
1369 };
1370
1371 pinctrl_rmii3_default: rmii3_default {
1372 function = "RMII3";
1373 groups = "RMII3";
1374 };
1375
1376 pinctrl_rmii4_default: rmii4_default {
1377 function = "RMII4";
1378 groups = "RMII4";
1379 };
1380
1381 pinctrl_rmii1rclk_default: rmii1rclk_default {
1382 function = "RMII1RCLK";
1383 groups = "RMII1RCLK";
1384 };
1385
1386 pinctrl_rmii2rclk_default: rmii2rclk_default {
1387 function = "RMII2RCLK";
1388 groups = "RMII2RCLK";
1389 };
1390
1391 pinctrl_rmii3rclk_default: rmii3rclk_default {
1392 function = "RMII3RCLK";
1393 groups = "RMII3RCLK";
1394 };
1395
1396 pinctrl_rmii4rclk_default: rmii4rclk_default {
1397 function = "RMII4RCLK";
1398 groups = "RMII4RCLK";
1399 };
1400
1401 pinctrl_ncts1_default: ncts1_default {
1402 function = "NCTS1";
1403 groups = "NCTS1";
1404 };
1405
1406 pinctrl_ncts2_default: ncts2_default {
1407 function = "NCTS2";
1408 groups = "NCTS2";
1409 };
1410
1411 pinctrl_ncts3_default: ncts3_default {
1412 function = "NCTS3";
1413 groups = "NCTS3";
1414 };
1415
1416 pinctrl_ncts4_default: ncts4_default {
1417 function = "NCTS4";
1418 groups = "NCTS4";
1419 };
1420
1421 pinctrl_ndcd1_default: ndcd1_default {
1422 function = "NDCD1";
1423 groups = "NDCD1";
1424 };
1425
1426 pinctrl_ndcd2_default: ndcd2_default {
1427 function = "NDCD2";
1428 groups = "NDCD2";
1429 };
1430
1431 pinctrl_ndcd3_default: ndcd3_default {
1432 function = "NDCD3";
1433 groups = "NDCD3";
1434 };
1435
1436 pinctrl_ndcd4_default: ndcd4_default {
1437 function = "NDCD4";
1438 groups = "NDCD4";
1439 };
1440
1441 pinctrl_ndsr1_default: ndsr1_default {
1442 function = "NDSR1";
1443 groups = "NDSR1";
1444 };
1445
1446 pinctrl_ndsr2_default: ndsr2_default {
1447 function = "NDSR2";
1448 groups = "NDSR2";
1449 };
1450
1451 pinctrl_ndsr3_default: ndsr3_default {
1452 function = "NDSR3";
1453 groups = "NDSR3";
1454 };
1455
1456 pinctrl_ndsr4_default: ndsr4_default {
1457 function = "NDSR4";
1458 groups = "NDSR4";
1459 };
1460
1461 pinctrl_ndtr1_default: ndtr1_default {
1462 function = "NDTR1";
1463 groups = "NDTR1";
1464 };
1465
1466 pinctrl_ndtr2_default: ndtr2_default {
1467 function = "NDTR2";
1468 groups = "NDTR2";
1469 };
1470
1471 pinctrl_ndtr3_default: ndtr3_default {
1472 function = "NDTR3";
1473 groups = "NDTR3";
1474 };
1475
1476 pinctrl_ndtr4_default: ndtr4_default {
1477 function = "NDTR4";
1478 groups = "NDTR4";
1479 };
1480
1481 pinctrl_nri1_default: nri1_default {
1482 function = "NRI1";
1483 groups = "NRI1";
1484 };
1485
1486 pinctrl_nri2_default: nri2_default {
1487 function = "NRI2";
1488 groups = "NRI2";
1489 };
1490
1491 pinctrl_nri3_default: nri3_default {
1492 function = "NRI3";
1493 groups = "NRI3";
1494 };
1495
1496 pinctrl_nri4_default: nri4_default {
1497 function = "NRI4";
1498 groups = "NRI4";
1499 };
1500
1501 pinctrl_nrts1_default: nrts1_default {
1502 function = "NRTS1";
1503 groups = "NRTS1";
1504 };
1505
1506 pinctrl_nrts2_default: nrts2_default {
1507 function = "NRTS2";
1508 groups = "NRTS2";
1509 };
1510
1511 pinctrl_nrts3_default: nrts3_default {
1512 function = "NRTS3";
1513 groups = "NRTS3";
1514 };
1515
1516 pinctrl_nrts4_default: nrts4_default {
1517 function = "NRTS4";
1518 groups = "NRTS4";
1519 };
1520
1521 pinctrl_oscclk_default: oscclk_default {
1522 function = "OSCCLK";
1523 groups = "OSCCLK";
1524 };
1525
1526 pinctrl_pewake_default: pewake_default {
1527 function = "PEWAKE";
1528 groups = "PEWAKE";
1529 };
1530
1531 pinctrl_pnor_default: pnor_default {
1532 function = "PNOR";
1533 groups = "PNOR";
1534 };
1535
1536 pinctrl_pwm0_default: pwm0_default {
1537 function = "PWM0";
1538 groups = "PWM0";
1539 };
1540
1541 pinctrl_pwm1_default: pwm1_default {
1542 function = "PWM1";
1543 groups = "PWM1";
1544 };
1545
1546 pinctrl_pwm2_default: pwm2_default {
1547 function = "PWM2";
1548 groups = "PWM2";
1549 };
1550
1551 pinctrl_pwm3_default: pwm3_default {
1552 function = "PWM3";
1553 groups = "PWM3";
1554 };
1555
1556 pinctrl_pwm4_default: pwm4_default {
1557 function = "PWM4";
1558 groups = "PWM4";
1559 };
1560
1561 pinctrl_pwm5_default: pwm5_default {
1562 function = "PWM5";
1563 groups = "PWM5";
1564 };
1565
1566 pinctrl_pwm6_default: pwm6_default {
1567 function = "PWM6";
1568 groups = "PWM6";
1569 };
1570
1571 pinctrl_pwm7_default: pwm7_default {
1572 function = "PWM7";
1573 groups = "PWM7";
1574 };
1575
1576 pinctrl_rgmii1_default: rgmii1_default {
1577 function = "RGMII1";
1578 groups = "RGMII1";
1579 };
1580
1581 pinctrl_rgmii2_default: rgmii2_default {
1582 function = "RGMII2";
1583 groups = "RGMII2";
1584 };
1585
1586 pinctrl_rgmii3_default: rgmii3_default {
1587 function = "RGMII3";
1588 groups = "RGMII3";
1589 };
1590
1591 pinctrl_rgmii4_default: rgmii4_default {
1592 function = "RGMII4";
1593 groups = "RGMII4";
1594 };
1595
1596 pinctrl_rmii1_default: rmii1_default {
1597 function = "RMII1";
1598 groups = "RMII1";
1599 };
1600
1601 pinctrl_rmii2_default: rmii2_default {
1602 function = "RMII2";
1603 groups = "RMII2";
1604 };
1605
1606 pinctrl_rxd1_default: rxd1_default {
1607 function = "RXD1";
1608 groups = "RXD1";
1609 };
1610
1611 pinctrl_rxd2_default: rxd2_default {
1612 function = "RXD2";
1613 groups = "RXD2";
1614 };
1615
1616 pinctrl_rxd3_default: rxd3_default {
1617 function = "RXD3";
1618 groups = "RXD3";
1619 };
1620
1621 pinctrl_rxd4_default: rxd4_default {
1622 function = "RXD4";
1623 groups = "RXD4";
1624 };
1625
1626 pinctrl_salt1_default: salt1_default {
1627 function = "SALT1";
1628 groups = "SALT1";
1629 };
1630
1631 pinctrl_salt10_default: salt10_default {
1632 function = "SALT10";
1633 groups = "SALT10";
1634 };
1635
1636 pinctrl_salt11_default: salt11_default {
1637 function = "SALT11";
1638 groups = "SALT11";
1639 };
1640
1641 pinctrl_salt12_default: salt12_default {
1642 function = "SALT12";
1643 groups = "SALT12";
1644 };
1645
1646 pinctrl_salt13_default: salt13_default {
1647 function = "SALT13";
1648 groups = "SALT13";
1649 };
1650
1651 pinctrl_salt14_default: salt14_default {
1652 function = "SALT14";
1653 groups = "SALT14";
1654 };
1655
1656 pinctrl_salt2_default: salt2_default {
1657 function = "SALT2";
1658 groups = "SALT2";
1659 };
1660
1661 pinctrl_salt3_default: salt3_default {
1662 function = "SALT3";
1663 groups = "SALT3";
1664 };
1665
1666 pinctrl_salt4_default: salt4_default {
1667 function = "SALT4";
1668 groups = "SALT4";
1669 };
1670
1671 pinctrl_salt5_default: salt5_default {
1672 function = "SALT5";
1673 groups = "SALT5";
1674 };
1675
1676 pinctrl_salt6_default: salt6_default {
1677 function = "SALT6";
1678 groups = "SALT6";
1679 };
1680
1681 pinctrl_salt7_default: salt7_default {
1682 function = "SALT7";
1683 groups = "SALT7";
1684 };
1685
1686 pinctrl_salt8_default: salt8_default {
1687 function = "SALT8";
1688 groups = "SALT8";
1689 };
1690
1691 pinctrl_salt9_default: salt9_default {
1692 function = "SALT9";
1693 groups = "SALT9";
1694 };
1695
1696 pinctrl_scl1_default: scl1_default {
1697 function = "SCL1";
1698 groups = "SCL1";
1699 };
1700
1701 pinctrl_scl2_default: scl2_default {
1702 function = "SCL2";
1703 groups = "SCL2";
1704 };
1705
1706 pinctrl_sd1_default: sd1_default {
1707 function = "SD1";
1708 groups = "SD1";
1709 };
1710
1711 pinctrl_sd2_default: sd2_default {
1712 function = "SD2";
1713 groups = "SD2";
1714 };
1715
1716 pinctrl_emmc_default: emmc_default {
1717 function = "EMMC";
1718 groups = "EMMC";
1719 };
1720
1721 pinctrl_emmcg8_default: emmcg8_default {
1722 function = "EMMCG8";
1723 groups = "EMMCG8";
1724 };
1725
1726 pinctrl_sda1_default: sda1_default {
1727 function = "SDA1";
1728 groups = "SDA1";
1729 };
1730
1731 pinctrl_sda2_default: sda2_default {
1732 function = "SDA2";
1733 groups = "SDA2";
1734 };
1735
1736 pinctrl_sgps1_default: sgps1_default {
1737 function = "SGPS1";
1738 groups = "SGPS1";
1739 };
1740
1741 pinctrl_sgps2_default: sgps2_default {
1742 function = "SGPS2";
1743 groups = "SGPS2";
1744 };
1745
1746 pinctrl_sioonctrl_default: sioonctrl_default {
1747 function = "SIOONCTRL";
1748 groups = "SIOONCTRL";
1749 };
1750
1751 pinctrl_siopbi_default: siopbi_default {
1752 function = "SIOPBI";
1753 groups = "SIOPBI";
1754 };
1755
1756 pinctrl_siopbo_default: siopbo_default {
1757 function = "SIOPBO";
1758 groups = "SIOPBO";
1759 };
1760
1761 pinctrl_siopwreq_default: siopwreq_default {
1762 function = "SIOPWREQ";
1763 groups = "SIOPWREQ";
1764 };
1765
1766 pinctrl_siopwrgd_default: siopwrgd_default {
1767 function = "SIOPWRGD";
1768 groups = "SIOPWRGD";
1769 };
1770
1771 pinctrl_sios3_default: sios3_default {
1772 function = "SIOS3";
1773 groups = "SIOS3";
1774 };
1775
1776 pinctrl_sios5_default: sios5_default {
1777 function = "SIOS5";
1778 groups = "SIOS5";
1779 };
1780
1781 pinctrl_siosci_default: siosci_default {
1782 function = "SIOSCI";
1783 groups = "SIOSCI";
1784 };
1785
1786 pinctrl_spi1_default: spi1_default {
1787 function = "SPI1";
1788 groups = "SPI1";
1789 };
1790
1791 pinctrl_spi1cs1_default: spi1cs1_default {
1792 function = "SPI1CS1";
1793 groups = "SPI1CS1";
1794 };
1795
1796 pinctrl_spi1debug_default: spi1debug_default {
1797 function = "SPI1DEBUG";
1798 groups = "SPI1DEBUG";
1799 };
1800
1801 pinctrl_spi1passthru_default: spi1passthru_default {
1802 function = "SPI1PASSTHRU";
1803 groups = "SPI1PASSTHRU";
1804 };
1805
1806 pinctrl_spi2ck_default: spi2ck_default {
1807 function = "SPI2CK";
1808 groups = "SPI2CK";
1809 };
1810
1811 pinctrl_spi2cs0_default: spi2cs0_default {
1812 function = "SPI2CS0";
1813 groups = "SPI2CS0";
1814 };
1815
1816 pinctrl_spi2cs1_default: spi2cs1_default {
1817 function = "SPI2CS1";
1818 groups = "SPI2CS1";
1819 };
1820
1821 pinctrl_spi2miso_default: spi2miso_default {
1822 function = "SPI2MISO";
1823 groups = "SPI2MISO";
1824 };
1825
1826 pinctrl_spi2mosi_default: spi2mosi_default {
1827 function = "SPI2MOSI";
1828 groups = "SPI2MOSI";
1829 };
1830
1831 pinctrl_timer3_default: timer3_default {
1832 function = "TIMER3";
1833 groups = "TIMER3";
1834 };
1835
1836 pinctrl_timer4_default: timer4_default {
1837 function = "TIMER4";
1838 groups = "TIMER4";
1839 };
1840
1841 pinctrl_timer5_default: timer5_default {
1842 function = "TIMER5";
1843 groups = "TIMER5";
1844 };
1845
1846 pinctrl_timer6_default: timer6_default {
1847 function = "TIMER6";
1848 groups = "TIMER6";
1849 };
1850
1851 pinctrl_timer7_default: timer7_default {
1852 function = "TIMER7";
1853 groups = "TIMER7";
1854 };
1855
1856 pinctrl_timer8_default: timer8_default {
1857 function = "TIMER8";
1858 groups = "TIMER8";
1859 };
1860
1861 pinctrl_txd1_default: txd1_default {
1862 function = "TXD1";
1863 groups = "TXD1";
1864 };
1865
1866 pinctrl_txd2_default: txd2_default {
1867 function = "TXD2";
1868 groups = "TXD2";
1869 };
1870
1871 pinctrl_txd3_default: txd3_default {
1872 function = "TXD3";
1873 groups = "TXD3";
1874 };
1875
1876 pinctrl_txd4_default: txd4_default {
1877 function = "TXD4";
1878 groups = "TXD4";
1879 };
1880
1881 pinctrl_uart6_default: uart6_default {
1882 function = "UART6";
1883 groups = "UART6";
1884 };
1885
1886 pinctrl_usbcki_default: usbcki_default {
1887 function = "USBCKI";
1888 groups = "USBCKI";
1889 };
1890
1891 pinctrl_usb2ah_default: usb2ah_default {
1892 function = "USB2AH";
1893 groups = "USB2AH";
1894 };
1895
1896 pinctrl_usb11bhid_default: usb11bhid_default {
1897 function = "USB11BHID";
1898 groups = "USB11BHID";
1899 };
1900
1901 pinctrl_usb2bh_default: usb2bh_default {
1902 function = "USB2BH";
1903 groups = "USB2BH";
1904 };
1905
1906 pinctrl_vgabiosrom_default: vgabiosrom_default {
1907 function = "VGABIOSROM";
1908 groups = "VGABIOSROM";
1909 };
1910
1911 pinctrl_vgahs_default: vgahs_default {
1912 function = "VGAHS";
1913 groups = "VGAHS";
1914 };
1915
1916 pinctrl_vgavs_default: vgavs_default {
1917 function = "VGAVS";
1918 groups = "VGAVS";
1919 };
1920
1921 pinctrl_vpi24_default: vpi24_default {
1922 function = "VPI24";
1923 groups = "VPI24";
1924 };
1925
1926 pinctrl_vpo_default: vpo_default {
1927 function = "VPO";
1928 groups = "VPO";
1929 };
1930
1931 pinctrl_wdtrst1_default: wdtrst1_default {
1932 function = "WDTRST1";
1933 groups = "WDTRST1";
1934 };
1935
1936 pinctrl_wdtrst2_default: wdtrst2_default {
1937 function = "WDTRST2";
1938 groups = "WDTRST2";
1939 };
1940
1941 pinctrl_pcie0rc_default: pcie0rc_default {
1942 function = "PCIE0RC";
1943 groups = "PCIE0RC";
1944 };
1945
1946 pinctrl_pcie1rc_default: pcie1rc_default {
1947 function = "PCIE1RC";
1948 groups = "PCIE1RC";
1949 };
1950};