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Dirk Behme53736ba2010-12-11 11:01:00 -05001/*
2 * Register definitions for the OMAP3 McSPI Controller
3 *
4 * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
5 *
6 * Parts taken from linux/drivers/spi/omap2_mcspi.c
7 * Copyright (C) 2005, 2006 Nokia Corporation
8 *
9 * Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
10 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020011 * SPDX-License-Identifier: GPL-2.0+
Dirk Behme53736ba2010-12-11 11:01:00 -050012 */
13
14#ifndef _OMAP3_SPI_H_
15#define _OMAP3_SPI_H_
16
Tom Rini4c0620b2012-08-08 14:29:51 -070017#ifdef CONFIG_AM33XX
18#define OMAP3_MCSPI1_BASE 0x48030100
19#define OMAP3_MCSPI2_BASE 0x481A0100
20#else
Dirk Behme53736ba2010-12-11 11:01:00 -050021#define OMAP3_MCSPI1_BASE 0x48098000
22#define OMAP3_MCSPI2_BASE 0x4809A000
23#define OMAP3_MCSPI3_BASE 0x480B8000
24#define OMAP3_MCSPI4_BASE 0x480BA000
Tom Rini4c0620b2012-08-08 14:29:51 -070025#endif
Dirk Behme53736ba2010-12-11 11:01:00 -050026
27#define OMAP3_MCSPI_MAX_FREQ 48000000
28
29/* OMAP3 McSPI registers */
30struct mcspi_channel {
31 unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */
32 unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */
33 unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */
34 unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */
35 unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */
36};
37
38struct mcspi {
39 unsigned char res1[0x10];
40 unsigned int sysconfig; /* 0x10 */
41 unsigned int sysstatus; /* 0x14 */
42 unsigned int irqstatus; /* 0x18 */
43 unsigned int irqenable; /* 0x1C */
44 unsigned int wakeupenable; /* 0x20 */
45 unsigned int syst; /* 0x24 */
46 unsigned int modulctrl; /* 0x28 */
47 struct mcspi_channel channel[4]; /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
48 /* channel1: 0x40 - 0x50, bus 0 & 1 */
49 /* channel2: 0x54 - 0x64, bus 0 & 1 */
50 /* channel3: 0x68 - 0x78, bus 0 */
51};
52
53/* per-register bitmasks */
54#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
55#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP (1 << 2)
56#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE (1 << 0)
57#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
58
59#define OMAP3_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
60
61#define OMAP3_MCSPI_MODULCTRL_SINGLE (1 << 0)
62#define OMAP3_MCSPI_MODULCTRL_MS (1 << 2)
63#define OMAP3_MCSPI_MODULCTRL_STEST (1 << 3)
64
65#define OMAP3_MCSPI_CHCONF_PHA (1 << 0)
66#define OMAP3_MCSPI_CHCONF_POL (1 << 1)
67#define OMAP3_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
68#define OMAP3_MCSPI_CHCONF_EPOL (1 << 6)
69#define OMAP3_MCSPI_CHCONF_WL_MASK (0x1f << 7)
70#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12)
71#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12)
72#define OMAP3_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
73#define OMAP3_MCSPI_CHCONF_DMAW (1 << 14)
74#define OMAP3_MCSPI_CHCONF_DMAR (1 << 15)
75#define OMAP3_MCSPI_CHCONF_DPE0 (1 << 16)
76#define OMAP3_MCSPI_CHCONF_DPE1 (1 << 17)
77#define OMAP3_MCSPI_CHCONF_IS (1 << 18)
78#define OMAP3_MCSPI_CHCONF_TURBO (1 << 19)
79#define OMAP3_MCSPI_CHCONF_FORCE (1 << 20)
80
81#define OMAP3_MCSPI_CHSTAT_RXS (1 << 0)
82#define OMAP3_MCSPI_CHSTAT_TXS (1 << 1)
83#define OMAP3_MCSPI_CHSTAT_EOT (1 << 2)
84
85#define OMAP3_MCSPI_CHCTRL_EN (1 << 0)
ajoycc1182b2012-11-17 21:10:15 +000086#define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
Dirk Behme53736ba2010-12-11 11:01:00 -050087
88#define OMAP3_MCSPI_WAKEUPENABLE_WKEN (1 << 0)
89
90struct omap3_spi_slave {
91 struct spi_slave slave;
92 struct mcspi *regs;
93 unsigned int freq;
94 unsigned int mode;
95};
96
97static inline struct omap3_spi_slave *to_omap3_spi(struct spi_slave *slave)
98{
99 return container_of(slave, struct omap3_spi_slave, slave);
100}
101
jacopo mondi08b5ab02011-03-02 05:13:22 +0000102int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, const u8 *txp,
103 u8 *rxp, unsigned long flags);
Dirk Behme53736ba2010-12-11 11:01:00 -0500104int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp,
105 unsigned long flags);
106int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp,
107 unsigned long flags);
108
109#endif /* _OMAP3_SPI_H_ */