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Kever Yangfa437432017-02-22 16:56:35 +08001Rockchip Dynamic Memory Controller Driver
2Required properties:
3- compatible: "rockchip,rk3399-dmc", "syscon"
4- rockchip,cru: this driver should access cru regs, so need get cru here
5- rockchip,pmucru: this driver should access pmucru regs, so need get pmucru here
6- rockchip,pmugrf: this driver should access pmugrf regs, so need get pmugrf here
7- rockchip,pmusgrf: this driver should access pmusgrf regs, so need get pmusgrf here
8- rockchip,cic: this driver should access cic regs, so need get cic here
9- reg: dynamic ram protocol controller(PCTL) address, PHY Independent(PI) address, phy controller(PHYCTL) address and memory schedule(MSCH) address
10- clock: must include clock specifiers corresponding to entries in the clock-names property.
11 Must contain
12 dmc_clk: for ddr working frequency
13- rockchip,sdram-params: SDRAM parameters, including all the information by ddr driver:
14 Must contain
15 Genarate by vendor tool and adjust for U-Boot dtsi.
16
17Example:
18 dmc: dmc {
19 u-boot,dm-pre-reloc;
20 compatible = "rockchip,rk3399-dmc";
21 devfreq-events = <&dfi>;
22 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
23 clocks = <&cru SCLK_DDRCLK>;
24 clock-names = "dmc_clk";
25 reg = <0x0 0xffa80000 0x0 0x0800
26 0x0 0xffa80800 0x0 0x1800
27 0x0 0xffa82000 0x0 0x2000
28 0x0 0xffa84000 0x0 0x1000
29 0x0 0xffa88000 0x0 0x0800
30 0x0 0xffa88800 0x0 0x1800
31 0x0 0xffa8a000 0x0 0x2000
32 0x0 0xffa8c000 0x0 0x1000>;
33 };
34
35 &dmc {
36 rockchip,sdram-params = <
37 0x2
38 0xa
39 0x3
40 ...
41 >;
42 };