| Yash Shah | 0dae9e2 | 2020-04-23 16:57:15 +0530 | [diff] [blame] | 1 | SiFive PWM controller |
| 2 | |
| 3 | Unlike most other PWM controllers, the SiFive PWM controller currently only |
| 4 | supports one period for all channels in the PWM. All PWMs need to run at |
| 5 | the same period. The period also has significant restrictions on the values |
| 6 | it can achieve, which the driver rounds to the nearest achievable period. |
| 7 | PWM RTL that corresponds to the IP block version numbers can be found |
| 8 | here: |
| 9 | |
| 10 | https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm |
| 11 | |
| 12 | Required properties: |
| 13 | - compatible: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". |
| 14 | Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive |
| 15 | PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the |
| 16 | SiFive PWM v0 IP block with no chip integration tweaks. |
| 17 | - reg: physical base address and length of the controller's registers |
| 18 | - clocks: Should contain a clock identifier for the PWM's parent clock. |
| 19 | - #pwm-cells: Should be 3. |
| 20 | - interrupts: one interrupt per PWM channel |
| 21 | |
| 22 | Examples: |
| 23 | |
| 24 | pwm: pwm@10020000 { |
| 25 | compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; |
| 26 | reg = <0x0 0x10020000 0x0 0x1000>; |
| 27 | clocks = <&tlclk>; |
| 28 | interrupt-parent = <&plic>; |
| 29 | interrupts = <42 43 44 45>; |
| 30 | #pwm-cells = <3>; |
| 31 | }; |