| Marek Vasut | a3c31e9 | 2019-03-04 21:23:25 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ |
| Marek Vasut | a3fb9ff | 2018-01-07 20:17:53 +0100 | [diff] [blame] | 2 | * |
| Marek Vasut | a3c31e9 | 2019-03-04 21:23:25 +0100 | [diff] [blame] | 3 | * Copyright (C) 2015 Renesas Electronics Corp. |
| Marek Vasut | a3fb9ff | 2018-01-07 20:17:53 +0100 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ |
| 7 | #define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ |
| 8 | |
| 9 | #include <dt-bindings/clock/renesas-cpg-mssr.h> |
| 10 | |
| 11 | /* r8a7792 CPG Core Clocks */ |
| 12 | #define R8A7792_CLK_Z 0 |
| 13 | #define R8A7792_CLK_ZG 1 |
| 14 | #define R8A7792_CLK_ZTR 2 |
| 15 | #define R8A7792_CLK_ZTRD2 3 |
| 16 | #define R8A7792_CLK_ZT 4 |
| 17 | #define R8A7792_CLK_ZX 5 |
| 18 | #define R8A7792_CLK_ZS 6 |
| 19 | #define R8A7792_CLK_HP 7 |
| 20 | #define R8A7792_CLK_I 8 |
| 21 | #define R8A7792_CLK_B 9 |
| 22 | #define R8A7792_CLK_LB 10 |
| 23 | #define R8A7792_CLK_P 11 |
| 24 | #define R8A7792_CLK_CL 12 |
| 25 | #define R8A7792_CLK_M2 13 |
| 26 | #define R8A7792_CLK_IMP 14 |
| 27 | #define R8A7792_CLK_ZB3 15 |
| 28 | #define R8A7792_CLK_ZB3D2 16 |
| 29 | #define R8A7792_CLK_DDR 17 |
| 30 | #define R8A7792_CLK_SD 18 |
| 31 | #define R8A7792_CLK_MP 19 |
| 32 | #define R8A7792_CLK_QSPI 20 |
| 33 | #define R8A7792_CLK_CP 21 |
| 34 | #define R8A7792_CLK_CPEX 22 |
| 35 | #define R8A7792_CLK_RCAN 23 |
| 36 | #define R8A7792_CLK_R 24 |
| 37 | #define R8A7792_CLK_OSC 25 |
| 38 | |
| 39 | #endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */ |