blob: 55e9de01ae5149b20a2fc19d6296964e226bf3ea [file] [log] [blame]
Marian Balakowicz991425f2006-03-14 16:24:38 +01001/*
2 * (C) Copyright 2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * mpc8349emds board configuration file
26 *
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
Marian Balakowicz991425f2006-03-14 16:24:38 +010032/*
33 * High Level Configuration Options
34 */
35#define CONFIG_E300 1 /* E300 Family */
Peter Tyser0f898602009-05-22 17:23:24 -050036#define CONFIG_MPC83xx 1 /* MPC83xx family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050037#define CONFIG_MPC834x 1 /* MPC834x family */
Marian Balakowicz991425f2006-03-14 16:24:38 +010038#define CONFIG_MPC8349 1 /* MPC8349 specific */
39#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
40
Marian Balakowicz991425f2006-03-14 16:24:38 +010041#define PCI_66M
42#ifdef PCI_66M
43#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
44#else
45#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
46#endif
47
Ira W. Snyder447ad572008-08-22 11:00:15 -070048#ifdef CONFIG_PCISLAVE
49#define CONFIG_PCI
50#define CONFIG_83XX_PCICLK 66666666 /* in Hz */
51#endif /* CONFIG_PCISLAVE */
52
Marian Balakowicz991425f2006-03-14 16:24:38 +010053#ifndef CONFIG_SYS_CLK_FREQ
54#ifdef PCI_66M
55#define CONFIG_SYS_CLK_FREQ 66000000
Kumar Gala8fe9bf62006-04-20 13:45:32 -050056#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
Marian Balakowicz991425f2006-03-14 16:24:38 +010057#else
58#define CONFIG_SYS_CLK_FREQ 33000000
Kumar Gala8fe9bf62006-04-20 13:45:32 -050059#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
Marian Balakowicz991425f2006-03-14 16:24:38 +010060#endif
61#endif
62
63#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
64
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_IMMR 0xE0000000
Marian Balakowicz991425f2006-03-14 16:24:38 +010066
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
68#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
69#define CONFIG_SYS_MEMTEST_END 0x00100000
Marian Balakowicz991425f2006-03-14 16:24:38 +010070
71/*
72 * DDR Setup
73 */
Xie Xiaobo8d172c02007-02-14 18:26:44 +080074#define CONFIG_DDR_ECC /* support DDR ECC function */
Marian Balakowiczd326f4a2006-03-16 15:19:35 +010075#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
Marian Balakowicz991425f2006-03-14 16:24:38 +010076#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
77
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010078/*
79 * 32-bit data path mode.
Wolfgang Denkcf48eb92006-04-16 10:51:58 +020080 *
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010081 * Please note that using this mode for devices with the real density of 64-bit
82 * effectively reduces the amount of available memory due to the effect of
83 * wrapping around while translating address to row/columns, for example in the
84 * 256MB module the upper 128MB get aliased with contents of the lower
85 * 128MB); normally this define should be used for devices with real 32-bit
Wolfgang Denkcf48eb92006-04-16 10:51:58 +020086 * data path.
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010087 */
88#undef CONFIG_DDR_32BIT
89
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
91#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
92#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
93#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
Xie Xiaobo8d172c02007-02-14 18:26:44 +080094 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
Marian Balakowicz991425f2006-03-14 16:24:38 +010095#undef CONFIG_DDR_2T_TIMING
96
Xie Xiaobo8d172c02007-02-14 18:26:44 +080097/*
98 * DDRCDR - DDR Control Driver Register
99 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800101
Marian Balakowicz991425f2006-03-14 16:24:38 +0100102#if defined(CONFIG_SPD_EEPROM)
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100103/*
104 * Determine DDR configuration from I2C interface.
105 */
106#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100107#else
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100108/*
109 * Manually set up DDR parameters
110 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_DDR_SIZE 256 /* MB */
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800112#if defined(CONFIG_DDR_II)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_DDRCDR 0x80080001
114#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
115#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
116#define CONFIG_SYS_DDR_TIMING_0 0x00220802
117#define CONFIG_SYS_DDR_TIMING_1 0x38357322
118#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
119#define CONFIG_SYS_DDR_TIMING_3 0x00000000
120#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
121#define CONFIG_SYS_DDR_MODE 0x47d00432
122#define CONFIG_SYS_DDR_MODE2 0x8000c000
123#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
124#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
125#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800126#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
128#define CONFIG_SYS_DDR_TIMING_1 0x36332321
129#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
130#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
131#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100132
133#if defined(CONFIG_DDR_32BIT)
134/* set burst length to 8 for 32-bit data path */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100136#else
137/* the default burst length is 4 - for 64-bit data path */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100139#endif
Marian Balakowicz991425f2006-03-14 16:24:38 +0100140#endif
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800141#endif
Marian Balakowicz991425f2006-03-14 16:24:38 +0100142
143/*
144 * SDRAM on the Local Bus
145 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
147#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100148
149/*
150 * FLASH on the Local Bus
151 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200153#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
155#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
156#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
157/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800160 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
Marian Balakowicz991425f2006-03-14 16:24:38 +0100161 BR_V) /* valid */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
Anton Vorontsovf9023af2008-05-29 18:14:56 +0400163 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800164 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */
166#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100167
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
169#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#undef CONFIG_SYS_FLASH_CHECKSUM
172#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
173#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
178#define CONFIG_SYS_RAMBOOT
Marian Balakowicz991425f2006-03-14 16:24:38 +0100179#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#undef CONFIG_SYS_RAMBOOT
Marian Balakowicz991425f2006-03-14 16:24:38 +0100181#endif
182
183/*
184 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
185 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_BCSR 0xE2400000
187#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */
188#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
189#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */
190#define CONFIG_SYS_OR1_PRELIM 0xFFFFE8F0 /* length 32K */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_INIT_RAM_LOCK 1
193#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
194#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
Marian Balakowicz991425f2006-03-14 16:24:38 +0100195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
197#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
198#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Marian Balakowicz991425f2006-03-14 16:24:38 +0100199
Kim Phillips4a9932a2009-07-07 18:04:21 -0500200#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100202
203/*
204 * Local Bus LCRR and LBCR regs
205 * LCRR: DLL bypass, Clock divider is 4
206 * External Local Bus rate is
207 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
208 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500209#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
210#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_LBC_LBCR 0x00000000
Marian Balakowicz991425f2006-03-14 16:24:38 +0100212
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800213/*
214 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215 * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800216 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#undef CONFIG_SYS_LB_SDRAM
Marian Balakowicz991425f2006-03-14 16:24:38 +0100218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#ifdef CONFIG_SYS_LB_SDRAM
Marian Balakowicz991425f2006-03-14 16:24:38 +0100220/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
221/*
222 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Marian Balakowicz991425f2006-03-14 16:24:38 +0100224 *
225 * For BR2, need:
226 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
227 * port-size = 32-bits = BR2[19:20] = 11
228 * no parity checking = BR2[21:22] = 00
229 * SDRAM for MSEL = BR2[24:26] = 011
230 * Valid = BR[31] = 1
231 *
232 * 0 4 8 12 16 20 24 28
233 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
234 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
Marian Balakowicz991425f2006-03-14 16:24:38 +0100236 * FIXME: the top 17 bits of BR2.
237 */
238
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
240#define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000
241#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100242
243/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Marian Balakowicz991425f2006-03-14 16:24:38 +0100245 *
246 * For OR2, need:
247 * 64MB mask for AM, OR2[0:7] = 1111 1100
248 * XAM, OR2[17:18] = 11
249 * 9 columns OR2[19-21] = 010
250 * 13 rows OR2[23-25] = 100
251 * EAD set for extra time OR[31] = 1
252 *
253 * 0 4 8 12 16 20 24 28
254 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
255 */
256
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_OR2_PRELIM 0xFC006901
Marian Balakowicz991425f2006-03-14 16:24:38 +0100258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
260#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100261
Kumar Gala540dcf12009-03-26 01:34:39 -0500262#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFEN \
263 | LSDMR_BSMA1516 \
264 | LSDMR_RFCR8 \
265 | LSDMR_PRETOACT6 \
266 | LSDMR_ACTTORW3 \
267 | LSDMR_BL8 \
268 | LSDMR_WRC3 \
269 | LSDMR_CL3 \
Marian Balakowicz991425f2006-03-14 16:24:38 +0100270 )
271
272/*
273 * SDRAM Controller configuration sequence.
274 */
Kumar Gala540dcf12009-03-26 01:34:39 -0500275#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
276#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
277#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
278#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
279#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100280#endif
281
282/*
283 * Serial Port
284 */
285#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_NS16550
287#define CONFIG_SYS_NS16550_SERIAL
288#define CONFIG_SYS_NS16550_REG_SIZE 1
289#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100290
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_BAUDRATE_TABLE \
Marian Balakowicz991425f2006-03-14 16:24:38 +0100292 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
293
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
295#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100296
Kim Phillips22d71a72007-02-27 18:41:08 -0600297#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500298#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100299/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_HUSH_PARSER
301#ifdef CONFIG_SYS_HUSH_PARSER
302#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Marian Balakowicz991425f2006-03-14 16:24:38 +0100303#endif
304
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600305/* pass open firmware flat tree */
Kim Phillips35cc4e42007-08-15 22:30:39 -0500306#define CONFIG_OF_LIBFDT 1
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600307#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600308#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600309
Marian Balakowicz991425f2006-03-14 16:24:38 +0100310/* I2C */
311#define CONFIG_HARD_I2C /* I2C with hardware support*/
312#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Timur Tabibe5e6182006-11-03 19:15:00 -0600313#define CONFIG_FSL_I2C
Ben Warrenb24f1192006-09-07 16:51:04 -0400314#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
316#define CONFIG_SYS_I2C_SLAVE 0x7F
317#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
318#define CONFIG_SYS_I2C_OFFSET 0x3000
319#define CONFIG_SYS_I2C2_OFFSET 0x3100
Marian Balakowicz991425f2006-03-14 16:24:38 +0100320
Ben Warren80ddd222008-01-16 22:37:42 -0500321/* SPI */
Ben Warren8931ab12008-01-26 23:41:19 -0500322#define CONFIG_MPC8XXX_SPI
Ben Warren80ddd222008-01-16 22:37:42 -0500323#undef CONFIG_SOFT_SPI /* SPI bit-banged */
Ben Warren80ddd222008-01-16 22:37:42 -0500324
325/* GPIOs. Used as SPI chip selects */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_GPIO1_PRELIM
327#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
328#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
Ben Warren80ddd222008-01-16 22:37:42 -0500329
Marian Balakowicz991425f2006-03-14 16:24:38 +0100330/* TSEC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_TSEC1_OFFSET 0x24000
332#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
333#define CONFIG_SYS_TSEC2_OFFSET 0x25000
334#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100335
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500336/* USB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100338
339/*
340 * General PCI
341 * Addresses are mapped 1-1.
342 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
344#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
345#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
346#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
347#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
348#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
349#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
350#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
351#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100352
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
354#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
355#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
356#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
357#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
358#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
359#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
360#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
361#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100362
363#if defined(CONFIG_PCI)
364
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500365#define PCI_ONE_PCI1
Marian Balakowicz991425f2006-03-14 16:24:38 +0100366#if defined(PCI_64BIT)
367#undef PCI_ALL_PCI1
368#undef PCI_TWO_PCI1
369#undef PCI_ONE_PCI1
370#endif
371
372#define CONFIG_NET_MULTI
373#define CONFIG_PCI_PNP /* do pci plug-and-play */
Ira W. Snyder162338e2008-08-22 11:00:13 -0700374#define CONFIG_83XX_PCI_STREAMING
Marian Balakowicz991425f2006-03-14 16:24:38 +0100375
376#undef CONFIG_EEPRO100
377#undef CONFIG_TULIP
378
379#if !defined(CONFIG_PCI_PNP)
380 #define PCI_ENET0_IOADDR 0xFIXME
381 #define PCI_ENET0_MEMADDR 0xFIXME
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200382 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100383#endif
384
385#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100387
388#endif /* CONFIG_PCI */
389
390/*
391 * TSEC configuration
392 */
393#define CONFIG_TSEC_ENET /* TSEC ethernet support */
394
395#if defined(CONFIG_TSEC_ENET)
396#ifndef CONFIG_NET_MULTI
397#define CONFIG_NET_MULTI 1
398#endif
399
400#define CONFIG_GMII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500401#define CONFIG_TSEC1 1
402#define CONFIG_TSEC1_NAME "TSEC0"
403#define CONFIG_TSEC2 1
404#define CONFIG_TSEC2_NAME "TSEC1"
Marian Balakowicz991425f2006-03-14 16:24:38 +0100405#define TSEC1_PHY_ADDR 0
406#define TSEC2_PHY_ADDR 1
407#define TSEC1_PHYIDX 0
408#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500409#define TSEC1_FLAGS TSEC_GIGABIT
410#define TSEC2_FLAGS TSEC_GIGABIT
Marian Balakowicz991425f2006-03-14 16:24:38 +0100411
412/* Options are: TSEC[0-1] */
413#define CONFIG_ETHPRIME "TSEC0"
414
415#endif /* CONFIG_TSEC_ENET */
416
417/*
418 * Configure on-board RTC
419 */
420#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100422
423/*
424 * Environment
425 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200427 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200429 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
430 #define CONFIG_ENV_SIZE 0x2000
Marian Balakowicz991425f2006-03-14 16:24:38 +0100431
432/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200433#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
434#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100435
436#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200438 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200440 #define CONFIG_ENV_SIZE 0x2000
Marian Balakowicz991425f2006-03-14 16:24:38 +0100441#endif
442
443#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100445
Jon Loeliger8ea54992007-07-04 22:30:06 -0500446
447/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500448 * BOOTP options
449 */
450#define CONFIG_BOOTP_BOOTFILESIZE
451#define CONFIG_BOOTP_BOOTPATH
452#define CONFIG_BOOTP_GATEWAY
453#define CONFIG_BOOTP_HOSTNAME
454
455
456/*
Jon Loeliger8ea54992007-07-04 22:30:06 -0500457 * Command line configuration.
458 */
459#include <config_cmd_default.h>
460
461#define CONFIG_CMD_PING
462#define CONFIG_CMD_I2C
463#define CONFIG_CMD_DATE
464#define CONFIG_CMD_MII
465
Marian Balakowicz991425f2006-03-14 16:24:38 +0100466#if defined(CONFIG_PCI)
Jon Loeliger8ea54992007-07-04 22:30:06 -0500467 #define CONFIG_CMD_PCI
Marian Balakowicz991425f2006-03-14 16:24:38 +0100468#endif
469
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500471 #undef CONFIG_CMD_SAVEENV
Jon Loeliger8ea54992007-07-04 22:30:06 -0500472 #undef CONFIG_CMD_LOADS
473#endif
474
Marian Balakowicz991425f2006-03-14 16:24:38 +0100475
476#undef CONFIG_WATCHDOG /* watchdog disabled */
477
478/*
479 * Miscellaneous configurable options
480 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200481#define CONFIG_SYS_LONGHELP /* undef to save memory */
482#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
483#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100484
Jon Loeliger8ea54992007-07-04 22:30:06 -0500485#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200486 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100487#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200488 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100489#endif
490
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200491#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
492#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
493#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
494#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100495
496/*
497 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700498 * have to be in the first 256 MB of memory, since this is
Marian Balakowicz991425f2006-03-14 16:24:38 +0100499 * the maximum mapped by the Linux kernel during initialization.
500 */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700501#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
Marian Balakowicz991425f2006-03-14 16:24:38 +0100502
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200503#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100504
505#if 1 /*528/264*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200506#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100507 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
508 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500509 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100510 HRCWL_VCO_1X2 |\
511 HRCWL_CORE_TO_CSB_2X1)
512#elif 0 /*396/132*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200513#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100514 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
515 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500516 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100517 HRCWL_VCO_1X4 |\
518 HRCWL_CORE_TO_CSB_3X1)
519#elif 0 /*264/132*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200520#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100521 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
522 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500523 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100524 HRCWL_VCO_1X4 |\
525 HRCWL_CORE_TO_CSB_2X1)
526#elif 0 /*132/132*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100528 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
529 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500530 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100531 HRCWL_VCO_1X4 |\
532 HRCWL_CORE_TO_CSB_1X1)
533#elif 0 /*264/264 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200534#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100535 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
536 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500537 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100538 HRCWL_VCO_1X4 |\
539 HRCWL_CORE_TO_CSB_1X1)
540#endif
541
Ira W. Snyder447ad572008-08-22 11:00:15 -0700542#ifdef CONFIG_PCISLAVE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200543#define CONFIG_SYS_HRCW_HIGH (\
Ira W. Snyder447ad572008-08-22 11:00:15 -0700544 HRCWH_PCI_AGENT |\
545 HRCWH_64_BIT_PCI |\
546 HRCWH_PCI1_ARBITER_DISABLE |\
547 HRCWH_PCI2_ARBITER_DISABLE |\
548 HRCWH_CORE_ENABLE |\
549 HRCWH_FROM_0X00000100 |\
550 HRCWH_BOOTSEQ_DISABLE |\
551 HRCWH_SW_WATCHDOG_DISABLE |\
552 HRCWH_ROM_LOC_LOCAL_16BIT |\
553 HRCWH_TSEC1M_IN_GMII |\
554 HRCWH_TSEC2M_IN_GMII )
555#else
Marian Balakowicz991425f2006-03-14 16:24:38 +0100556#if defined(PCI_64BIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200557#define CONFIG_SYS_HRCW_HIGH (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100558 HRCWH_PCI_HOST |\
559 HRCWH_64_BIT_PCI |\
560 HRCWH_PCI1_ARBITER_ENABLE |\
561 HRCWH_PCI2_ARBITER_DISABLE |\
562 HRCWH_CORE_ENABLE |\
563 HRCWH_FROM_0X00000100 |\
564 HRCWH_BOOTSEQ_DISABLE |\
565 HRCWH_SW_WATCHDOG_DISABLE |\
566 HRCWH_ROM_LOC_LOCAL_16BIT |\
567 HRCWH_TSEC1M_IN_GMII |\
568 HRCWH_TSEC2M_IN_GMII )
569#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200570#define CONFIG_SYS_HRCW_HIGH (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100571 HRCWH_PCI_HOST |\
572 HRCWH_32_BIT_PCI |\
573 HRCWH_PCI1_ARBITER_ENABLE |\
574 HRCWH_PCI2_ARBITER_ENABLE |\
575 HRCWH_CORE_ENABLE |\
576 HRCWH_FROM_0X00000100 |\
577 HRCWH_BOOTSEQ_DISABLE |\
578 HRCWH_SW_WATCHDOG_DISABLE |\
579 HRCWH_ROM_LOC_LOCAL_16BIT |\
580 HRCWH_TSEC1M_IN_GMII |\
581 HRCWH_TSEC2M_IN_GMII )
Ira W. Snyder447ad572008-08-22 11:00:15 -0700582#endif /* PCI_64BIT */
583#endif /* CONFIG_PCISLAVE */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100584
Lee Nippera5fe5142008-04-25 15:44:45 -0500585/*
586 * System performance
587 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200588#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
589#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
590#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
591#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
592#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
593#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
Lee Nippera5fe5142008-04-25 15:44:45 -0500594
Marian Balakowicz991425f2006-03-14 16:24:38 +0100595/* System IO Config */
Kim Phillips3c9b1ee2009-06-05 14:11:33 -0500596#define CONFIG_SYS_SICRH 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200597#define CONFIG_SYS_SICRL SICRL_LDP_A
Marian Balakowicz991425f2006-03-14 16:24:38 +0100598
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200599#define CONFIG_SYS_HID0_INIT 0x000000000
Kim Phillips1a2e2032010-04-20 19:37:54 -0500600#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
601 HID0_ENABLE_INSTRUCTION_CACHE)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100602
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200603/* #define CONFIG_SYS_HID0_FINAL (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100604 HID0_ENABLE_INSTRUCTION_CACHE |\
605 HID0_ENABLE_M_BIT |\
606 HID0_ENABLE_ADDRESS_BROADCAST ) */
607
608
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200609#define CONFIG_SYS_HID2 HID2_HBE
Becky Bruce31d82672008-05-08 19:02:12 -0500610#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100611
612/* DDR @ 0x00000000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200613#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
614#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100615
616/* PCI @ 0x80000000 */
617#ifdef CONFIG_PCI
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200618#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
619#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
620#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
621#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100622#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200623#define CONFIG_SYS_IBAT1L (0)
624#define CONFIG_SYS_IBAT1U (0)
625#define CONFIG_SYS_IBAT2L (0)
626#define CONFIG_SYS_IBAT2U (0)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100627#endif
628
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500629#ifdef CONFIG_MPC83XX_PCI2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200630#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
631#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
632#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
633#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500634#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200635#define CONFIG_SYS_IBAT3L (0)
636#define CONFIG_SYS_IBAT3U (0)
637#define CONFIG_SYS_IBAT4L (0)
638#define CONFIG_SYS_IBAT4U (0)
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500639#endif
Marian Balakowicz991425f2006-03-14 16:24:38 +0100640
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500641/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200642#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
643#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100644
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500645/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
Scott Woodc1230982009-03-31 17:49:36 -0500646#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
647 BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200648#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100649
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200650#define CONFIG_SYS_IBAT7L (0)
651#define CONFIG_SYS_IBAT7U (0)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100652
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200653#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
654#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
655#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
656#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
657#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
658#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
659#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
660#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
661#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
662#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
663#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
664#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
665#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
666#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
667#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
668#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Marian Balakowicz991425f2006-03-14 16:24:38 +0100669
670/*
671 * Internal Definitions
672 *
673 * Boot Flags
674 */
675#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
676#define BOOTFLAG_WARM 0x02 /* Software reboot */
677
Jon Loeliger8ea54992007-07-04 22:30:06 -0500678#if defined(CONFIG_CMD_KGDB)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100679#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
680#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
681#endif
682
683/*
684 * Environment Configuration
685 */
686#define CONFIG_ENV_OVERWRITE
687
688#if defined(CONFIG_TSEC_ENET)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100689#define CONFIG_HAS_ETH1
Andy Fleming10327dc2007-08-16 16:35:02 -0500690#define CONFIG_HAS_ETH0
Marian Balakowicz991425f2006-03-14 16:24:38 +0100691#endif
692
Marian Balakowicz991425f2006-03-14 16:24:38 +0100693#define CONFIG_HOSTNAME mpc8349emds
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600694#define CONFIG_ROOTPATH /nfsroot/rootfs
695#define CONFIG_BOOTFILE uImage
Marian Balakowicz991425f2006-03-14 16:24:38 +0100696
Kim Phillips79f516b2009-08-21 16:34:38 -0500697#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100698
699#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
700#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
701
702#define CONFIG_BAUDRATE 115200
703
704#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100705 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Marian Balakowicz991425f2006-03-14 16:24:38 +0100706 "echo"
707
708#define CONFIG_EXTRA_ENV_SETTINGS \
709 "netdev=eth0\0" \
710 "hostname=mpc8349emds\0" \
711 "nfsargs=setenv bootargs root=/dev/nfs rw " \
712 "nfsroot=${serverip}:${rootpath}\0" \
713 "ramargs=setenv bootargs root=/dev/ram rw\0" \
714 "addip=setenv bootargs ${bootargs} " \
715 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
716 ":${hostname}:${netdev}:off panic=1\0" \
717 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
718 "flash_nfs=run nfsargs addip addtty;" \
719 "bootm ${kernel_addr}\0" \
720 "flash_self=run ramargs addip addtty;" \
721 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
722 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
723 "bootm\0" \
Marian Balakowicz991425f2006-03-14 16:24:38 +0100724 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
725 "update=protect off fe000000 fe03ffff; " \
726 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100727 "upd=run load update\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500728 "fdtaddr=780000\0" \
Kim Phillipscc861f72009-08-26 21:25:46 -0500729 "fdtfile=mpc834x_mds.dtb\0" \
Marian Balakowicz991425f2006-03-14 16:24:38 +0100730 ""
731
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600732#define CONFIG_NFSBOOTCOMMAND \
733 "setenv bootargs root=/dev/nfs rw " \
734 "nfsroot=$serverip:$rootpath " \
735 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
736 "console=$consoledev,$baudrate $othbootargs;" \
737 "tftp $loadaddr $bootfile;" \
738 "tftp $fdtaddr $fdtfile;" \
739 "bootm $loadaddr - $fdtaddr"
740
741#define CONFIG_RAMBOOTCOMMAND \
742 "setenv bootargs root=/dev/ram rw " \
743 "console=$consoledev,$baudrate $othbootargs;" \
744 "tftp $ramdiskaddr $ramdiskfile;" \
745 "tftp $loadaddr $bootfile;" \
746 "tftp $fdtaddr $fdtfile;" \
747 "bootm $loadaddr $ramdiskaddr $fdtaddr"
748
Marian Balakowicz991425f2006-03-14 16:24:38 +0100749#define CONFIG_BOOTCOMMAND "run flash_self"
750
751#endif /* __CONFIG_H */