blob: 357bedeebfac45e451a57ca736cf993bd2698c24 [file] [log] [blame]
Tom Rini57cd6812015-07-31 19:55:12 -04001/*
2 * Device Tree Source for DRA7xx clock data
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10&cm_core_aon_clocks {
11 atl_clkin0_ck: atl_clkin0_ck {
12 #clock-cells = <0>;
13 compatible = "ti,dra7-atl-clock";
14 clocks = <&atl_gfclk_mux>;
15 };
16
17 atl_clkin1_ck: atl_clkin1_ck {
18 #clock-cells = <0>;
19 compatible = "ti,dra7-atl-clock";
20 clocks = <&atl_gfclk_mux>;
21 };
22
23 atl_clkin2_ck: atl_clkin2_ck {
24 #clock-cells = <0>;
25 compatible = "ti,dra7-atl-clock";
26 clocks = <&atl_gfclk_mux>;
27 };
28
29 atl_clkin3_ck: atl_clkin3_ck {
30 #clock-cells = <0>;
31 compatible = "ti,dra7-atl-clock";
32 clocks = <&atl_gfclk_mux>;
33 };
34
35 hdmi_clkin_ck: hdmi_clkin_ck {
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
38 clock-frequency = <0>;
39 };
40
41 mlb_clkin_ck: mlb_clkin_ck {
42 #clock-cells = <0>;
43 compatible = "fixed-clock";
44 clock-frequency = <0>;
45 };
46
47 mlbp_clkin_ck: mlbp_clkin_ck {
48 #clock-cells = <0>;
49 compatible = "fixed-clock";
50 clock-frequency = <0>;
51 };
52
53 pciesref_acs_clk_ck: pciesref_acs_clk_ck {
54 #clock-cells = <0>;
55 compatible = "fixed-clock";
56 clock-frequency = <100000000>;
57 };
58
59 ref_clkin0_ck: ref_clkin0_ck {
60 #clock-cells = <0>;
61 compatible = "fixed-clock";
62 clock-frequency = <0>;
63 };
64
65 ref_clkin1_ck: ref_clkin1_ck {
66 #clock-cells = <0>;
67 compatible = "fixed-clock";
68 clock-frequency = <0>;
69 };
70
71 ref_clkin2_ck: ref_clkin2_ck {
72 #clock-cells = <0>;
73 compatible = "fixed-clock";
74 clock-frequency = <0>;
75 };
76
77 ref_clkin3_ck: ref_clkin3_ck {
78 #clock-cells = <0>;
79 compatible = "fixed-clock";
80 clock-frequency = <0>;
81 };
82
83 rmii_clk_ck: rmii_clk_ck {
84 #clock-cells = <0>;
85 compatible = "fixed-clock";
86 clock-frequency = <0>;
87 };
88
89 sdvenc_clkin_ck: sdvenc_clkin_ck {
90 #clock-cells = <0>;
91 compatible = "fixed-clock";
92 clock-frequency = <0>;
93 };
94
95 secure_32k_clk_src_ck: secure_32k_clk_src_ck {
96 #clock-cells = <0>;
97 compatible = "fixed-clock";
98 clock-frequency = <32768>;
99 };
100
101 sys_32k_ck: sys_32k_ck {
102 #clock-cells = <0>;
103 compatible = "fixed-clock";
104 clock-frequency = <32768>;
105 };
106
107 virt_12000000_ck: virt_12000000_ck {
108 #clock-cells = <0>;
109 compatible = "fixed-clock";
110 clock-frequency = <12000000>;
111 };
112
113 virt_13000000_ck: virt_13000000_ck {
114 #clock-cells = <0>;
115 compatible = "fixed-clock";
116 clock-frequency = <13000000>;
117 };
118
119 virt_16800000_ck: virt_16800000_ck {
120 #clock-cells = <0>;
121 compatible = "fixed-clock";
122 clock-frequency = <16800000>;
123 };
124
125 virt_19200000_ck: virt_19200000_ck {
126 #clock-cells = <0>;
127 compatible = "fixed-clock";
128 clock-frequency = <19200000>;
129 };
130
131 virt_20000000_ck: virt_20000000_ck {
132 #clock-cells = <0>;
133 compatible = "fixed-clock";
134 clock-frequency = <20000000>;
135 };
136
137 virt_26000000_ck: virt_26000000_ck {
138 #clock-cells = <0>;
139 compatible = "fixed-clock";
140 clock-frequency = <26000000>;
141 };
142
143 virt_27000000_ck: virt_27000000_ck {
144 #clock-cells = <0>;
145 compatible = "fixed-clock";
146 clock-frequency = <27000000>;
147 };
148
149 virt_38400000_ck: virt_38400000_ck {
150 #clock-cells = <0>;
151 compatible = "fixed-clock";
152 clock-frequency = <38400000>;
153 };
154
155 sys_clkin2: sys_clkin2 {
156 #clock-cells = <0>;
157 compatible = "fixed-clock";
158 clock-frequency = <22579200>;
159 };
160
161 usb_otg_clkin_ck: usb_otg_clkin_ck {
162 #clock-cells = <0>;
163 compatible = "fixed-clock";
164 clock-frequency = <0>;
165 };
166
167 video1_clkin_ck: video1_clkin_ck {
168 #clock-cells = <0>;
169 compatible = "fixed-clock";
170 clock-frequency = <0>;
171 };
172
173 video1_m2_clkin_ck: video1_m2_clkin_ck {
174 #clock-cells = <0>;
175 compatible = "fixed-clock";
176 clock-frequency = <0>;
177 };
178
179 video2_clkin_ck: video2_clkin_ck {
180 #clock-cells = <0>;
181 compatible = "fixed-clock";
182 clock-frequency = <0>;
183 };
184
185 video2_m2_clkin_ck: video2_m2_clkin_ck {
186 #clock-cells = <0>;
187 compatible = "fixed-clock";
188 clock-frequency = <0>;
189 };
190
191 dpll_abe_ck: dpll_abe_ck {
192 #clock-cells = <0>;
193 compatible = "ti,omap4-dpll-m4xen-clock";
194 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
195 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
196 };
197
198 dpll_abe_x2_ck: dpll_abe_x2_ck {
199 #clock-cells = <0>;
200 compatible = "ti,omap4-dpll-x2-clock";
201 clocks = <&dpll_abe_ck>;
202 };
203
204 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
205 #clock-cells = <0>;
206 compatible = "ti,divider-clock";
207 clocks = <&dpll_abe_x2_ck>;
208 ti,max-div = <31>;
209 ti,autoidle-shift = <8>;
210 reg = <0x01f0>;
211 ti,index-starts-at-one;
212 ti,invert-autoidle-bit;
213 };
214
215 abe_clk: abe_clk {
216 #clock-cells = <0>;
217 compatible = "ti,divider-clock";
218 clocks = <&dpll_abe_m2x2_ck>;
219 ti,max-div = <4>;
220 reg = <0x0108>;
221 ti,index-power-of-two;
222 };
223
224 dpll_abe_m2_ck: dpll_abe_m2_ck {
225 #clock-cells = <0>;
226 compatible = "ti,divider-clock";
227 clocks = <&dpll_abe_ck>;
228 ti,max-div = <31>;
229 ti,autoidle-shift = <8>;
230 reg = <0x01f0>;
231 ti,index-starts-at-one;
232 ti,invert-autoidle-bit;
233 };
234
235 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
236 #clock-cells = <0>;
237 compatible = "ti,divider-clock";
238 clocks = <&dpll_abe_x2_ck>;
239 ti,max-div = <31>;
240 ti,autoidle-shift = <8>;
241 reg = <0x01f4>;
242 ti,index-starts-at-one;
243 ti,invert-autoidle-bit;
244 };
245
246 dpll_core_byp_mux: dpll_core_byp_mux {
247 #clock-cells = <0>;
248 compatible = "ti,mux-clock";
249 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
250 ti,bit-shift = <23>;
251 reg = <0x012c>;
252 };
253
254 dpll_core_ck: dpll_core_ck {
255 #clock-cells = <0>;
256 compatible = "ti,omap4-dpll-core-clock";
257 clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
258 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
259 };
260
261 dpll_core_x2_ck: dpll_core_x2_ck {
262 #clock-cells = <0>;
263 compatible = "ti,omap4-dpll-x2-clock";
264 clocks = <&dpll_core_ck>;
265 };
266
267 dpll_core_h12x2_ck: dpll_core_h12x2_ck {
268 #clock-cells = <0>;
269 compatible = "ti,divider-clock";
270 clocks = <&dpll_core_x2_ck>;
271 ti,max-div = <63>;
272 ti,autoidle-shift = <8>;
273 reg = <0x013c>;
274 ti,index-starts-at-one;
275 ti,invert-autoidle-bit;
276 };
277
278 mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
279 #clock-cells = <0>;
280 compatible = "fixed-factor-clock";
281 clocks = <&dpll_core_h12x2_ck>;
282 clock-mult = <1>;
283 clock-div = <1>;
284 };
285
286 dpll_mpu_ck: dpll_mpu_ck {
287 #clock-cells = <0>;
288 compatible = "ti,omap5-mpu-dpll-clock";
289 clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
290 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
291 };
292
293 dpll_mpu_m2_ck: dpll_mpu_m2_ck {
294 #clock-cells = <0>;
295 compatible = "ti,divider-clock";
296 clocks = <&dpll_mpu_ck>;
297 ti,max-div = <31>;
298 ti,autoidle-shift = <8>;
299 reg = <0x0170>;
300 ti,index-starts-at-one;
301 ti,invert-autoidle-bit;
302 };
303
304 mpu_dclk_div: mpu_dclk_div {
305 #clock-cells = <0>;
306 compatible = "fixed-factor-clock";
307 clocks = <&dpll_mpu_m2_ck>;
308 clock-mult = <1>;
309 clock-div = <1>;
310 };
311
312 dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
313 #clock-cells = <0>;
314 compatible = "fixed-factor-clock";
315 clocks = <&dpll_core_h12x2_ck>;
316 clock-mult = <1>;
317 clock-div = <1>;
318 };
319
320 dpll_dsp_byp_mux: dpll_dsp_byp_mux {
321 #clock-cells = <0>;
322 compatible = "ti,mux-clock";
323 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
324 ti,bit-shift = <23>;
325 reg = <0x0240>;
326 };
327
328 dpll_dsp_ck: dpll_dsp_ck {
329 #clock-cells = <0>;
330 compatible = "ti,omap4-dpll-clock";
331 clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
332 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
333 };
334
335 dpll_dsp_m2_ck: dpll_dsp_m2_ck {
336 #clock-cells = <0>;
337 compatible = "ti,divider-clock";
338 clocks = <&dpll_dsp_ck>;
339 ti,max-div = <31>;
340 ti,autoidle-shift = <8>;
341 reg = <0x0244>;
342 ti,index-starts-at-one;
343 ti,invert-autoidle-bit;
344 };
345
346 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
347 #clock-cells = <0>;
348 compatible = "fixed-factor-clock";
349 clocks = <&dpll_core_h12x2_ck>;
350 clock-mult = <1>;
351 clock-div = <1>;
352 };
353
354 dpll_iva_byp_mux: dpll_iva_byp_mux {
355 #clock-cells = <0>;
356 compatible = "ti,mux-clock";
357 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
358 ti,bit-shift = <23>;
359 reg = <0x01ac>;
360 };
361
362 dpll_iva_ck: dpll_iva_ck {
363 #clock-cells = <0>;
364 compatible = "ti,omap4-dpll-clock";
365 clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
366 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
367 };
368
369 dpll_iva_m2_ck: dpll_iva_m2_ck {
370 #clock-cells = <0>;
371 compatible = "ti,divider-clock";
372 clocks = <&dpll_iva_ck>;
373 ti,max-div = <31>;
374 ti,autoidle-shift = <8>;
375 reg = <0x01b0>;
376 ti,index-starts-at-one;
377 ti,invert-autoidle-bit;
378 };
379
380 iva_dclk: iva_dclk {
381 #clock-cells = <0>;
382 compatible = "fixed-factor-clock";
383 clocks = <&dpll_iva_m2_ck>;
384 clock-mult = <1>;
385 clock-div = <1>;
386 };
387
388 dpll_gpu_byp_mux: dpll_gpu_byp_mux {
389 #clock-cells = <0>;
390 compatible = "ti,mux-clock";
391 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
392 ti,bit-shift = <23>;
393 reg = <0x02e4>;
394 };
395
396 dpll_gpu_ck: dpll_gpu_ck {
397 #clock-cells = <0>;
398 compatible = "ti,omap4-dpll-clock";
399 clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
400 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
401 };
402
403 dpll_gpu_m2_ck: dpll_gpu_m2_ck {
404 #clock-cells = <0>;
405 compatible = "ti,divider-clock";
406 clocks = <&dpll_gpu_ck>;
407 ti,max-div = <31>;
408 ti,autoidle-shift = <8>;
409 reg = <0x02e8>;
410 ti,index-starts-at-one;
411 ti,invert-autoidle-bit;
412 };
413
414 dpll_core_m2_ck: dpll_core_m2_ck {
415 #clock-cells = <0>;
416 compatible = "ti,divider-clock";
417 clocks = <&dpll_core_ck>;
418 ti,max-div = <31>;
419 ti,autoidle-shift = <8>;
420 reg = <0x0130>;
421 ti,index-starts-at-one;
422 ti,invert-autoidle-bit;
423 };
424
425 core_dpll_out_dclk_div: core_dpll_out_dclk_div {
426 #clock-cells = <0>;
427 compatible = "fixed-factor-clock";
428 clocks = <&dpll_core_m2_ck>;
429 clock-mult = <1>;
430 clock-div = <1>;
431 };
432
433 dpll_ddr_byp_mux: dpll_ddr_byp_mux {
434 #clock-cells = <0>;
435 compatible = "ti,mux-clock";
436 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
437 ti,bit-shift = <23>;
438 reg = <0x021c>;
439 };
440
441 dpll_ddr_ck: dpll_ddr_ck {
442 #clock-cells = <0>;
443 compatible = "ti,omap4-dpll-clock";
444 clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
445 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
446 };
447
448 dpll_ddr_m2_ck: dpll_ddr_m2_ck {
449 #clock-cells = <0>;
450 compatible = "ti,divider-clock";
451 clocks = <&dpll_ddr_ck>;
452 ti,max-div = <31>;
453 ti,autoidle-shift = <8>;
454 reg = <0x0220>;
455 ti,index-starts-at-one;
456 ti,invert-autoidle-bit;
457 };
458
459 dpll_gmac_byp_mux: dpll_gmac_byp_mux {
460 #clock-cells = <0>;
461 compatible = "ti,mux-clock";
462 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
463 ti,bit-shift = <23>;
464 reg = <0x02b4>;
465 };
466
467 dpll_gmac_ck: dpll_gmac_ck {
468 #clock-cells = <0>;
469 compatible = "ti,omap4-dpll-clock";
470 clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
471 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
472 };
473
474 dpll_gmac_m2_ck: dpll_gmac_m2_ck {
475 #clock-cells = <0>;
476 compatible = "ti,divider-clock";
477 clocks = <&dpll_gmac_ck>;
478 ti,max-div = <31>;
479 ti,autoidle-shift = <8>;
480 reg = <0x02b8>;
481 ti,index-starts-at-one;
482 ti,invert-autoidle-bit;
483 };
484
485 video2_dclk_div: video2_dclk_div {
486 #clock-cells = <0>;
487 compatible = "fixed-factor-clock";
488 clocks = <&video2_m2_clkin_ck>;
489 clock-mult = <1>;
490 clock-div = <1>;
491 };
492
493 video1_dclk_div: video1_dclk_div {
494 #clock-cells = <0>;
495 compatible = "fixed-factor-clock";
496 clocks = <&video1_m2_clkin_ck>;
497 clock-mult = <1>;
498 clock-div = <1>;
499 };
500
501 hdmi_dclk_div: hdmi_dclk_div {
502 #clock-cells = <0>;
503 compatible = "fixed-factor-clock";
504 clocks = <&hdmi_clkin_ck>;
505 clock-mult = <1>;
506 clock-div = <1>;
507 };
508
509 per_dpll_hs_clk_div: per_dpll_hs_clk_div {
510 #clock-cells = <0>;
511 compatible = "fixed-factor-clock";
512 clocks = <&dpll_abe_m3x2_ck>;
513 clock-mult = <1>;
514 clock-div = <2>;
515 };
516
517 usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
518 #clock-cells = <0>;
519 compatible = "fixed-factor-clock";
520 clocks = <&dpll_abe_m3x2_ck>;
521 clock-mult = <1>;
522 clock-div = <3>;
523 };
524
525 eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
526 #clock-cells = <0>;
527 compatible = "fixed-factor-clock";
528 clocks = <&dpll_core_h12x2_ck>;
529 clock-mult = <1>;
530 clock-div = <1>;
531 };
532
533 dpll_eve_byp_mux: dpll_eve_byp_mux {
534 #clock-cells = <0>;
535 compatible = "ti,mux-clock";
536 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
537 ti,bit-shift = <23>;
538 reg = <0x0290>;
539 };
540
541 dpll_eve_ck: dpll_eve_ck {
542 #clock-cells = <0>;
543 compatible = "ti,omap4-dpll-clock";
544 clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
545 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
546 };
547
548 dpll_eve_m2_ck: dpll_eve_m2_ck {
549 #clock-cells = <0>;
550 compatible = "ti,divider-clock";
551 clocks = <&dpll_eve_ck>;
552 ti,max-div = <31>;
553 ti,autoidle-shift = <8>;
554 reg = <0x0294>;
555 ti,index-starts-at-one;
556 ti,invert-autoidle-bit;
557 };
558
559 eve_dclk_div: eve_dclk_div {
560 #clock-cells = <0>;
561 compatible = "fixed-factor-clock";
562 clocks = <&dpll_eve_m2_ck>;
563 clock-mult = <1>;
564 clock-div = <1>;
565 };
566
567 dpll_core_h13x2_ck: dpll_core_h13x2_ck {
568 #clock-cells = <0>;
569 compatible = "ti,divider-clock";
570 clocks = <&dpll_core_x2_ck>;
571 ti,max-div = <63>;
572 ti,autoidle-shift = <8>;
573 reg = <0x0140>;
574 ti,index-starts-at-one;
575 ti,invert-autoidle-bit;
576 };
577
578 dpll_core_h14x2_ck: dpll_core_h14x2_ck {
579 #clock-cells = <0>;
580 compatible = "ti,divider-clock";
581 clocks = <&dpll_core_x2_ck>;
582 ti,max-div = <63>;
583 ti,autoidle-shift = <8>;
584 reg = <0x0144>;
585 ti,index-starts-at-one;
586 ti,invert-autoidle-bit;
587 };
588
589 dpll_core_h22x2_ck: dpll_core_h22x2_ck {
590 #clock-cells = <0>;
591 compatible = "ti,divider-clock";
592 clocks = <&dpll_core_x2_ck>;
593 ti,max-div = <63>;
594 ti,autoidle-shift = <8>;
595 reg = <0x0154>;
596 ti,index-starts-at-one;
597 ti,invert-autoidle-bit;
598 };
599
600 dpll_core_h23x2_ck: dpll_core_h23x2_ck {
601 #clock-cells = <0>;
602 compatible = "ti,divider-clock";
603 clocks = <&dpll_core_x2_ck>;
604 ti,max-div = <63>;
605 ti,autoidle-shift = <8>;
606 reg = <0x0158>;
607 ti,index-starts-at-one;
608 ti,invert-autoidle-bit;
609 };
610
611 dpll_core_h24x2_ck: dpll_core_h24x2_ck {
612 #clock-cells = <0>;
613 compatible = "ti,divider-clock";
614 clocks = <&dpll_core_x2_ck>;
615 ti,max-div = <63>;
616 ti,autoidle-shift = <8>;
617 reg = <0x015c>;
618 ti,index-starts-at-one;
619 ti,invert-autoidle-bit;
620 };
621
622 dpll_ddr_x2_ck: dpll_ddr_x2_ck {
623 #clock-cells = <0>;
624 compatible = "ti,omap4-dpll-x2-clock";
625 clocks = <&dpll_ddr_ck>;
626 };
627
628 dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck {
629 #clock-cells = <0>;
630 compatible = "ti,divider-clock";
631 clocks = <&dpll_ddr_x2_ck>;
632 ti,max-div = <63>;
633 ti,autoidle-shift = <8>;
634 reg = <0x0228>;
635 ti,index-starts-at-one;
636 ti,invert-autoidle-bit;
637 };
638
639 dpll_dsp_x2_ck: dpll_dsp_x2_ck {
640 #clock-cells = <0>;
641 compatible = "ti,omap4-dpll-x2-clock";
642 clocks = <&dpll_dsp_ck>;
643 };
644
645 dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck {
646 #clock-cells = <0>;
647 compatible = "ti,divider-clock";
648 clocks = <&dpll_dsp_x2_ck>;
649 ti,max-div = <31>;
650 ti,autoidle-shift = <8>;
651 reg = <0x0248>;
652 ti,index-starts-at-one;
653 ti,invert-autoidle-bit;
654 };
655
656 dpll_gmac_x2_ck: dpll_gmac_x2_ck {
657 #clock-cells = <0>;
658 compatible = "ti,omap4-dpll-x2-clock";
659 clocks = <&dpll_gmac_ck>;
660 };
661
662 dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
663 #clock-cells = <0>;
664 compatible = "ti,divider-clock";
665 clocks = <&dpll_gmac_x2_ck>;
666 ti,max-div = <63>;
667 ti,autoidle-shift = <8>;
668 reg = <0x02c0>;
669 ti,index-starts-at-one;
670 ti,invert-autoidle-bit;
671 };
672
673 dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
674 #clock-cells = <0>;
675 compatible = "ti,divider-clock";
676 clocks = <&dpll_gmac_x2_ck>;
677 ti,max-div = <63>;
678 ti,autoidle-shift = <8>;
679 reg = <0x02c4>;
680 ti,index-starts-at-one;
681 ti,invert-autoidle-bit;
682 };
683
684 dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
685 #clock-cells = <0>;
686 compatible = "ti,divider-clock";
687 clocks = <&dpll_gmac_x2_ck>;
688 ti,max-div = <63>;
689 ti,autoidle-shift = <8>;
690 reg = <0x02c8>;
691 ti,index-starts-at-one;
692 ti,invert-autoidle-bit;
693 };
694
695 dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
696 #clock-cells = <0>;
697 compatible = "ti,divider-clock";
698 clocks = <&dpll_gmac_x2_ck>;
699 ti,max-div = <31>;
700 ti,autoidle-shift = <8>;
701 reg = <0x02bc>;
702 ti,index-starts-at-one;
703 ti,invert-autoidle-bit;
704 };
705
706 gmii_m_clk_div: gmii_m_clk_div {
707 #clock-cells = <0>;
708 compatible = "fixed-factor-clock";
709 clocks = <&dpll_gmac_h11x2_ck>;
710 clock-mult = <1>;
711 clock-div = <2>;
712 };
713
714 hdmi_clk2_div: hdmi_clk2_div {
715 #clock-cells = <0>;
716 compatible = "fixed-factor-clock";
717 clocks = <&hdmi_clkin_ck>;
718 clock-mult = <1>;
719 clock-div = <1>;
720 };
721
722 hdmi_div_clk: hdmi_div_clk {
723 #clock-cells = <0>;
724 compatible = "fixed-factor-clock";
725 clocks = <&hdmi_clkin_ck>;
726 clock-mult = <1>;
727 clock-div = <1>;
728 };
729
730 l3_iclk_div: l3_iclk_div {
731 #clock-cells = <0>;
732 compatible = "ti,divider-clock";
733 ti,max-div = <2>;
734 ti,bit-shift = <4>;
735 reg = <0x0100>;
736 clocks = <&dpll_core_h12x2_ck>;
737 ti,index-power-of-two;
738 };
739
740 l4_root_clk_div: l4_root_clk_div {
741 #clock-cells = <0>;
742 compatible = "fixed-factor-clock";
743 clocks = <&l3_iclk_div>;
744 clock-mult = <1>;
745 clock-div = <2>;
746 };
747
748 video1_clk2_div: video1_clk2_div {
749 #clock-cells = <0>;
750 compatible = "fixed-factor-clock";
751 clocks = <&video1_clkin_ck>;
752 clock-mult = <1>;
753 clock-div = <1>;
754 };
755
756 video1_div_clk: video1_div_clk {
757 #clock-cells = <0>;
758 compatible = "fixed-factor-clock";
759 clocks = <&video1_clkin_ck>;
760 clock-mult = <1>;
761 clock-div = <1>;
762 };
763
764 video2_clk2_div: video2_clk2_div {
765 #clock-cells = <0>;
766 compatible = "fixed-factor-clock";
767 clocks = <&video2_clkin_ck>;
768 clock-mult = <1>;
769 clock-div = <1>;
770 };
771
772 video2_div_clk: video2_div_clk {
773 #clock-cells = <0>;
774 compatible = "fixed-factor-clock";
775 clocks = <&video2_clkin_ck>;
776 clock-mult = <1>;
777 clock-div = <1>;
778 };
779
780 ipu1_gfclk_mux: ipu1_gfclk_mux {
781 #clock-cells = <0>;
782 compatible = "ti,mux-clock";
783 clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
784 ti,bit-shift = <24>;
785 reg = <0x0520>;
786 };
787
788 mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
789 #clock-cells = <0>;
790 compatible = "ti,mux-clock";
791 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
792 ti,bit-shift = <28>;
793 reg = <0x0550>;
794 };
795
796 mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
797 #clock-cells = <0>;
798 compatible = "ti,mux-clock";
799 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
800 ti,bit-shift = <24>;
801 reg = <0x0550>;
802 };
803
804 mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
805 #clock-cells = <0>;
806 compatible = "ti,mux-clock";
807 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
808 ti,bit-shift = <22>;
809 reg = <0x0550>;
810 };
811
812 timer5_gfclk_mux: timer5_gfclk_mux {
813 #clock-cells = <0>;
814 compatible = "ti,mux-clock";
815 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
816 ti,bit-shift = <24>;
817 reg = <0x0558>;
818 };
819
820 timer6_gfclk_mux: timer6_gfclk_mux {
821 #clock-cells = <0>;
822 compatible = "ti,mux-clock";
823 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
824 ti,bit-shift = <24>;
825 reg = <0x0560>;
826 };
827
828 timer7_gfclk_mux: timer7_gfclk_mux {
829 #clock-cells = <0>;
830 compatible = "ti,mux-clock";
831 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
832 ti,bit-shift = <24>;
833 reg = <0x0568>;
834 };
835
836 timer8_gfclk_mux: timer8_gfclk_mux {
837 #clock-cells = <0>;
838 compatible = "ti,mux-clock";
839 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
840 ti,bit-shift = <24>;
841 reg = <0x0570>;
842 };
843
844 uart6_gfclk_mux: uart6_gfclk_mux {
845 #clock-cells = <0>;
846 compatible = "ti,mux-clock";
847 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
848 ti,bit-shift = <24>;
849 reg = <0x0580>;
850 };
851
852 dummy_ck: dummy_ck {
853 #clock-cells = <0>;
854 compatible = "fixed-clock";
855 clock-frequency = <0>;
856 };
857};
858&prm_clocks {
859 sys_clkin1: sys_clkin1 {
860 #clock-cells = <0>;
861 compatible = "ti,mux-clock";
862 clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
863 reg = <0x0110>;
864 ti,index-starts-at-one;
865 };
866
867 abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux {
868 #clock-cells = <0>;
869 compatible = "ti,mux-clock";
870 clocks = <&sys_clkin1>, <&sys_clkin2>;
871 reg = <0x0118>;
872 };
873
874 abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
875 #clock-cells = <0>;
876 compatible = "ti,mux-clock";
877 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
878 reg = <0x0114>;
879 };
880
881 abe_dpll_clk_mux: abe_dpll_clk_mux {
882 #clock-cells = <0>;
883 compatible = "ti,mux-clock";
884 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
885 reg = <0x010c>;
886 };
887
888 abe_24m_fclk: abe_24m_fclk {
889 #clock-cells = <0>;
890 compatible = "ti,divider-clock";
891 clocks = <&dpll_abe_m2x2_ck>;
892 reg = <0x011c>;
893 ti,dividers = <8>, <16>;
894 };
895
896 aess_fclk: aess_fclk {
897 #clock-cells = <0>;
898 compatible = "ti,divider-clock";
899 clocks = <&abe_clk>;
900 reg = <0x0178>;
901 ti,max-div = <2>;
902 };
903
904 abe_giclk_div: abe_giclk_div {
905 #clock-cells = <0>;
906 compatible = "ti,divider-clock";
907 clocks = <&aess_fclk>;
908 reg = <0x0174>;
909 ti,max-div = <2>;
910 };
911
912 abe_lp_clk_div: abe_lp_clk_div {
913 #clock-cells = <0>;
914 compatible = "ti,divider-clock";
915 clocks = <&dpll_abe_m2x2_ck>;
916 reg = <0x01d8>;
917 ti,dividers = <16>, <32>;
918 };
919
920 abe_sys_clk_div: abe_sys_clk_div {
921 #clock-cells = <0>;
922 compatible = "ti,divider-clock";
923 clocks = <&sys_clkin1>;
924 reg = <0x0120>;
925 ti,max-div = <2>;
926 };
927
928 adc_gfclk_mux: adc_gfclk_mux {
929 #clock-cells = <0>;
930 compatible = "ti,mux-clock";
931 clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
932 reg = <0x01dc>;
933 };
934
935 sys_clk1_dclk_div: sys_clk1_dclk_div {
936 #clock-cells = <0>;
937 compatible = "ti,divider-clock";
938 clocks = <&sys_clkin1>;
939 ti,max-div = <64>;
940 reg = <0x01c8>;
941 ti,index-power-of-two;
942 };
943
944 sys_clk2_dclk_div: sys_clk2_dclk_div {
945 #clock-cells = <0>;
946 compatible = "ti,divider-clock";
947 clocks = <&sys_clkin2>;
948 ti,max-div = <64>;
949 reg = <0x01cc>;
950 ti,index-power-of-two;
951 };
952
953 per_abe_x1_dclk_div: per_abe_x1_dclk_div {
954 #clock-cells = <0>;
955 compatible = "ti,divider-clock";
956 clocks = <&dpll_abe_m2_ck>;
957 ti,max-div = <64>;
958 reg = <0x01bc>;
959 ti,index-power-of-two;
960 };
961
962 dsp_gclk_div: dsp_gclk_div {
963 #clock-cells = <0>;
964 compatible = "ti,divider-clock";
965 clocks = <&dpll_dsp_m2_ck>;
966 ti,max-div = <64>;
967 reg = <0x018c>;
968 ti,index-power-of-two;
969 };
970
971 gpu_dclk: gpu_dclk {
972 #clock-cells = <0>;
973 compatible = "ti,divider-clock";
974 clocks = <&dpll_gpu_m2_ck>;
975 ti,max-div = <64>;
976 reg = <0x01a0>;
977 ti,index-power-of-two;
978 };
979
980 emif_phy_dclk_div: emif_phy_dclk_div {
981 #clock-cells = <0>;
982 compatible = "ti,divider-clock";
983 clocks = <&dpll_ddr_m2_ck>;
984 ti,max-div = <64>;
985 reg = <0x0190>;
986 ti,index-power-of-two;
987 };
988
989 gmac_250m_dclk_div: gmac_250m_dclk_div {
990 #clock-cells = <0>;
991 compatible = "ti,divider-clock";
992 clocks = <&dpll_gmac_m2_ck>;
993 ti,max-div = <64>;
994 reg = <0x019c>;
995 ti,index-power-of-two;
996 };
997
998 l3init_480m_dclk_div: l3init_480m_dclk_div {
999 #clock-cells = <0>;
1000 compatible = "ti,divider-clock";
1001 clocks = <&dpll_usb_m2_ck>;
1002 ti,max-div = <64>;
1003 reg = <0x01ac>;
1004 ti,index-power-of-two;
1005 };
1006
1007 usb_otg_dclk_div: usb_otg_dclk_div {
1008 #clock-cells = <0>;
1009 compatible = "ti,divider-clock";
1010 clocks = <&usb_otg_clkin_ck>;
1011 ti,max-div = <64>;
1012 reg = <0x0184>;
1013 ti,index-power-of-two;
1014 };
1015
1016 sata_dclk_div: sata_dclk_div {
1017 #clock-cells = <0>;
1018 compatible = "ti,divider-clock";
1019 clocks = <&sys_clkin1>;
1020 ti,max-div = <64>;
1021 reg = <0x01c0>;
1022 ti,index-power-of-two;
1023 };
1024
1025 pcie2_dclk_div: pcie2_dclk_div {
1026 #clock-cells = <0>;
1027 compatible = "ti,divider-clock";
1028 clocks = <&dpll_pcie_ref_m2_ck>;
1029 ti,max-div = <64>;
1030 reg = <0x01b8>;
1031 ti,index-power-of-two;
1032 };
1033
1034 pcie_dclk_div: pcie_dclk_div {
1035 #clock-cells = <0>;
1036 compatible = "ti,divider-clock";
1037 clocks = <&apll_pcie_m2_ck>;
1038 ti,max-div = <64>;
1039 reg = <0x01b4>;
1040 ti,index-power-of-two;
1041 };
1042
1043 emu_dclk_div: emu_dclk_div {
1044 #clock-cells = <0>;
1045 compatible = "ti,divider-clock";
1046 clocks = <&sys_clkin1>;
1047 ti,max-div = <64>;
1048 reg = <0x0194>;
1049 ti,index-power-of-two;
1050 };
1051
1052 secure_32k_dclk_div: secure_32k_dclk_div {
1053 #clock-cells = <0>;
1054 compatible = "ti,divider-clock";
1055 clocks = <&secure_32k_clk_src_ck>;
1056 ti,max-div = <64>;
1057 reg = <0x01c4>;
1058 ti,index-power-of-two;
1059 };
1060
1061 clkoutmux0_clk_mux: clkoutmux0_clk_mux {
1062 #clock-cells = <0>;
1063 compatible = "ti,mux-clock";
1064 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1065 reg = <0x0158>;
1066 };
1067
1068 clkoutmux1_clk_mux: clkoutmux1_clk_mux {
1069 #clock-cells = <0>;
1070 compatible = "ti,mux-clock";
1071 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1072 reg = <0x015c>;
1073 };
1074
1075 clkoutmux2_clk_mux: clkoutmux2_clk_mux {
1076 #clock-cells = <0>;
1077 compatible = "ti,mux-clock";
1078 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1079 reg = <0x0160>;
1080 };
1081
1082 custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
1083 #clock-cells = <0>;
1084 compatible = "fixed-factor-clock";
1085 clocks = <&sys_clkin1>;
1086 clock-mult = <1>;
1087 clock-div = <2>;
1088 };
1089
1090 eve_clk: eve_clk {
1091 #clock-cells = <0>;
1092 compatible = "ti,mux-clock";
1093 clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
1094 reg = <0x0180>;
1095 };
1096
1097 hdmi_dpll_clk_mux: hdmi_dpll_clk_mux {
1098 #clock-cells = <0>;
1099 compatible = "ti,mux-clock";
1100 clocks = <&sys_clkin1>, <&sys_clkin2>;
1101 reg = <0x0164>;
1102 };
1103
1104 mlb_clk: mlb_clk {
1105 #clock-cells = <0>;
1106 compatible = "ti,divider-clock";
1107 clocks = <&mlb_clkin_ck>;
1108 ti,max-div = <64>;
1109 reg = <0x0134>;
1110 ti,index-power-of-two;
1111 };
1112
1113 mlbp_clk: mlbp_clk {
1114 #clock-cells = <0>;
1115 compatible = "ti,divider-clock";
1116 clocks = <&mlbp_clkin_ck>;
1117 ti,max-div = <64>;
1118 reg = <0x0130>;
1119 ti,index-power-of-two;
1120 };
1121
1122 per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
1123 #clock-cells = <0>;
1124 compatible = "ti,divider-clock";
1125 clocks = <&dpll_abe_m2_ck>;
1126 ti,max-div = <64>;
1127 reg = <0x0138>;
1128 ti,index-power-of-two;
1129 };
1130
1131 timer_sys_clk_div: timer_sys_clk_div {
1132 #clock-cells = <0>;
1133 compatible = "ti,divider-clock";
1134 clocks = <&sys_clkin1>;
1135 reg = <0x0144>;
1136 ti,max-div = <2>;
1137 };
1138
1139 video1_dpll_clk_mux: video1_dpll_clk_mux {
1140 #clock-cells = <0>;
1141 compatible = "ti,mux-clock";
1142 clocks = <&sys_clkin1>, <&sys_clkin2>;
1143 reg = <0x0168>;
1144 };
1145
1146 video2_dpll_clk_mux: video2_dpll_clk_mux {
1147 #clock-cells = <0>;
1148 compatible = "ti,mux-clock";
1149 clocks = <&sys_clkin1>, <&sys_clkin2>;
1150 reg = <0x016c>;
1151 };
1152
1153 wkupaon_iclk_mux: wkupaon_iclk_mux {
1154 #clock-cells = <0>;
1155 compatible = "ti,mux-clock";
1156 clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
1157 reg = <0x0108>;
1158 };
1159
1160 gpio1_dbclk: gpio1_dbclk {
1161 #clock-cells = <0>;
1162 compatible = "ti,gate-clock";
1163 clocks = <&sys_32k_ck>;
1164 ti,bit-shift = <8>;
1165 reg = <0x1838>;
1166 };
1167
1168 dcan1_sys_clk_mux: dcan1_sys_clk_mux {
1169 #clock-cells = <0>;
1170 compatible = "ti,mux-clock";
1171 clocks = <&sys_clkin1>, <&sys_clkin2>;
1172 ti,bit-shift = <24>;
1173 reg = <0x1888>;
1174 };
1175
1176 timer1_gfclk_mux: timer1_gfclk_mux {
1177 #clock-cells = <0>;
1178 compatible = "ti,mux-clock";
1179 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1180 ti,bit-shift = <24>;
1181 reg = <0x1840>;
1182 };
1183
1184 uart10_gfclk_mux: uart10_gfclk_mux {
1185 #clock-cells = <0>;
1186 compatible = "ti,mux-clock";
1187 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1188 ti,bit-shift = <24>;
1189 reg = <0x1880>;
1190 };
1191};
1192&cm_core_clocks {
1193 dpll_pcie_ref_ck: dpll_pcie_ref_ck {
1194 #clock-cells = <0>;
1195 compatible = "ti,omap4-dpll-clock";
1196 clocks = <&sys_clkin1>, <&sys_clkin1>;
1197 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1198 };
1199
1200 dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
1201 #clock-cells = <0>;
1202 compatible = "ti,divider-clock";
1203 clocks = <&dpll_pcie_ref_ck>;
1204 ti,max-div = <31>;
1205 ti,autoidle-shift = <8>;
1206 reg = <0x0210>;
1207 ti,index-starts-at-one;
1208 ti,invert-autoidle-bit;
1209 };
1210
1211 apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
1212 compatible = "ti,mux-clock";
1213 clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
1214 #clock-cells = <0>;
1215 reg = <0x021c 0x4>;
1216 ti,bit-shift = <7>;
1217 };
1218
1219 apll_pcie_ck: apll_pcie_ck {
1220 #clock-cells = <0>;
1221 compatible = "ti,dra7-apll-clock";
1222 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
1223 reg = <0x021c>, <0x0220>;
1224 };
1225
1226 optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
1227 compatible = "ti,gate-clock";
1228 clocks = <&sys_32k_ck>;
1229 #clock-cells = <0>;
1230 reg = <0x13b0>;
1231 ti,bit-shift = <8>;
1232 };
1233
1234 optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
1235 compatible = "ti,gate-clock";
1236 clocks = <&sys_32k_ck>;
1237 #clock-cells = <0>;
1238 reg = <0x13b8>;
1239 ti,bit-shift = <8>;
1240 };
1241
1242 optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1243 compatible = "ti,divider-clock";
1244 clocks = <&apll_pcie_ck>;
1245 #clock-cells = <0>;
1246 reg = <0x021c>;
1247 ti,dividers = <2>, <1>;
1248 ti,bit-shift = <8>;
1249 ti,max-div = <2>;
1250 };
1251
1252 optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
1253 compatible = "ti,gate-clock";
1254 clocks = <&apll_pcie_ck>;
1255 #clock-cells = <0>;
1256 reg = <0x13b0>;
1257 ti,bit-shift = <9>;
1258 };
1259
1260 optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
1261 compatible = "ti,gate-clock";
1262 clocks = <&apll_pcie_ck>;
1263 #clock-cells = <0>;
1264 reg = <0x13b8>;
1265 ti,bit-shift = <9>;
1266 };
1267
1268 optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
1269 compatible = "ti,gate-clock";
1270 clocks = <&optfclk_pciephy_div>;
1271 #clock-cells = <0>;
1272 reg = <0x13b0>;
1273 ti,bit-shift = <10>;
1274 };
1275
1276 optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
1277 compatible = "ti,gate-clock";
1278 clocks = <&optfclk_pciephy_div>;
1279 #clock-cells = <0>;
1280 reg = <0x13b8>;
1281 ti,bit-shift = <10>;
1282 };
1283
1284 apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1285 #clock-cells = <0>;
1286 compatible = "fixed-factor-clock";
1287 clocks = <&apll_pcie_ck>;
1288 clock-mult = <1>;
1289 clock-div = <1>;
1290 };
1291
1292 apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
1293 #clock-cells = <0>;
1294 compatible = "fixed-factor-clock";
1295 clocks = <&apll_pcie_ck>;
1296 clock-mult = <1>;
1297 clock-div = <1>;
1298 };
1299
1300 apll_pcie_m2_ck: apll_pcie_m2_ck {
1301 #clock-cells = <0>;
1302 compatible = "fixed-factor-clock";
1303 clocks = <&apll_pcie_ck>;
1304 clock-mult = <1>;
1305 clock-div = <1>;
1306 };
1307
1308 dpll_per_byp_mux: dpll_per_byp_mux {
1309 #clock-cells = <0>;
1310 compatible = "ti,mux-clock";
1311 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1312 ti,bit-shift = <23>;
1313 reg = <0x014c>;
1314 };
1315
1316 dpll_per_ck: dpll_per_ck {
1317 #clock-cells = <0>;
1318 compatible = "ti,omap4-dpll-clock";
1319 clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
1320 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1321 };
1322
1323 dpll_per_m2_ck: dpll_per_m2_ck {
1324 #clock-cells = <0>;
1325 compatible = "ti,divider-clock";
1326 clocks = <&dpll_per_ck>;
1327 ti,max-div = <31>;
1328 ti,autoidle-shift = <8>;
1329 reg = <0x0150>;
1330 ti,index-starts-at-one;
1331 ti,invert-autoidle-bit;
1332 };
1333
1334 func_96m_aon_dclk_div: func_96m_aon_dclk_div {
1335 #clock-cells = <0>;
1336 compatible = "fixed-factor-clock";
1337 clocks = <&dpll_per_m2_ck>;
1338 clock-mult = <1>;
1339 clock-div = <1>;
1340 };
1341
1342 dpll_usb_byp_mux: dpll_usb_byp_mux {
1343 #clock-cells = <0>;
1344 compatible = "ti,mux-clock";
1345 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1346 ti,bit-shift = <23>;
1347 reg = <0x018c>;
1348 };
1349
1350 dpll_usb_ck: dpll_usb_ck {
1351 #clock-cells = <0>;
1352 compatible = "ti,omap4-dpll-j-type-clock";
1353 clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
1354 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1355 };
1356
1357 dpll_usb_m2_ck: dpll_usb_m2_ck {
1358 #clock-cells = <0>;
1359 compatible = "ti,divider-clock";
1360 clocks = <&dpll_usb_ck>;
1361 ti,max-div = <127>;
1362 ti,autoidle-shift = <8>;
1363 reg = <0x0190>;
1364 ti,index-starts-at-one;
1365 ti,invert-autoidle-bit;
1366 };
1367
1368 dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
1369 #clock-cells = <0>;
1370 compatible = "ti,divider-clock";
1371 clocks = <&dpll_pcie_ref_ck>;
1372 ti,max-div = <127>;
1373 ti,autoidle-shift = <8>;
1374 reg = <0x0210>;
1375 ti,index-starts-at-one;
1376 ti,invert-autoidle-bit;
1377 };
1378
1379 dpll_per_x2_ck: dpll_per_x2_ck {
1380 #clock-cells = <0>;
1381 compatible = "ti,omap4-dpll-x2-clock";
1382 clocks = <&dpll_per_ck>;
1383 };
1384
1385 dpll_per_h11x2_ck: dpll_per_h11x2_ck {
1386 #clock-cells = <0>;
1387 compatible = "ti,divider-clock";
1388 clocks = <&dpll_per_x2_ck>;
1389 ti,max-div = <63>;
1390 ti,autoidle-shift = <8>;
1391 reg = <0x0158>;
1392 ti,index-starts-at-one;
1393 ti,invert-autoidle-bit;
1394 };
1395
1396 dpll_per_h12x2_ck: dpll_per_h12x2_ck {
1397 #clock-cells = <0>;
1398 compatible = "ti,divider-clock";
1399 clocks = <&dpll_per_x2_ck>;
1400 ti,max-div = <63>;
1401 ti,autoidle-shift = <8>;
1402 reg = <0x015c>;
1403 ti,index-starts-at-one;
1404 ti,invert-autoidle-bit;
1405 };
1406
1407 dpll_per_h13x2_ck: dpll_per_h13x2_ck {
1408 #clock-cells = <0>;
1409 compatible = "ti,divider-clock";
1410 clocks = <&dpll_per_x2_ck>;
1411 ti,max-div = <63>;
1412 ti,autoidle-shift = <8>;
1413 reg = <0x0160>;
1414 ti,index-starts-at-one;
1415 ti,invert-autoidle-bit;
1416 };
1417
1418 dpll_per_h14x2_ck: dpll_per_h14x2_ck {
1419 #clock-cells = <0>;
1420 compatible = "ti,divider-clock";
1421 clocks = <&dpll_per_x2_ck>;
1422 ti,max-div = <63>;
1423 ti,autoidle-shift = <8>;
1424 reg = <0x0164>;
1425 ti,index-starts-at-one;
1426 ti,invert-autoidle-bit;
1427 };
1428
1429 dpll_per_m2x2_ck: dpll_per_m2x2_ck {
1430 #clock-cells = <0>;
1431 compatible = "ti,divider-clock";
1432 clocks = <&dpll_per_x2_ck>;
1433 ti,max-div = <31>;
1434 ti,autoidle-shift = <8>;
1435 reg = <0x0150>;
1436 ti,index-starts-at-one;
1437 ti,invert-autoidle-bit;
1438 };
1439
1440 dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
1441 #clock-cells = <0>;
1442 compatible = "fixed-factor-clock";
1443 clocks = <&dpll_usb_ck>;
1444 clock-mult = <1>;
1445 clock-div = <1>;
1446 };
1447
1448 func_128m_clk: func_128m_clk {
1449 #clock-cells = <0>;
1450 compatible = "fixed-factor-clock";
1451 clocks = <&dpll_per_h11x2_ck>;
1452 clock-mult = <1>;
1453 clock-div = <2>;
1454 };
1455
1456 func_12m_fclk: func_12m_fclk {
1457 #clock-cells = <0>;
1458 compatible = "fixed-factor-clock";
1459 clocks = <&dpll_per_m2x2_ck>;
1460 clock-mult = <1>;
1461 clock-div = <16>;
1462 };
1463
1464 func_24m_clk: func_24m_clk {
1465 #clock-cells = <0>;
1466 compatible = "fixed-factor-clock";
1467 clocks = <&dpll_per_m2_ck>;
1468 clock-mult = <1>;
1469 clock-div = <4>;
1470 };
1471
1472 func_48m_fclk: func_48m_fclk {
1473 #clock-cells = <0>;
1474 compatible = "fixed-factor-clock";
1475 clocks = <&dpll_per_m2x2_ck>;
1476 clock-mult = <1>;
1477 clock-div = <4>;
1478 };
1479
1480 func_96m_fclk: func_96m_fclk {
1481 #clock-cells = <0>;
1482 compatible = "fixed-factor-clock";
1483 clocks = <&dpll_per_m2x2_ck>;
1484 clock-mult = <1>;
1485 clock-div = <2>;
1486 };
1487
1488 l3init_60m_fclk: l3init_60m_fclk {
1489 #clock-cells = <0>;
1490 compatible = "ti,divider-clock";
1491 clocks = <&dpll_usb_m2_ck>;
1492 reg = <0x0104>;
1493 ti,dividers = <1>, <8>;
1494 };
1495
1496 clkout2_clk: clkout2_clk {
1497 #clock-cells = <0>;
1498 compatible = "ti,gate-clock";
1499 clocks = <&clkoutmux2_clk_mux>;
1500 ti,bit-shift = <8>;
1501 reg = <0x06b0>;
1502 };
1503
1504 l3init_960m_gfclk: l3init_960m_gfclk {
1505 #clock-cells = <0>;
1506 compatible = "ti,gate-clock";
1507 clocks = <&dpll_usb_clkdcoldo>;
1508 ti,bit-shift = <8>;
1509 reg = <0x06c0>;
1510 };
1511
1512 dss_32khz_clk: dss_32khz_clk {
1513 #clock-cells = <0>;
1514 compatible = "ti,gate-clock";
1515 clocks = <&sys_32k_ck>;
1516 ti,bit-shift = <11>;
1517 reg = <0x1120>;
1518 };
1519
1520 dss_48mhz_clk: dss_48mhz_clk {
1521 #clock-cells = <0>;
1522 compatible = "ti,gate-clock";
1523 clocks = <&func_48m_fclk>;
1524 ti,bit-shift = <9>;
1525 reg = <0x1120>;
1526 };
1527
1528 dss_dss_clk: dss_dss_clk {
1529 #clock-cells = <0>;
1530 compatible = "ti,gate-clock";
1531 clocks = <&dpll_per_h12x2_ck>;
1532 ti,bit-shift = <8>;
1533 reg = <0x1120>;
1534 ti,set-rate-parent;
1535 };
1536
1537 dss_hdmi_clk: dss_hdmi_clk {
1538 #clock-cells = <0>;
1539 compatible = "ti,gate-clock";
1540 clocks = <&hdmi_dpll_clk_mux>;
1541 ti,bit-shift = <10>;
1542 reg = <0x1120>;
1543 };
1544
1545 dss_video1_clk: dss_video1_clk {
1546 #clock-cells = <0>;
1547 compatible = "ti,gate-clock";
1548 clocks = <&video1_dpll_clk_mux>;
1549 ti,bit-shift = <12>;
1550 reg = <0x1120>;
1551 };
1552
1553 dss_video2_clk: dss_video2_clk {
1554 #clock-cells = <0>;
1555 compatible = "ti,gate-clock";
1556 clocks = <&video2_dpll_clk_mux>;
1557 ti,bit-shift = <13>;
1558 reg = <0x1120>;
1559 };
1560
1561 gpio2_dbclk: gpio2_dbclk {
1562 #clock-cells = <0>;
1563 compatible = "ti,gate-clock";
1564 clocks = <&sys_32k_ck>;
1565 ti,bit-shift = <8>;
1566 reg = <0x1760>;
1567 };
1568
1569 gpio3_dbclk: gpio3_dbclk {
1570 #clock-cells = <0>;
1571 compatible = "ti,gate-clock";
1572 clocks = <&sys_32k_ck>;
1573 ti,bit-shift = <8>;
1574 reg = <0x1768>;
1575 };
1576
1577 gpio4_dbclk: gpio4_dbclk {
1578 #clock-cells = <0>;
1579 compatible = "ti,gate-clock";
1580 clocks = <&sys_32k_ck>;
1581 ti,bit-shift = <8>;
1582 reg = <0x1770>;
1583 };
1584
1585 gpio5_dbclk: gpio5_dbclk {
1586 #clock-cells = <0>;
1587 compatible = "ti,gate-clock";
1588 clocks = <&sys_32k_ck>;
1589 ti,bit-shift = <8>;
1590 reg = <0x1778>;
1591 };
1592
1593 gpio6_dbclk: gpio6_dbclk {
1594 #clock-cells = <0>;
1595 compatible = "ti,gate-clock";
1596 clocks = <&sys_32k_ck>;
1597 ti,bit-shift = <8>;
1598 reg = <0x1780>;
1599 };
1600
1601 gpio7_dbclk: gpio7_dbclk {
1602 #clock-cells = <0>;
1603 compatible = "ti,gate-clock";
1604 clocks = <&sys_32k_ck>;
1605 ti,bit-shift = <8>;
1606 reg = <0x1810>;
1607 };
1608
1609 gpio8_dbclk: gpio8_dbclk {
1610 #clock-cells = <0>;
1611 compatible = "ti,gate-clock";
1612 clocks = <&sys_32k_ck>;
1613 ti,bit-shift = <8>;
1614 reg = <0x1818>;
1615 };
1616
1617 mmc1_clk32k: mmc1_clk32k {
1618 #clock-cells = <0>;
1619 compatible = "ti,gate-clock";
1620 clocks = <&sys_32k_ck>;
1621 ti,bit-shift = <8>;
1622 reg = <0x1328>;
1623 };
1624
1625 mmc2_clk32k: mmc2_clk32k {
1626 #clock-cells = <0>;
1627 compatible = "ti,gate-clock";
1628 clocks = <&sys_32k_ck>;
1629 ti,bit-shift = <8>;
1630 reg = <0x1330>;
1631 };
1632
1633 mmc3_clk32k: mmc3_clk32k {
1634 #clock-cells = <0>;
1635 compatible = "ti,gate-clock";
1636 clocks = <&sys_32k_ck>;
1637 ti,bit-shift = <8>;
1638 reg = <0x1820>;
1639 };
1640
1641 mmc4_clk32k: mmc4_clk32k {
1642 #clock-cells = <0>;
1643 compatible = "ti,gate-clock";
1644 clocks = <&sys_32k_ck>;
1645 ti,bit-shift = <8>;
1646 reg = <0x1828>;
1647 };
1648
1649 sata_ref_clk: sata_ref_clk {
1650 #clock-cells = <0>;
1651 compatible = "ti,gate-clock";
1652 clocks = <&sys_clkin1>;
1653 ti,bit-shift = <8>;
1654 reg = <0x1388>;
1655 };
1656
1657 usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
1658 #clock-cells = <0>;
1659 compatible = "ti,gate-clock";
1660 clocks = <&l3init_960m_gfclk>;
1661 ti,bit-shift = <8>;
1662 reg = <0x13f0>;
1663 };
1664
1665 usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
1666 #clock-cells = <0>;
1667 compatible = "ti,gate-clock";
1668 clocks = <&l3init_960m_gfclk>;
1669 ti,bit-shift = <8>;
1670 reg = <0x1340>;
1671 };
1672
1673 usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
1674 #clock-cells = <0>;
1675 compatible = "ti,gate-clock";
1676 clocks = <&sys_32k_ck>;
1677 ti,bit-shift = <8>;
1678 reg = <0x0640>;
1679 };
1680
1681 usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
1682 #clock-cells = <0>;
1683 compatible = "ti,gate-clock";
1684 clocks = <&sys_32k_ck>;
1685 ti,bit-shift = <8>;
1686 reg = <0x0688>;
1687 };
1688
1689 usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
1690 #clock-cells = <0>;
1691 compatible = "ti,gate-clock";
1692 clocks = <&sys_32k_ck>;
1693 ti,bit-shift = <8>;
1694 reg = <0x0698>;
1695 };
1696
1697 atl_dpll_clk_mux: atl_dpll_clk_mux {
1698 #clock-cells = <0>;
1699 compatible = "ti,mux-clock";
1700 clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
1701 ti,bit-shift = <24>;
1702 reg = <0x0c00>;
1703 };
1704
1705 atl_gfclk_mux: atl_gfclk_mux {
1706 #clock-cells = <0>;
1707 compatible = "ti,mux-clock";
1708 clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
1709 ti,bit-shift = <26>;
1710 reg = <0x0c00>;
1711 };
1712
1713 gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
1714 #clock-cells = <0>;
1715 compatible = "ti,divider-clock";
1716 clocks = <&dpll_gmac_m2_ck>;
1717 ti,bit-shift = <24>;
1718 reg = <0x13d0>;
1719 ti,dividers = <2>;
1720 };
1721
1722 gmac_rft_clk_mux: gmac_rft_clk_mux {
1723 #clock-cells = <0>;
1724 compatible = "ti,mux-clock";
1725 clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
1726 ti,bit-shift = <25>;
1727 reg = <0x13d0>;
1728 };
1729
1730 gpu_core_gclk_mux: gpu_core_gclk_mux {
1731 #clock-cells = <0>;
1732 compatible = "ti,mux-clock";
1733 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1734 ti,bit-shift = <24>;
1735 reg = <0x1220>;
1736 };
1737
1738 gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
1739 #clock-cells = <0>;
1740 compatible = "ti,mux-clock";
1741 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1742 ti,bit-shift = <26>;
1743 reg = <0x1220>;
1744 };
1745
1746 l3instr_ts_gclk_div: l3instr_ts_gclk_div {
1747 #clock-cells = <0>;
1748 compatible = "ti,divider-clock";
1749 clocks = <&wkupaon_iclk_mux>;
1750 ti,bit-shift = <24>;
1751 reg = <0x0e50>;
1752 ti,dividers = <8>, <16>, <32>;
1753 };
1754
1755 mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
1756 #clock-cells = <0>;
1757 compatible = "ti,mux-clock";
1758 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1759 ti,bit-shift = <28>;
1760 reg = <0x1860>;
1761 };
1762
1763 mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
1764 #clock-cells = <0>;
1765 compatible = "ti,mux-clock";
1766 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1767 ti,bit-shift = <24>;
1768 reg = <0x1860>;
1769 };
1770
1771 mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
1772 #clock-cells = <0>;
1773 compatible = "ti,mux-clock";
1774 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1775 ti,bit-shift = <22>;
1776 reg = <0x1860>;
1777 };
1778
1779 mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
1780 #clock-cells = <0>;
1781 compatible = "ti,mux-clock";
1782 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1783 ti,bit-shift = <24>;
1784 reg = <0x1868>;
1785 };
1786
1787 mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
1788 #clock-cells = <0>;
1789 compatible = "ti,mux-clock";
1790 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1791 ti,bit-shift = <22>;
1792 reg = <0x1868>;
1793 };
1794
1795 mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
1796 #clock-cells = <0>;
1797 compatible = "ti,mux-clock";
1798 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1799 ti,bit-shift = <24>;
1800 reg = <0x1898>;
1801 };
1802
1803 mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
1804 #clock-cells = <0>;
1805 compatible = "ti,mux-clock";
1806 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1807 ti,bit-shift = <22>;
1808 reg = <0x1898>;
1809 };
1810
1811 mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
1812 #clock-cells = <0>;
1813 compatible = "ti,mux-clock";
1814 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1815 ti,bit-shift = <24>;
1816 reg = <0x1878>;
1817 };
1818
1819 mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
1820 #clock-cells = <0>;
1821 compatible = "ti,mux-clock";
1822 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1823 ti,bit-shift = <22>;
1824 reg = <0x1878>;
1825 };
1826
1827 mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
1828 #clock-cells = <0>;
1829 compatible = "ti,mux-clock";
1830 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1831 ti,bit-shift = <24>;
1832 reg = <0x1904>;
1833 };
1834
1835 mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
1836 #clock-cells = <0>;
1837 compatible = "ti,mux-clock";
1838 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1839 ti,bit-shift = <22>;
1840 reg = <0x1904>;
1841 };
1842
1843 mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
1844 #clock-cells = <0>;
1845 compatible = "ti,mux-clock";
1846 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1847 ti,bit-shift = <24>;
1848 reg = <0x1908>;
1849 };
1850
1851 mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
1852 #clock-cells = <0>;
1853 compatible = "ti,mux-clock";
1854 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1855 ti,bit-shift = <22>;
1856 reg = <0x1908>;
1857 };
1858
1859 mcasp8_ahclk_mux: mcasp8_ahclk_mux {
1860 #clock-cells = <0>;
1861 compatible = "ti,mux-clock";
1862 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1863 ti,bit-shift = <22>;
1864 reg = <0x1890>;
1865 };
1866
1867 mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
1868 #clock-cells = <0>;
1869 compatible = "ti,mux-clock";
1870 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1871 ti,bit-shift = <24>;
1872 reg = <0x1890>;
1873 };
1874
1875 mmc1_fclk_mux: mmc1_fclk_mux {
1876 #clock-cells = <0>;
1877 compatible = "ti,mux-clock";
1878 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1879 ti,bit-shift = <24>;
1880 reg = <0x1328>;
1881 };
1882
1883 mmc1_fclk_div: mmc1_fclk_div {
1884 #clock-cells = <0>;
1885 compatible = "ti,divider-clock";
1886 clocks = <&mmc1_fclk_mux>;
1887 ti,bit-shift = <25>;
1888 ti,max-div = <4>;
1889 reg = <0x1328>;
1890 ti,index-power-of-two;
1891 };
1892
1893 mmc2_fclk_mux: mmc2_fclk_mux {
1894 #clock-cells = <0>;
1895 compatible = "ti,mux-clock";
1896 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1897 ti,bit-shift = <24>;
1898 reg = <0x1330>;
1899 };
1900
1901 mmc2_fclk_div: mmc2_fclk_div {
1902 #clock-cells = <0>;
1903 compatible = "ti,divider-clock";
1904 clocks = <&mmc2_fclk_mux>;
1905 ti,bit-shift = <25>;
1906 ti,max-div = <4>;
1907 reg = <0x1330>;
1908 ti,index-power-of-two;
1909 };
1910
1911 mmc3_gfclk_mux: mmc3_gfclk_mux {
1912 #clock-cells = <0>;
1913 compatible = "ti,mux-clock";
1914 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1915 ti,bit-shift = <24>;
1916 reg = <0x1820>;
1917 };
1918
1919 mmc3_gfclk_div: mmc3_gfclk_div {
1920 #clock-cells = <0>;
1921 compatible = "ti,divider-clock";
1922 clocks = <&mmc3_gfclk_mux>;
1923 ti,bit-shift = <25>;
1924 ti,max-div = <4>;
1925 reg = <0x1820>;
1926 ti,index-power-of-two;
1927 };
1928
1929 mmc4_gfclk_mux: mmc4_gfclk_mux {
1930 #clock-cells = <0>;
1931 compatible = "ti,mux-clock";
1932 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1933 ti,bit-shift = <24>;
1934 reg = <0x1828>;
1935 };
1936
1937 mmc4_gfclk_div: mmc4_gfclk_div {
1938 #clock-cells = <0>;
1939 compatible = "ti,divider-clock";
1940 clocks = <&mmc4_gfclk_mux>;
1941 ti,bit-shift = <25>;
1942 ti,max-div = <4>;
1943 reg = <0x1828>;
1944 ti,index-power-of-two;
1945 };
1946
1947 qspi_gfclk_mux: qspi_gfclk_mux {
1948 #clock-cells = <0>;
1949 compatible = "ti,mux-clock";
1950 clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
1951 ti,bit-shift = <24>;
1952 reg = <0x1838>;
1953 };
1954
1955 qspi_gfclk_div: qspi_gfclk_div {
1956 #clock-cells = <0>;
1957 compatible = "ti,divider-clock";
1958 clocks = <&qspi_gfclk_mux>;
1959 ti,bit-shift = <25>;
1960 ti,max-div = <4>;
1961 reg = <0x1838>;
1962 ti,index-power-of-two;
1963 };
1964
1965 timer10_gfclk_mux: timer10_gfclk_mux {
1966 #clock-cells = <0>;
1967 compatible = "ti,mux-clock";
1968 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1969 ti,bit-shift = <24>;
1970 reg = <0x1728>;
1971 };
1972
1973 timer11_gfclk_mux: timer11_gfclk_mux {
1974 #clock-cells = <0>;
1975 compatible = "ti,mux-clock";
1976 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1977 ti,bit-shift = <24>;
1978 reg = <0x1730>;
1979 };
1980
1981 timer13_gfclk_mux: timer13_gfclk_mux {
1982 #clock-cells = <0>;
1983 compatible = "ti,mux-clock";
1984 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1985 ti,bit-shift = <24>;
1986 reg = <0x17c8>;
1987 };
1988
1989 timer14_gfclk_mux: timer14_gfclk_mux {
1990 #clock-cells = <0>;
1991 compatible = "ti,mux-clock";
1992 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1993 ti,bit-shift = <24>;
1994 reg = <0x17d0>;
1995 };
1996
1997 timer15_gfclk_mux: timer15_gfclk_mux {
1998 #clock-cells = <0>;
1999 compatible = "ti,mux-clock";
2000 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2001 ti,bit-shift = <24>;
2002 reg = <0x17d8>;
2003 };
2004
2005 timer16_gfclk_mux: timer16_gfclk_mux {
2006 #clock-cells = <0>;
2007 compatible = "ti,mux-clock";
2008 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2009 ti,bit-shift = <24>;
2010 reg = <0x1830>;
2011 };
2012
2013 timer2_gfclk_mux: timer2_gfclk_mux {
2014 #clock-cells = <0>;
2015 compatible = "ti,mux-clock";
2016 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2017 ti,bit-shift = <24>;
2018 reg = <0x1738>;
2019 };
2020
2021 timer3_gfclk_mux: timer3_gfclk_mux {
2022 #clock-cells = <0>;
2023 compatible = "ti,mux-clock";
2024 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2025 ti,bit-shift = <24>;
2026 reg = <0x1740>;
2027 };
2028
2029 timer4_gfclk_mux: timer4_gfclk_mux {
2030 #clock-cells = <0>;
2031 compatible = "ti,mux-clock";
2032 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2033 ti,bit-shift = <24>;
2034 reg = <0x1748>;
2035 };
2036
2037 timer9_gfclk_mux: timer9_gfclk_mux {
2038 #clock-cells = <0>;
2039 compatible = "ti,mux-clock";
2040 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2041 ti,bit-shift = <24>;
2042 reg = <0x1750>;
2043 };
2044
2045 uart1_gfclk_mux: uart1_gfclk_mux {
2046 #clock-cells = <0>;
2047 compatible = "ti,mux-clock";
2048 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2049 ti,bit-shift = <24>;
2050 reg = <0x1840>;
2051 };
2052
2053 uart2_gfclk_mux: uart2_gfclk_mux {
2054 #clock-cells = <0>;
2055 compatible = "ti,mux-clock";
2056 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2057 ti,bit-shift = <24>;
2058 reg = <0x1848>;
2059 };
2060
2061 uart3_gfclk_mux: uart3_gfclk_mux {
2062 #clock-cells = <0>;
2063 compatible = "ti,mux-clock";
2064 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2065 ti,bit-shift = <24>;
2066 reg = <0x1850>;
2067 };
2068
2069 uart4_gfclk_mux: uart4_gfclk_mux {
2070 #clock-cells = <0>;
2071 compatible = "ti,mux-clock";
2072 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2073 ti,bit-shift = <24>;
2074 reg = <0x1858>;
2075 };
2076
2077 uart5_gfclk_mux: uart5_gfclk_mux {
2078 #clock-cells = <0>;
2079 compatible = "ti,mux-clock";
2080 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2081 ti,bit-shift = <24>;
2082 reg = <0x1870>;
2083 };
2084
2085 uart7_gfclk_mux: uart7_gfclk_mux {
2086 #clock-cells = <0>;
2087 compatible = "ti,mux-clock";
2088 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2089 ti,bit-shift = <24>;
2090 reg = <0x18d0>;
2091 };
2092
2093 uart8_gfclk_mux: uart8_gfclk_mux {
2094 #clock-cells = <0>;
2095 compatible = "ti,mux-clock";
2096 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2097 ti,bit-shift = <24>;
2098 reg = <0x18e0>;
2099 };
2100
2101 uart9_gfclk_mux: uart9_gfclk_mux {
2102 #clock-cells = <0>;
2103 compatible = "ti,mux-clock";
2104 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2105 ti,bit-shift = <24>;
2106 reg = <0x18e8>;
2107 };
2108
2109 vip1_gclk_mux: vip1_gclk_mux {
2110 #clock-cells = <0>;
2111 compatible = "ti,mux-clock";
2112 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2113 ti,bit-shift = <24>;
2114 reg = <0x1020>;
2115 };
2116
2117 vip2_gclk_mux: vip2_gclk_mux {
2118 #clock-cells = <0>;
2119 compatible = "ti,mux-clock";
2120 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2121 ti,bit-shift = <24>;
2122 reg = <0x1028>;
2123 };
2124
2125 vip3_gclk_mux: vip3_gclk_mux {
2126 #clock-cells = <0>;
2127 compatible = "ti,mux-clock";
2128 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2129 ti,bit-shift = <24>;
2130 reg = <0x1030>;
2131 };
2132};
2133
2134&cm_core_clockdomains {
2135 coreaon_clkdm: coreaon_clkdm {
2136 compatible = "ti,clockdomain";
2137 clocks = <&dpll_usb_ck>;
2138 };
2139};
2140
2141&scm_conf_clocks {
2142 dss_deshdcp_clk: dss_deshdcp_clk {
2143 #clock-cells = <0>;
2144 compatible = "ti,gate-clock";
2145 clocks = <&l3_iclk_div>;
2146 ti,bit-shift = <0>;
2147 reg = <0x558>;
2148 };
2149};