| Dave Gerlach | 58211db | 2021-04-23 11:27:44 -0500 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Device Tree Source for AM642 SoC Family |
| 4 | * |
| 5 | * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ |
| 6 | */ |
| 7 | |
| 8 | #include <dt-bindings/gpio/gpio.h> |
| 9 | #include <dt-bindings/interrupt-controller/irq.h> |
| 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 11 | #include <dt-bindings/pinctrl/k3.h> |
| 12 | #include <dt-bindings/soc/ti,sci_pm_domain.h> |
| 13 | |
| 14 | / { |
| 15 | model = "Texas Instruments K3 AM642 SoC"; |
| 16 | compatible = "ti,am642"; |
| 17 | interrupt-parent = <&gic500>; |
| 18 | #address-cells = <2>; |
| 19 | #size-cells = <2>; |
| 20 | |
| 21 | aliases { |
| 22 | serial0 = &mcu_uart0; |
| 23 | serial1 = &mcu_uart1; |
| 24 | serial2 = &main_uart0; |
| 25 | serial3 = &main_uart1; |
| 26 | serial4 = &main_uart2; |
| 27 | serial5 = &main_uart3; |
| 28 | serial6 = &main_uart4; |
| 29 | serial7 = &main_uart5; |
| 30 | serial8 = &main_uart6; |
| 31 | }; |
| 32 | |
| 33 | chosen { }; |
| 34 | |
| 35 | firmware { |
| 36 | optee { |
| 37 | compatible = "linaro,optee-tz"; |
| 38 | method = "smc"; |
| 39 | }; |
| 40 | |
| 41 | psci: psci { |
| 42 | compatible = "arm,psci-1.0"; |
| 43 | method = "smc"; |
| 44 | }; |
| 45 | }; |
| 46 | |
| 47 | a53_timer0: timer-cl0-cpu0 { |
| 48 | compatible = "arm,armv8-timer"; |
| 49 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ |
| 50 | <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ |
| 51 | <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ |
| 52 | <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ |
| 53 | }; |
| 54 | |
| 55 | pmu: pmu { |
| 56 | compatible = "arm,cortex-a53-pmu"; |
| 57 | interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| 58 | }; |
| 59 | |
| 60 | cbass_main: bus@f4000 { |
| 61 | compatible = "simple-bus"; |
| 62 | #address-cells = <2>; |
| 63 | #size-cells = <2>; |
| 64 | ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */ |
| 65 | <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ |
| 66 | <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ |
| 67 | <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ |
| 68 | <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ |
| 69 | <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */ |
| 70 | <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */ |
| 71 | <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ |
| 72 | <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */ |
| 73 | <0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */ |
| 74 | <0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */ |
| 75 | <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */ |
| 76 | <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */ |
| 77 | <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */ |
| 78 | <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */ |
| 79 | <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ |
| 80 | <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */ |
| 81 | <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */ |
| 82 | <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ |
| 83 | <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */ |
| 84 | <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */ |
| 85 | <0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */ |
| 86 | <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */ |
| 87 | <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ |
| 88 | |
| 89 | /* MCU Domain Range */ |
| 90 | <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; |
| 91 | |
| 92 | cbass_mcu: bus@4000000 { |
| 93 | compatible = "simple-bus"; |
| 94 | #address-cells = <2>; |
| 95 | #size-cells = <2>; |
| 96 | ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ |
| 97 | }; |
| 98 | }; |
| 99 | }; |
| 100 | |
| 101 | /* Now include the peripherals for each bus segments */ |
| 102 | #include "k3-am64-main.dtsi" |
| 103 | #include "k3-am64-mcu.dtsi" |