blob: ac580a0da746c35e37a901755e1bf99332cc700e [file] [log] [blame]
Dave Liu7737d5c2006-11-03 12:11:15 -06001/*
Kumar Gala2b21ec92011-01-19 03:36:40 -06002 * Copyright (C) 2005,2010-2011 Freescale Semiconductor, Inc.
Dave Liu7737d5c2006-11-03 12:11:15 -06003 *
4 * Author: Shlomi Gridish
5 *
6 * Description: UCC GETH Driver -- PHY handling
Wolfgang Denkdd520bf2006-11-30 18:02:20 +01007 * Driver for UEC on QE
8 * Based on 8260_io/fcc_enet.c
Dave Liu7737d5c2006-11-03 12:11:15 -06009 *
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010010 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
Dave Liu7737d5c2006-11-03 12:11:15 -060012 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#include "common.h"
18#include "net.h"
19#include "malloc.h"
20#include "asm/errno.h"
21#include "asm/immap_qe.h"
22#include "asm/io.h"
23#include "qe.h"
24#include "uccf.h"
25#include "uec.h"
26#include "uec_phy.h"
27#include "miiphy.h"
Andy Fleming865ff852011-04-13 00:37:12 -050028#include <phy.h>
Dave Liu7737d5c2006-11-03 12:11:15 -060029
Dave Liu7737d5c2006-11-03 12:11:15 -060030#define ugphy_printk(format, arg...) \
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010031 printf(format "\n", ## arg)
Dave Liu7737d5c2006-11-03 12:11:15 -060032
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010033#define ugphy_dbg(format, arg...) \
34 ugphy_printk(format , ## arg)
35#define ugphy_err(format, arg...) \
36 ugphy_printk(format , ## arg)
37#define ugphy_info(format, arg...) \
38 ugphy_printk(format , ## arg)
39#define ugphy_warn(format, arg...) \
40 ugphy_printk(format , ## arg)
Dave Liu7737d5c2006-11-03 12:11:15 -060041
42#ifdef UEC_VERBOSE_DEBUG
43#define ugphy_vdbg ugphy_dbg
44#else
45#define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
46#endif /* UEC_VERBOSE_DEBUG */
47
Richard Retanubunedf3fe72008-10-23 09:08:18 -040048/*--------------------------------------------------------------------+
49 * Fixed PHY (PHY-less) support for Ethernet Ports.
50 *
Stefan Roesea47a12b2010-04-15 16:07:28 +020051 * Copied from arch/powerpc/cpu/ppc4xx/4xx_enet.c
Richard Retanubunedf3fe72008-10-23 09:08:18 -040052 *--------------------------------------------------------------------*/
53
54/*
Richard Retanubun1443cd72009-07-01 14:04:05 -040055 * Some boards do not have a PHY for each ethernet port. These ports are known
56 * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate
57 * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
58 * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned
59 * and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network
60 * speed and duplex should be for the port.
Richard Retanubunedf3fe72008-10-23 09:08:18 -040061 *
Richard Retanubun1443cd72009-07-01 14:04:05 -040062 * Example board header configuration file:
Richard Retanubunedf3fe72008-10-23 09:08:18 -040063 * #define CONFIG_FIXED_PHY 0xFFFFFFFF
Richard Retanubun1443cd72009-07-01 14:04:05 -040064 * #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address)
Richard Retanubunedf3fe72008-10-23 09:08:18 -040065 *
Richard Retanubun1443cd72009-07-01 14:04:05 -040066 * #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
67 * #define CONFIG_SYS_UEC2_PHY_ADDR 0x02
68 * #define CONFIG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
69 * #define CONFIG_SYS_UEC4_PHY_ADDR 0x04
Richard Retanubunedf3fe72008-10-23 09:08:18 -040070 *
Richard Retanubun1443cd72009-07-01 14:04:05 -040071 * #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \
72 * {name, speed, duplex},
Richard Retanubunedf3fe72008-10-23 09:08:18 -040073 *
74 * #define CONFIG_SYS_FIXED_PHY_PORTS \
Kim Phillips78b7a8e2010-07-26 18:34:57 -050075 * CONFIG_SYS_FIXED_PHY_PORT("UEC0",SPEED_100,DUPLEX_FULL) \
76 * CONFIG_SYS_FIXED_PHY_PORT("UEC2",SPEED_100,DUPLEX_HALF)
Richard Retanubunedf3fe72008-10-23 09:08:18 -040077 */
78
79#ifndef CONFIG_FIXED_PHY
80#define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
81#endif
82
83#ifndef CONFIG_SYS_FIXED_PHY_PORTS
84#define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
85#endif
86
87struct fixed_phy_port {
Mike Frysingerf6add132011-11-10 14:11:04 +000088 char name[16]; /* ethernet port name */
Richard Retanubunedf3fe72008-10-23 09:08:18 -040089 unsigned int speed; /* specified speed 10,100 or 1000 */
90 unsigned int duplex; /* specified duplex FULL or HALF */
91};
92
93static const struct fixed_phy_port fixed_phy_port[] = {
94 CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
95};
96
Richard Retanubun23c34af2009-06-17 16:00:41 -040097/*--------------------------------------------------------------------+
98 * BitBang MII support for ethernet ports
99 *
100 * Based from MPC8560ADS implementation
101 *--------------------------------------------------------------------*/
102/*
103 * Example board header file to define bitbang ethernet ports:
104 *
105 * #define CONFIG_SYS_BITBANG_PHY_PORT(name) name,
Kim Phillips78b7a8e2010-07-26 18:34:57 -0500106 * #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("UEC0")
Richard Retanubun23c34af2009-06-17 16:00:41 -0400107*/
108#ifndef CONFIG_SYS_BITBANG_PHY_PORTS
109#define CONFIG_SYS_BITBANG_PHY_PORTS /* default is an empty array */
110#endif
111
112#if defined(CONFIG_BITBANGMII)
113static const char *bitbang_phy_port[] = {
114 CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */
115};
116#endif /* CONFIG_BITBANGMII */
117
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100118static void config_genmii_advert (struct uec_mii_info *mii_info);
119static void genmii_setup_forced (struct uec_mii_info *mii_info);
120static void genmii_restart_aneg (struct uec_mii_info *mii_info);
121static int gbit_config_aneg (struct uec_mii_info *mii_info);
122static int genmii_config_aneg (struct uec_mii_info *mii_info);
123static int genmii_update_link (struct uec_mii_info *mii_info);
124static int genmii_read_status (struct uec_mii_info *mii_info);
Andy Fleming09c04c22011-03-22 22:49:13 -0500125u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum);
126void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val);
Dave Liu7737d5c2006-11-03 12:11:15 -0600127
128/* Write value to the PHY for this device to the register at regnum, */
129/* waiting until the write is done before it returns. All PHY */
130/* configuration has to be done through the TSEC1 MIIM regs */
Andy Flemingda9d4612007-08-14 00:14:25 -0500131void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
Dave Liu7737d5c2006-11-03 12:11:15 -0600132{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100133 uec_private_t *ugeth = (uec_private_t *) dev->priv;
Andy Flemingda9d4612007-08-14 00:14:25 -0500134 uec_mii_t *ug_regs;
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100135 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
136 u32 tmp_reg;
Dave Liu7737d5c2006-11-03 12:11:15 -0600137
Richard Retanubun23c34af2009-06-17 16:00:41 -0400138
139#if defined(CONFIG_BITBANGMII)
140 u32 i = 0;
141
142 for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
143 if (strncmp(dev->name, bitbang_phy_port[i],
144 sizeof(dev->name)) == 0) {
145 (void)bb_miiphy_write(NULL, mii_id, regnum, value);
146 return;
147 }
148 }
149#endif /* CONFIG_BITBANGMII */
150
Andy Flemingda9d4612007-08-14 00:14:25 -0500151 ug_regs = ugeth->uec_mii_regs;
Dave Liu7737d5c2006-11-03 12:11:15 -0600152
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100153 /* Stop the MII management read cycle */
154 out_be32 (&ug_regs->miimcom, 0);
155 /* Setting up the MII Mangement Address Register */
156 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
157 out_be32 (&ug_regs->miimadd, tmp_reg);
Dave Liu7737d5c2006-11-03 12:11:15 -0600158
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100159 /* Setting up the MII Mangement Control Register with the value */
160 out_be32 (&ug_regs->miimcon, (u32) value);
Kim Phillipsee62ed32008-01-15 14:11:00 -0600161 sync();
Dave Liu7737d5c2006-11-03 12:11:15 -0600162
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100163 /* Wait till MII management write is complete */
164 while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY);
Dave Liu7737d5c2006-11-03 12:11:15 -0600165}
166
167/* Reads from register regnum in the PHY for device dev, */
168/* returning the value. Clears miimcom first. All PHY */
169/* configuration has to be done through the TSEC1 MIIM regs */
Andy Flemingda9d4612007-08-14 00:14:25 -0500170int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
Dave Liu7737d5c2006-11-03 12:11:15 -0600171{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100172 uec_private_t *ugeth = (uec_private_t *) dev->priv;
Andy Flemingda9d4612007-08-14 00:14:25 -0500173 uec_mii_t *ug_regs;
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100174 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
175 u32 tmp_reg;
176 u16 value;
Dave Liu7737d5c2006-11-03 12:11:15 -0600177
Richard Retanubun23c34af2009-06-17 16:00:41 -0400178
179#if defined(CONFIG_BITBANGMII)
180 u32 i = 0;
181
182 for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
183 if (strncmp(dev->name, bitbang_phy_port[i],
184 sizeof(dev->name)) == 0) {
185 (void)bb_miiphy_read(NULL, mii_id, regnum, &value);
186 return (value);
187 }
188 }
189#endif /* CONFIG_BITBANGMII */
190
Andy Flemingda9d4612007-08-14 00:14:25 -0500191 ug_regs = ugeth->uec_mii_regs;
Dave Liu7737d5c2006-11-03 12:11:15 -0600192
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100193 /* Setting up the MII Mangement Address Register */
194 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
195 out_be32 (&ug_regs->miimadd, tmp_reg);
Dave Liu7737d5c2006-11-03 12:11:15 -0600196
Kim Phillipsee62ed32008-01-15 14:11:00 -0600197 /* clear MII management command cycle */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100198 out_be32 (&ug_regs->miimcom, 0);
Kim Phillipsee62ed32008-01-15 14:11:00 -0600199 sync();
200
201 /* Perform an MII management read cycle */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100202 out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
Dave Liu7737d5c2006-11-03 12:11:15 -0600203
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100204 /* Wait till MII management write is complete */
205 while ((in_be32 (&ug_regs->miimind)) &
206 (MIIMIND_NOT_VALID | MIIMIND_BUSY));
Dave Liu7737d5c2006-11-03 12:11:15 -0600207
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100208 /* Read MII management status */
209 value = (u16) in_be32 (&ug_regs->miimstat);
210 if (value == 0xffff)
Joakim Tjernlund84a30472008-01-16 09:40:41 +0100211 ugphy_vdbg
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100212 ("read wrong value : mii_id %d,mii_reg %d, base %08x",
213 mii_id, mii_reg, (u32) & (ug_regs->miimcfg));
Dave Liu7737d5c2006-11-03 12:11:15 -0600214
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100215 return (value);
Dave Liu7737d5c2006-11-03 12:11:15 -0600216}
217
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100218void mii_clear_phy_interrupt (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600219{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100220 if (mii_info->phyinfo->ack_interrupt)
221 mii_info->phyinfo->ack_interrupt (mii_info);
Dave Liu7737d5c2006-11-03 12:11:15 -0600222}
223
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100224void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
225 u32 interrupts)
Dave Liu7737d5c2006-11-03 12:11:15 -0600226{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100227 mii_info->interrupts = interrupts;
228 if (mii_info->phyinfo->config_intr)
229 mii_info->phyinfo->config_intr (mii_info);
Dave Liu7737d5c2006-11-03 12:11:15 -0600230}
231
232/* Writes MII_ADVERTISE with the appropriate values, after
233 * sanitizing advertise to make sure only supported features
234 * are advertised
235 */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100236static void config_genmii_advert (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600237{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100238 u32 advertise;
239 u16 adv;
Dave Liu7737d5c2006-11-03 12:11:15 -0600240
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100241 /* Only allow advertising what this PHY supports */
242 mii_info->advertising &= mii_info->phyinfo->features;
243 advertise = mii_info->advertising;
Dave Liu7737d5c2006-11-03 12:11:15 -0600244
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100245 /* Setup standard advertisement */
Andy Fleming09c04c22011-03-22 22:49:13 -0500246 adv = uec_phy_read(mii_info, MII_ADVERTISE);
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100247 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
248 if (advertise & ADVERTISED_10baseT_Half)
249 adv |= ADVERTISE_10HALF;
250 if (advertise & ADVERTISED_10baseT_Full)
251 adv |= ADVERTISE_10FULL;
252 if (advertise & ADVERTISED_100baseT_Half)
253 adv |= ADVERTISE_100HALF;
254 if (advertise & ADVERTISED_100baseT_Full)
255 adv |= ADVERTISE_100FULL;
Andy Fleming09c04c22011-03-22 22:49:13 -0500256 uec_phy_write(mii_info, MII_ADVERTISE, adv);
Dave Liu7737d5c2006-11-03 12:11:15 -0600257}
258
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100259static void genmii_setup_forced (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600260{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100261 u16 ctrl;
262 u32 features = mii_info->phyinfo->features;
Dave Liu7737d5c2006-11-03 12:11:15 -0600263
Andy Fleming09c04c22011-03-22 22:49:13 -0500264 ctrl = uec_phy_read(mii_info, MII_BMCR);
Dave Liu7737d5c2006-11-03 12:11:15 -0600265
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500266 ctrl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
267 BMCR_SPEED1000 | BMCR_ANENABLE);
268 ctrl |= BMCR_RESET;
Dave Liu7737d5c2006-11-03 12:11:15 -0600269
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100270 switch (mii_info->speed) {
271 case SPEED_1000:
272 if (features & (SUPPORTED_1000baseT_Half
273 | SUPPORTED_1000baseT_Full)) {
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500274 ctrl |= BMCR_SPEED1000;
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100275 break;
276 }
277 mii_info->speed = SPEED_100;
278 case SPEED_100:
279 if (features & (SUPPORTED_100baseT_Half
280 | SUPPORTED_100baseT_Full)) {
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500281 ctrl |= BMCR_SPEED100;
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100282 break;
283 }
284 mii_info->speed = SPEED_10;
285 case SPEED_10:
286 if (features & (SUPPORTED_10baseT_Half
287 | SUPPORTED_10baseT_Full))
288 break;
289 default: /* Unsupported speed! */
290 ugphy_err ("%s: Bad speed!", mii_info->dev->name);
291 break;
292 }
Dave Liu7737d5c2006-11-03 12:11:15 -0600293
Andy Fleming09c04c22011-03-22 22:49:13 -0500294 uec_phy_write(mii_info, MII_BMCR, ctrl);
Dave Liu7737d5c2006-11-03 12:11:15 -0600295}
296
297/* Enable and Restart Autonegotiation */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100298static void genmii_restart_aneg (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600299{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100300 u16 ctl;
Dave Liu7737d5c2006-11-03 12:11:15 -0600301
Andy Fleming09c04c22011-03-22 22:49:13 -0500302 ctl = uec_phy_read(mii_info, MII_BMCR);
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500303 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
Andy Fleming09c04c22011-03-22 22:49:13 -0500304 uec_phy_write(mii_info, MII_BMCR, ctl);
Dave Liu7737d5c2006-11-03 12:11:15 -0600305}
306
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100307static int gbit_config_aneg (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600308{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100309 u16 adv;
310 u32 advertise;
Dave Liu7737d5c2006-11-03 12:11:15 -0600311
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100312 if (mii_info->autoneg) {
313 /* Configure the ADVERTISE register */
314 config_genmii_advert (mii_info);
315 advertise = mii_info->advertising;
Dave Liu7737d5c2006-11-03 12:11:15 -0600316
Andy Fleming09c04c22011-03-22 22:49:13 -0500317 adv = uec_phy_read(mii_info, MII_CTRL1000);
Kumar Gala2b21ec92011-01-19 03:36:40 -0600318 adv &= ~(ADVERTISE_1000FULL |
319 ADVERTISE_1000HALF);
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100320 if (advertise & SUPPORTED_1000baseT_Half)
Kumar Gala2b21ec92011-01-19 03:36:40 -0600321 adv |= ADVERTISE_1000HALF;
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100322 if (advertise & SUPPORTED_1000baseT_Full)
Kumar Gala2b21ec92011-01-19 03:36:40 -0600323 adv |= ADVERTISE_1000FULL;
Andy Fleming09c04c22011-03-22 22:49:13 -0500324 uec_phy_write(mii_info, MII_CTRL1000, adv);
Dave Liu7737d5c2006-11-03 12:11:15 -0600325
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100326 /* Start/Restart aneg */
327 genmii_restart_aneg (mii_info);
328 } else
329 genmii_setup_forced (mii_info);
Dave Liu7737d5c2006-11-03 12:11:15 -0600330
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100331 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600332}
333
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100334static int marvell_config_aneg (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600335{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100336 /* The Marvell PHY has an errata which requires
337 * that certain registers get written in order
338 * to restart autonegotiation */
Andy Fleming09c04c22011-03-22 22:49:13 -0500339 uec_phy_write(mii_info, MII_BMCR, BMCR_RESET);
Dave Liu7737d5c2006-11-03 12:11:15 -0600340
Andy Fleming09c04c22011-03-22 22:49:13 -0500341 uec_phy_write(mii_info, 0x1d, 0x1f);
342 uec_phy_write(mii_info, 0x1e, 0x200c);
343 uec_phy_write(mii_info, 0x1d, 0x5);
344 uec_phy_write(mii_info, 0x1e, 0);
345 uec_phy_write(mii_info, 0x1e, 0x100);
Dave Liu7737d5c2006-11-03 12:11:15 -0600346
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100347 gbit_config_aneg (mii_info);
Dave Liu7737d5c2006-11-03 12:11:15 -0600348
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100349 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600350}
351
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100352static int genmii_config_aneg (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600353{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100354 if (mii_info->autoneg) {
Joakim Tjernlundf29c1812010-08-10 16:36:49 +0200355 /* Speed up the common case, if link is already up, speed and
356 duplex match, skip auto neg as it already matches */
357 if (!genmii_read_status(mii_info) && mii_info->link)
358 if (mii_info->duplex == DUPLEX_FULL &&
359 mii_info->speed == SPEED_100)
360 if (mii_info->advertising &
361 ADVERTISED_100baseT_Full)
362 return 0;
363
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100364 config_genmii_advert (mii_info);
365 genmii_restart_aneg (mii_info);
366 } else
367 genmii_setup_forced (mii_info);
Dave Liu7737d5c2006-11-03 12:11:15 -0600368
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100369 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600370}
371
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100372static int genmii_update_link (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600373{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100374 u16 status;
Dave Liu7737d5c2006-11-03 12:11:15 -0600375
Kim Phillipsee62ed32008-01-15 14:11:00 -0600376 /* Status is read once to clear old link state */
Andy Fleming09c04c22011-03-22 22:49:13 -0500377 uec_phy_read(mii_info, MII_BMSR);
Dave Liu7737d5c2006-11-03 12:11:15 -0600378
Kim Phillipsee62ed32008-01-15 14:11:00 -0600379 /*
380 * Wait if the link is up, and autonegotiation is in progress
381 * (ie - we're capable and it's not done)
382 */
Andy Fleming09c04c22011-03-22 22:49:13 -0500383 status = uec_phy_read(mii_info, MII_BMSR);
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500384 if ((status & BMSR_LSTATUS) && (status & BMSR_ANEGCAPABLE)
385 && !(status & BMSR_ANEGCOMPLETE)) {
Kim Phillipsee62ed32008-01-15 14:11:00 -0600386 int i = 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600387
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500388 while (!(status & BMSR_ANEGCOMPLETE)) {
Kim Phillipsee62ed32008-01-15 14:11:00 -0600389 /*
390 * Timeout reached ?
391 */
392 if (i > UGETH_AN_TIMEOUT) {
393 mii_info->link = 0;
394 return 0;
395 }
396
Kim Phillipsf30b61542008-02-27 16:08:22 -0600397 i++;
Kim Phillipsee62ed32008-01-15 14:11:00 -0600398 udelay(1000); /* 1 ms */
Andy Fleming09c04c22011-03-22 22:49:13 -0500399 status = uec_phy_read(mii_info, MII_BMSR);
Kim Phillipsee62ed32008-01-15 14:11:00 -0600400 }
401 mii_info->link = 1;
Kim Phillipsee62ed32008-01-15 14:11:00 -0600402 } else {
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500403 if (status & BMSR_LSTATUS)
Kim Phillipsee62ed32008-01-15 14:11:00 -0600404 mii_info->link = 1;
405 else
406 mii_info->link = 0;
407 }
Dave Liu7737d5c2006-11-03 12:11:15 -0600408
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100409 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600410}
411
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100412static int genmii_read_status (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600413{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100414 u16 status;
415 int err;
Dave Liu7737d5c2006-11-03 12:11:15 -0600416
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100417 /* Update the link, but return if there
418 * was an error */
419 err = genmii_update_link (mii_info);
420 if (err)
421 return err;
Dave Liu7737d5c2006-11-03 12:11:15 -0600422
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100423 if (mii_info->autoneg) {
Andy Fleming09c04c22011-03-22 22:49:13 -0500424 status = uec_phy_read(mii_info, MII_STAT1000);
Dave Liu7737d5c2006-11-03 12:11:15 -0600425
Anton Vorontsov91cdaa32008-03-24 20:46:24 +0300426 if (status & (LPA_1000FULL | LPA_1000HALF)) {
427 mii_info->speed = SPEED_1000;
428 if (status & LPA_1000FULL)
429 mii_info->duplex = DUPLEX_FULL;
430 else
431 mii_info->duplex = DUPLEX_HALF;
432 } else {
Andy Fleming09c04c22011-03-22 22:49:13 -0500433 status = uec_phy_read(mii_info, MII_LPA);
Anton Vorontsov91cdaa32008-03-24 20:46:24 +0300434
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500435 if (status & (LPA_10FULL | LPA_100FULL))
Anton Vorontsov91cdaa32008-03-24 20:46:24 +0300436 mii_info->duplex = DUPLEX_FULL;
437 else
438 mii_info->duplex = DUPLEX_HALF;
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500439 if (status & (LPA_100FULL | LPA_100HALF))
Anton Vorontsov91cdaa32008-03-24 20:46:24 +0300440 mii_info->speed = SPEED_100;
441 else
442 mii_info->speed = SPEED_10;
443 }
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100444 mii_info->pause = 0;
445 }
446 /* On non-aneg, we assume what we put in BMCR is the speed,
447 * though magic-aneg shouldn't prevent this case from occurring
448 */
Dave Liu7737d5c2006-11-03 12:11:15 -0600449
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100450 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600451}
452
Anton Vorontsov300615d2008-03-24 20:46:34 +0300453static int bcm_init(struct uec_mii_info *mii_info)
454{
455 struct eth_device *edev = mii_info->dev;
456 uec_private_t *uec = edev->priv;
457
458 gbit_config_aneg(mii_info);
459
Andy Fleming865ff852011-04-13 00:37:12 -0500460 if ((uec->uec_info->enet_interface_type ==
461 PHY_INTERFACE_MODE_RGMII_RXID) &&
462 (uec->uec_info->speed == SPEED_1000)) {
Anton Vorontsov300615d2008-03-24 20:46:34 +0300463 u16 val;
464 int cnt = 50;
465
466 /* Wait for aneg to complete. */
467 do
Andy Fleming09c04c22011-03-22 22:49:13 -0500468 val = uec_phy_read(mii_info, MII_BMSR);
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500469 while (--cnt && !(val & BMSR_ANEGCOMPLETE));
Anton Vorontsov300615d2008-03-24 20:46:34 +0300470
471 /* Set RDX clk delay. */
Andy Fleming09c04c22011-03-22 22:49:13 -0500472 uec_phy_write(mii_info, 0x18, 0x7 | (7 << 12));
Anton Vorontsov300615d2008-03-24 20:46:34 +0300473
Andy Fleming09c04c22011-03-22 22:49:13 -0500474 val = uec_phy_read(mii_info, 0x18);
Anton Vorontsov300615d2008-03-24 20:46:34 +0300475 /* Set RDX-RXC skew. */
476 val |= (1 << 8);
477 val |= (7 | (7 << 12));
478 /* Write bits 14:0. */
479 val |= (1 << 15);
Andy Fleming09c04c22011-03-22 22:49:13 -0500480 uec_phy_write(mii_info, 0x18, val);
Anton Vorontsov300615d2008-03-24 20:46:34 +0300481 }
482
483 return 0;
484}
485
Andy Fleming09c04c22011-03-22 22:49:13 -0500486static int uec_marvell_init(struct uec_mii_info *mii_info)
Haiying Wang41410ee2008-09-24 11:42:12 -0500487{
488 struct eth_device *edev = mii_info->dev;
489 uec_private_t *uec = edev->priv;
Andy Fleming865ff852011-04-13 00:37:12 -0500490 phy_interface_t iface = uec->uec_info->enet_interface_type;
Heiko Schocher582c55a2010-01-20 09:04:28 +0100491 int speed = uec->uec_info->speed;
Haiying Wang41410ee2008-09-24 11:42:12 -0500492
Andy Fleming865ff852011-04-13 00:37:12 -0500493 if ((speed == SPEED_1000) &&
494 (iface == PHY_INTERFACE_MODE_RGMII_ID ||
495 iface == PHY_INTERFACE_MODE_RGMII_RXID ||
496 iface == PHY_INTERFACE_MODE_RGMII_TXID)) {
Haiying Wang41410ee2008-09-24 11:42:12 -0500497 int temp;
498
Andy Fleming09c04c22011-03-22 22:49:13 -0500499 temp = uec_phy_read(mii_info, MII_M1111_PHY_EXT_CR);
Andy Fleming865ff852011-04-13 00:37:12 -0500500 if (iface == PHY_INTERFACE_MODE_RGMII_ID) {
Anton Vorontsov6185f802009-09-16 23:21:53 +0400501 temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY;
Andy Fleming865ff852011-04-13 00:37:12 -0500502 } else if (iface == PHY_INTERFACE_MODE_RGMII_RXID) {
Anton Vorontsov6185f802009-09-16 23:21:53 +0400503 temp &= ~MII_M1111_TX_DELAY;
504 temp |= MII_M1111_RX_DELAY;
Andy Fleming865ff852011-04-13 00:37:12 -0500505 } else if (iface == PHY_INTERFACE_MODE_RGMII_TXID) {
Anton Vorontsov6185f802009-09-16 23:21:53 +0400506 temp &= ~MII_M1111_RX_DELAY;
507 temp |= MII_M1111_TX_DELAY;
508 }
Andy Fleming09c04c22011-03-22 22:49:13 -0500509 uec_phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp);
Haiying Wang41410ee2008-09-24 11:42:12 -0500510
Andy Fleming09c04c22011-03-22 22:49:13 -0500511 temp = uec_phy_read(mii_info, MII_M1111_PHY_EXT_SR);
Haiying Wang41410ee2008-09-24 11:42:12 -0500512 temp &= ~MII_M1111_HWCFG_MODE_MASK;
513 temp |= MII_M1111_HWCFG_MODE_RGMII;
Andy Fleming09c04c22011-03-22 22:49:13 -0500514 uec_phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp);
Haiying Wang41410ee2008-09-24 11:42:12 -0500515
Andy Fleming09c04c22011-03-22 22:49:13 -0500516 uec_phy_write(mii_info, MII_BMCR, BMCR_RESET);
Haiying Wang41410ee2008-09-24 11:42:12 -0500517 }
518
519 return 0;
520}
521
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100522static int marvell_read_status (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600523{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100524 u16 status;
525 int err;
Dave Liu7737d5c2006-11-03 12:11:15 -0600526
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100527 /* Update the link, but return if there
528 * was an error */
529 err = genmii_update_link (mii_info);
530 if (err)
531 return err;
Dave Liu7737d5c2006-11-03 12:11:15 -0600532
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100533 /* If the link is up, read the speed and duplex */
534 /* If we aren't autonegotiating, assume speeds
535 * are as set */
536 if (mii_info->autoneg && mii_info->link) {
537 int speed;
Dave Liu7737d5c2006-11-03 12:11:15 -0600538
Andy Fleming09c04c22011-03-22 22:49:13 -0500539 status = uec_phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS);
Dave Liu7737d5c2006-11-03 12:11:15 -0600540
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100541 /* Get the duplexity */
542 if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
543 mii_info->duplex = DUPLEX_FULL;
544 else
545 mii_info->duplex = DUPLEX_HALF;
Dave Liu7737d5c2006-11-03 12:11:15 -0600546
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100547 /* Get the speed */
548 speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
549 switch (speed) {
550 case MII_M1011_PHY_SPEC_STATUS_1000:
551 mii_info->speed = SPEED_1000;
552 break;
553 case MII_M1011_PHY_SPEC_STATUS_100:
554 mii_info->speed = SPEED_100;
555 break;
556 default:
557 mii_info->speed = SPEED_10;
558 break;
559 }
560 mii_info->pause = 0;
561 }
562
563 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600564}
565
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100566static int marvell_ack_interrupt (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600567{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100568 /* Clear the interrupts by reading the reg */
Andy Fleming09c04c22011-03-22 22:49:13 -0500569 uec_phy_read(mii_info, MII_M1011_IEVENT);
Dave Liu7737d5c2006-11-03 12:11:15 -0600570
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100571 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600572}
573
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100574static int marvell_config_intr (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600575{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100576 if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
Andy Fleming09c04c22011-03-22 22:49:13 -0500577 uec_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100578 else
Andy Fleming09c04c22011-03-22 22:49:13 -0500579 uec_phy_write(mii_info, MII_M1011_IMASK,
580 MII_M1011_IMASK_CLEAR);
Dave Liu7737d5c2006-11-03 12:11:15 -0600581
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100582 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600583}
584
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100585static int dm9161_init (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600586{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100587 /* Reset the PHY */
Andy Fleming09c04c22011-03-22 22:49:13 -0500588 uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) |
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500589 BMCR_RESET);
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100590 /* PHY and MAC connect */
Andy Fleming09c04c22011-03-22 22:49:13 -0500591 uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) &
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500592 ~BMCR_ISOLATE);
Kim Phillipsee62ed32008-01-15 14:11:00 -0600593
Andy Fleming09c04c22011-03-22 22:49:13 -0500594 uec_phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
Kim Phillipsee62ed32008-01-15 14:11:00 -0600595
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100596 config_genmii_advert (mii_info);
597 /* Start/restart aneg */
598 genmii_config_aneg (mii_info);
Dave Liu7737d5c2006-11-03 12:11:15 -0600599
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100600 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600601}
602
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100603static int dm9161_config_aneg (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600604{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100605 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600606}
607
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100608static int dm9161_read_status (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600609{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100610 u16 status;
611 int err;
Dave Liu7737d5c2006-11-03 12:11:15 -0600612
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100613 /* Update the link, but return if there was an error */
614 err = genmii_update_link (mii_info);
615 if (err)
616 return err;
617 /* If the link is up, read the speed and duplex
618 If we aren't autonegotiating assume speeds are as set */
619 if (mii_info->autoneg && mii_info->link) {
Andy Fleming09c04c22011-03-22 22:49:13 -0500620 status = uec_phy_read(mii_info, MII_DM9161_SCSR);
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100621 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
622 mii_info->speed = SPEED_100;
623 else
624 mii_info->speed = SPEED_10;
Dave Liu7737d5c2006-11-03 12:11:15 -0600625
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100626 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
627 mii_info->duplex = DUPLEX_FULL;
628 else
629 mii_info->duplex = DUPLEX_HALF;
630 }
Dave Liu7737d5c2006-11-03 12:11:15 -0600631
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100632 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600633}
634
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100635static int dm9161_ack_interrupt (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600636{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100637 /* Clear the interrupt by reading the reg */
Andy Fleming09c04c22011-03-22 22:49:13 -0500638 uec_phy_read(mii_info, MII_DM9161_INTR);
Dave Liu7737d5c2006-11-03 12:11:15 -0600639
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100640 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600641}
642
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100643static int dm9161_config_intr (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600644{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100645 if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
Andy Fleming09c04c22011-03-22 22:49:13 -0500646 uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100647 else
Andy Fleming09c04c22011-03-22 22:49:13 -0500648 uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
Dave Liu7737d5c2006-11-03 12:11:15 -0600649
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100650 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600651}
652
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100653static void dm9161_close (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600654{
655}
656
Richard Retanubunedf3fe72008-10-23 09:08:18 -0400657static int fixed_phy_aneg (struct uec_mii_info *mii_info)
658{
659 mii_info->autoneg = 0; /* Turn off auto negotiation for fixed phy */
660 return 0;
661}
662
663static int fixed_phy_read_status (struct uec_mii_info *mii_info)
664{
665 int i = 0;
666
667 for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
Richard Retanubun1443cd72009-07-01 14:04:05 -0400668 if (strncmp(mii_info->dev->name, fixed_phy_port[i].name,
669 strlen(mii_info->dev->name)) == 0) {
Richard Retanubunedf3fe72008-10-23 09:08:18 -0400670 mii_info->speed = fixed_phy_port[i].speed;
671 mii_info->duplex = fixed_phy_port[i].duplex;
672 mii_info->link = 1; /* Link is always UP */
673 mii_info->pause = 0;
674 break;
675 }
676 }
677 return 0;
678}
679
Heiko Schocher8b69b562008-11-20 09:57:14 +0100680static int smsc_config_aneg (struct uec_mii_info *mii_info)
681{
682 return 0;
683}
684
685static int smsc_read_status (struct uec_mii_info *mii_info)
686{
687 u16 status;
688 int err;
689
690 /* Update the link, but return if there
691 * was an error */
692 err = genmii_update_link (mii_info);
693 if (err)
694 return err;
695
696 /* If the link is up, read the speed and duplex */
697 /* If we aren't autonegotiating, assume speeds
698 * are as set */
699 if (mii_info->autoneg && mii_info->link) {
700 int val;
701
Andy Fleming09c04c22011-03-22 22:49:13 -0500702 status = uec_phy_read(mii_info, 0x1f);
Heiko Schocher8b69b562008-11-20 09:57:14 +0100703 val = (status & 0x1c) >> 2;
704
705 switch (val) {
706 case 1:
707 mii_info->duplex = DUPLEX_HALF;
708 mii_info->speed = SPEED_10;
709 break;
710 case 5:
711 mii_info->duplex = DUPLEX_FULL;
712 mii_info->speed = SPEED_10;
713 break;
714 case 2:
715 mii_info->duplex = DUPLEX_HALF;
716 mii_info->speed = SPEED_100;
717 break;
718 case 6:
719 mii_info->duplex = DUPLEX_FULL;
720 mii_info->speed = SPEED_100;
721 break;
722 }
723 mii_info->pause = 0;
724 }
725
726 return 0;
727}
728
Dave Liu7737d5c2006-11-03 12:11:15 -0600729static struct phy_info phy_info_dm9161 = {
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100730 .phy_id = 0x0181b880,
731 .phy_id_mask = 0x0ffffff0,
732 .name = "Davicom DM9161E",
733 .init = dm9161_init,
734 .config_aneg = dm9161_config_aneg,
735 .read_status = dm9161_read_status,
736 .close = dm9161_close,
Dave Liu7737d5c2006-11-03 12:11:15 -0600737};
738
739static struct phy_info phy_info_dm9161a = {
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100740 .phy_id = 0x0181b8a0,
741 .phy_id_mask = 0x0ffffff0,
742 .name = "Davicom DM9161A",
743 .features = MII_BASIC_FEATURES,
744 .init = dm9161_init,
745 .config_aneg = dm9161_config_aneg,
746 .read_status = dm9161_read_status,
747 .ack_interrupt = dm9161_ack_interrupt,
748 .config_intr = dm9161_config_intr,
749 .close = dm9161_close,
Dave Liu7737d5c2006-11-03 12:11:15 -0600750};
751
752static struct phy_info phy_info_marvell = {
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100753 .phy_id = 0x01410c00,
754 .phy_id_mask = 0xffffff00,
755 .name = "Marvell 88E11x1",
756 .features = MII_GBIT_FEATURES,
Andy Fleming09c04c22011-03-22 22:49:13 -0500757 .init = &uec_marvell_init,
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100758 .config_aneg = &marvell_config_aneg,
759 .read_status = &marvell_read_status,
760 .ack_interrupt = &marvell_ack_interrupt,
761 .config_intr = &marvell_config_intr,
Dave Liu7737d5c2006-11-03 12:11:15 -0600762};
763
Anton Vorontsov300615d2008-03-24 20:46:34 +0300764static struct phy_info phy_info_bcm5481 = {
765 .phy_id = 0x0143bca0,
766 .phy_id_mask = 0xffffff0,
767 .name = "Broadcom 5481",
768 .features = MII_GBIT_FEATURES,
769 .read_status = genmii_read_status,
770 .init = bcm_init,
771};
772
Richard Retanubunedf3fe72008-10-23 09:08:18 -0400773static struct phy_info phy_info_fixedphy = {
774 .phy_id = CONFIG_FIXED_PHY,
775 .phy_id_mask = CONFIG_FIXED_PHY,
776 .name = "Fixed PHY",
777 .config_aneg = fixed_phy_aneg,
778 .read_status = fixed_phy_read_status,
779};
780
Heiko Schocher8b69b562008-11-20 09:57:14 +0100781static struct phy_info phy_info_smsclan8700 = {
782 .phy_id = 0x0007c0c0,
783 .phy_id_mask = 0xfffffff0,
784 .name = "SMSC LAN8700",
785 .features = MII_BASIC_FEATURES,
786 .config_aneg = smsc_config_aneg,
787 .read_status = smsc_read_status,
788};
789
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100790static struct phy_info phy_info_genmii = {
791 .phy_id = 0x00000000,
792 .phy_id_mask = 0x00000000,
793 .name = "Generic MII",
794 .features = MII_BASIC_FEATURES,
795 .config_aneg = genmii_config_aneg,
796 .read_status = genmii_read_status,
Dave Liu7737d5c2006-11-03 12:11:15 -0600797};
798
799static struct phy_info *phy_info[] = {
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100800 &phy_info_dm9161,
801 &phy_info_dm9161a,
802 &phy_info_marvell,
Anton Vorontsov300615d2008-03-24 20:46:34 +0300803 &phy_info_bcm5481,
Heiko Schocher8b69b562008-11-20 09:57:14 +0100804 &phy_info_smsclan8700,
Richard Retanubunedf3fe72008-10-23 09:08:18 -0400805 &phy_info_fixedphy,
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100806 &phy_info_genmii,
807 NULL
Dave Liu7737d5c2006-11-03 12:11:15 -0600808};
809
Andy Fleming09c04c22011-03-22 22:49:13 -0500810u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum)
Dave Liu7737d5c2006-11-03 12:11:15 -0600811{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100812 return mii_info->mdio_read (mii_info->dev, mii_info->mii_id, regnum);
Dave Liu7737d5c2006-11-03 12:11:15 -0600813}
814
Andy Fleming09c04c22011-03-22 22:49:13 -0500815void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val)
Dave Liu7737d5c2006-11-03 12:11:15 -0600816{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100817 mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val);
Dave Liu7737d5c2006-11-03 12:11:15 -0600818}
819
820/* Use the PHY ID registers to determine what type of PHY is attached
821 * to device dev. return a struct phy_info structure describing that PHY
822 */
Andy Flemingda9d4612007-08-14 00:14:25 -0500823struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600824{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100825 u16 phy_reg;
826 u32 phy_ID;
827 int i;
828 struct phy_info *theInfo = NULL;
Dave Liu7737d5c2006-11-03 12:11:15 -0600829
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100830 /* Grab the bits from PHYIR1, and put them in the upper half */
Andy Fleming09c04c22011-03-22 22:49:13 -0500831 phy_reg = uec_phy_read(mii_info, MII_PHYSID1);
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100832 phy_ID = (phy_reg & 0xffff) << 16;
Dave Liu7737d5c2006-11-03 12:11:15 -0600833
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100834 /* Grab the bits from PHYIR2, and put them in the lower half */
Andy Fleming09c04c22011-03-22 22:49:13 -0500835 phy_reg = uec_phy_read(mii_info, MII_PHYSID2);
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100836 phy_ID |= (phy_reg & 0xffff);
Dave Liu7737d5c2006-11-03 12:11:15 -0600837
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100838 /* loop through all the known PHY types, and find one that */
839 /* matches the ID we read from the PHY. */
840 for (i = 0; phy_info[i]; i++)
841 if (phy_info[i]->phy_id ==
842 (phy_ID & phy_info[i]->phy_id_mask)) {
843 theInfo = phy_info[i];
844 break;
845 }
Dave Liu7737d5c2006-11-03 12:11:15 -0600846
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100847 /* This shouldn't happen, as we have generic PHY support */
848 if (theInfo == NULL) {
849 ugphy_info ("UEC: PHY id %x is not supported!", phy_ID);
850 return NULL;
851 } else {
852 ugphy_info ("UEC: PHY is %s (%x)", theInfo->name, phy_ID);
853 }
Dave Liu7737d5c2006-11-03 12:11:15 -0600854
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100855 return theInfo;
Dave Liu7737d5c2006-11-03 12:11:15 -0600856}
857
Andy Fleming865ff852011-04-13 00:37:12 -0500858void marvell_phy_interface_mode(struct eth_device *dev, phy_interface_t type,
859 int speed)
Dave Liu7737d5c2006-11-03 12:11:15 -0600860{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100861 uec_private_t *uec = (uec_private_t *) dev->priv;
862 struct uec_mii_info *mii_info;
Kim Phillipsf655ade2008-02-27 15:06:39 -0600863 u16 status;
Dave Liu7737d5c2006-11-03 12:11:15 -0600864
865 if (!uec->mii_info) {
Kim Phillipsf30b61542008-02-27 16:08:22 -0600866 printf ("%s: the PHY not initialized\n", __FUNCTION__);
Dave Liu7737d5c2006-11-03 12:11:15 -0600867 return;
868 }
869 mii_info = uec->mii_info;
870
Andy Fleming865ff852011-04-13 00:37:12 -0500871 if (type == PHY_INTERFACE_MODE_RGMII) {
872 if (speed == SPEED_100) {
Andy Fleming09c04c22011-03-22 22:49:13 -0500873 uec_phy_write(mii_info, 0x00, 0x9140);
874 uec_phy_write(mii_info, 0x1d, 0x001f);
875 uec_phy_write(mii_info, 0x1e, 0x200c);
876 uec_phy_write(mii_info, 0x1d, 0x0005);
877 uec_phy_write(mii_info, 0x1e, 0x0000);
878 uec_phy_write(mii_info, 0x1e, 0x0100);
879 uec_phy_write(mii_info, 0x09, 0x0e00);
880 uec_phy_write(mii_info, 0x04, 0x01e1);
881 uec_phy_write(mii_info, 0x00, 0x9140);
882 uec_phy_write(mii_info, 0x00, 0x1000);
Heiko Schocher582c55a2010-01-20 09:04:28 +0100883 udelay (100000);
Andy Fleming09c04c22011-03-22 22:49:13 -0500884 uec_phy_write(mii_info, 0x00, 0x2900);
885 uec_phy_write(mii_info, 0x14, 0x0cd2);
886 uec_phy_write(mii_info, 0x00, 0xa100);
887 uec_phy_write(mii_info, 0x09, 0x0000);
888 uec_phy_write(mii_info, 0x1b, 0x800b);
889 uec_phy_write(mii_info, 0x04, 0x05e1);
890 uec_phy_write(mii_info, 0x00, 0xa100);
891 uec_phy_write(mii_info, 0x00, 0x2100);
Heiko Schocher582c55a2010-01-20 09:04:28 +0100892 udelay (1000000);
Andy Fleming865ff852011-04-13 00:37:12 -0500893 } else if (speed == SPEED_10) {
Andy Fleming09c04c22011-03-22 22:49:13 -0500894 uec_phy_write(mii_info, 0x14, 0x8e40);
895 uec_phy_write(mii_info, 0x1b, 0x800b);
896 uec_phy_write(mii_info, 0x14, 0x0c82);
897 uec_phy_write(mii_info, 0x00, 0x8100);
Heiko Schocher582c55a2010-01-20 09:04:28 +0100898 udelay (1000000);
899 }
Dave Liu7737d5c2006-11-03 12:11:15 -0600900 }
Kim Phillipsf655ade2008-02-27 15:06:39 -0600901
902 /* handle 88e1111 rev.B2 erratum 5.6 */
903 if (mii_info->autoneg) {
Andy Fleming09c04c22011-03-22 22:49:13 -0500904 status = uec_phy_read(mii_info, MII_BMCR);
905 uec_phy_write(mii_info, MII_BMCR, status | BMCR_ANENABLE);
Kim Phillipsf655ade2008-02-27 15:06:39 -0600906 }
907 /* now the B2 will correctly report autoneg completion status */
Dave Liu7737d5c2006-11-03 12:11:15 -0600908}
909
Heiko Schocher582c55a2010-01-20 09:04:28 +0100910void change_phy_interface_mode (struct eth_device *dev,
Andy Fleming865ff852011-04-13 00:37:12 -0500911 phy_interface_t type, int speed)
Dave Liu7737d5c2006-11-03 12:11:15 -0600912{
913#ifdef CONFIG_PHY_MODE_NEED_CHANGE
Heiko Schocher582c55a2010-01-20 09:04:28 +0100914 marvell_phy_interface_mode (dev, type, speed);
Dave Liu7737d5c2006-11-03 12:11:15 -0600915#endif
916}