| Mike Frysinger | d4d7730 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 1 | /* DO NOT EDIT THIS FILE |
| 2 | * Automatically generated by generate-def-headers.xsl |
| 3 | * DO NOT EDIT THIS FILE |
| 4 | */ |
| 5 | |
| 6 | #ifndef __BFIN_DEF_ADSP_EDN_BF542_extended__ |
| 7 | #define __BFIN_DEF_ADSP_EDN_BF542_extended__ |
| 8 | |
| 9 | #define SIC_IMASK0 0xFFC0010C /* System Interrupt Mask Register 0 */ |
| 10 | #define SIC_IMASK1 0xFFC00110 /* System Interrupt Mask Register 1 */ |
| 11 | #define SIC_IMASK2 0xFFC00114 /* System Interrupt Mask Register 2 */ |
| 12 | #define SIC_ISR0 0xFFC00118 /* System Interrupt Status Register 0 */ |
| 13 | #define SIC_ISR1 0xFFC0011C /* System Interrupt Status Register 1 */ |
| 14 | #define SIC_ISR2 0xFFC00120 /* System Interrupt Status Register 2 */ |
| 15 | #define SIC_IWR0 0xFFC00124 /* System Interrupt Wakeup Register 0 */ |
| 16 | #define SIC_IWR1 0xFFC00128 /* System Interrupt Wakeup Register 1 */ |
| 17 | #define SIC_IWR2 0xFFC0012C /* System Interrupt Wakeup Register 2 */ |
| 18 | #define SIC_IAR0 0xFFC00130 /* System Interrupt Assignment Register 0 */ |
| 19 | #define SIC_IAR1 0xFFC00134 /* System Interrupt Assignment Register 1 */ |
| 20 | #define SIC_IAR2 0xFFC00138 /* System Interrupt Assignment Register 2 */ |
| 21 | #define SIC_IAR3 0xFFC0013C /* System Interrupt Assignment Register 3 */ |
| 22 | #define SIC_IAR4 0xFFC00140 /* System Interrupt Assignment Register 4 */ |
| 23 | #define SIC_IAR5 0xFFC00144 /* System Interrupt Assignment Register 5 */ |
| 24 | #define SIC_IAR6 0xFFC00148 /* System Interrupt Assignment Register 6 */ |
| 25 | #define SIC_IAR7 0xFFC0014C /* System Interrupt Assignment Register 7 */ |
| 26 | #define SIC_IAR8 0xFFC00150 /* System Interrupt Assignment Register 8 */ |
| 27 | #define SIC_IAR9 0xFFC00154 /* System Interrupt Assignment Register 9 */ |
| 28 | #define SIC_IAR10 0xFFC00158 /* System Interrupt Assignment Register 10 */ |
| 29 | #define SIC_IAR11 0xFFC0015C /* System Interrupt Assignment Register 11 */ |
| 30 | #define DMAC0_TCPER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */ |
| 31 | #define DMAC0_TCCNT 0xFFC00B10 /* DMA Controller 0 Current Counts Register */ |
| 32 | #define DMAC1_TCPER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */ |
| 33 | #define DMAC1_TCCNT 0xFFC01B10 /* DMA Controller 1 Current Counts Register */ |
| 34 | #define DMAC1_PERIMUX 0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */ |
| 35 | #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ |
| 36 | #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ |
| 37 | #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ |
| 38 | #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ |
| 39 | #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ |
| 40 | #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ |
| 41 | #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ |
| 42 | #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ |
| 43 | #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ |
| 44 | #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ |
| 45 | #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ |
| 46 | #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ |
| 47 | #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ |
| 48 | #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ |
| 49 | #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ |
| 50 | #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ |
| 51 | #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ |
| 52 | #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ |
| 53 | #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ |
| 54 | #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ |
| 55 | #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ |
| 56 | #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ |
| 57 | #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ |
| 58 | #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ |
| 59 | #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ |
| 60 | #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ |
| 61 | #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ |
| 62 | #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ |
| 63 | #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ |
| 64 | #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ |
| 65 | #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ |
| 66 | #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ |
| 67 | #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ |
| 68 | #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ |
| 69 | #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ |
| 70 | #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ |
| 71 | #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ |
| 72 | #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ |
| 73 | #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ |
| 74 | #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ |
| 75 | #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ |
| 76 | #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ |
| 77 | #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ |
| 78 | #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ |
| 79 | #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ |
| 80 | #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ |
| 81 | #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ |
| 82 | #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ |
| 83 | #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ |
| 84 | #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ |
| 85 | #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ |
| 86 | #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ |
| 87 | #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ |
| 88 | #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ |
| 89 | #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ |
| 90 | #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ |
| 91 | #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ |
| 92 | #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ |
| 93 | #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ |
| 94 | #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ |
| 95 | #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ |
| 96 | #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ |
| 97 | #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ |
| 98 | #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ |
| 99 | #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ |
| 100 | #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ |
| 101 | #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ |
| 102 | #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ |
| 103 | #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ |
| 104 | #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ |
| 105 | #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ |
| 106 | #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ |
| 107 | #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ |
| 108 | #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ |
| 109 | #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ |
| 110 | #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ |
| 111 | #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ |
| 112 | #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ |
| 113 | #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ |
| 114 | #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ |
| 115 | #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ |
| 116 | #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ |
| 117 | #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ |
| 118 | #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ |
| 119 | #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ |
| 120 | #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ |
| 121 | #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ |
| 122 | #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ |
| 123 | #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ |
| 124 | #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ |
| 125 | #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ |
| 126 | #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ |
| 127 | #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ |
| 128 | #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ |
| 129 | #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ |
| 130 | #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ |
| 131 | #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ |
| 132 | #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ |
| 133 | #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ |
| 134 | #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ |
| 135 | #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ |
| 136 | #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ |
| 137 | #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ |
| 138 | #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ |
| 139 | #define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ |
| 140 | #define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ |
| 141 | #define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ |
| 142 | #define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ |
| 143 | #define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ |
| 144 | #define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ |
| 145 | #define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ |
| 146 | #define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ |
| 147 | #define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ |
| 148 | #define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ |
| 149 | #define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ |
| 150 | #define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ |
| 151 | #define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ |
| 152 | #define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ |
| 153 | #define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ |
| 154 | #define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ |
| 155 | #define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ |
| 156 | #define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ |
| 157 | #define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ |
| 158 | #define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ |
| 159 | #define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ |
| 160 | #define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ |
| 161 | #define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ |
| 162 | #define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ |
| 163 | #define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ |
| 164 | #define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ |
| 165 | #define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ |
| 166 | #define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ |
| 167 | #define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ |
| 168 | #define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ |
| 169 | #define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ |
| 170 | #define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ |
| 171 | #define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ |
| 172 | #define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ |
| 173 | #define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ |
| 174 | #define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ |
| 175 | #define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ |
| 176 | #define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ |
| 177 | #define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ |
| 178 | #define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ |
| 179 | #define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ |
| 180 | #define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ |
| 181 | #define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ |
| 182 | #define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ |
| 183 | #define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ |
| 184 | #define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ |
| 185 | #define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ |
| 186 | #define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ |
| 187 | #define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ |
| 188 | #define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ |
| 189 | #define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ |
| 190 | #define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ |
| 191 | #define DMA12_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */ |
| 192 | #define DMA12_START_ADDR 0xFFC01C04 /* DMA Channel 12 Start Address Register */ |
| 193 | #define DMA12_CONFIG 0xFFC01C08 /* DMA Channel 12 Configuration Register */ |
| 194 | #define DMA12_X_COUNT 0xFFC01C10 /* DMA Channel 12 X Count Register */ |
| 195 | #define DMA12_X_MODIFY 0xFFC01C14 /* DMA Channel 12 X Modify Register */ |
| 196 | #define DMA12_Y_COUNT 0xFFC01C18 /* DMA Channel 12 Y Count Register */ |
| 197 | #define DMA12_Y_MODIFY 0xFFC01C1C /* DMA Channel 12 Y Modify Register */ |
| 198 | #define DMA12_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */ |
| 199 | #define DMA12_CURR_ADDR 0xFFC01C24 /* DMA Channel 12 Current Address Register */ |
| 200 | #define DMA12_IRQ_STATUS 0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */ |
| 201 | #define DMA12_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */ |
| 202 | #define DMA12_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 12 Current X Count Register */ |
| 203 | #define DMA12_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 12 Current Y Count Register */ |
| 204 | #define DMA13_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */ |
| 205 | #define DMA13_START_ADDR 0xFFC01C44 /* DMA Channel 13 Start Address Register */ |
| 206 | #define DMA13_CONFIG 0xFFC01C48 /* DMA Channel 13 Configuration Register */ |
| 207 | #define DMA13_X_COUNT 0xFFC01C50 /* DMA Channel 13 X Count Register */ |
| 208 | #define DMA13_X_MODIFY 0xFFC01C54 /* DMA Channel 13 X Modify Register */ |
| 209 | #define DMA13_Y_COUNT 0xFFC01C58 /* DMA Channel 13 Y Count Register */ |
| 210 | #define DMA13_Y_MODIFY 0xFFC01C5C /* DMA Channel 13 Y Modify Register */ |
| 211 | #define DMA13_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */ |
| 212 | #define DMA13_CURR_ADDR 0xFFC01C64 /* DMA Channel 13 Current Address Register */ |
| 213 | #define DMA13_IRQ_STATUS 0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */ |
| 214 | #define DMA13_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */ |
| 215 | #define DMA13_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 13 Current X Count Register */ |
| 216 | #define DMA13_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 13 Current Y Count Register */ |
| 217 | #define DMA14_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */ |
| 218 | #define DMA14_START_ADDR 0xFFC01C84 /* DMA Channel 14 Start Address Register */ |
| 219 | #define DMA14_CONFIG 0xFFC01C88 /* DMA Channel 14 Configuration Register */ |
| 220 | #define DMA14_X_COUNT 0xFFC01C90 /* DMA Channel 14 X Count Register */ |
| 221 | #define DMA14_X_MODIFY 0xFFC01C94 /* DMA Channel 14 X Modify Register */ |
| 222 | #define DMA14_Y_COUNT 0xFFC01C98 /* DMA Channel 14 Y Count Register */ |
| 223 | #define DMA14_Y_MODIFY 0xFFC01C9C /* DMA Channel 14 Y Modify Register */ |
| 224 | #define DMA14_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */ |
| 225 | #define DMA14_CURR_ADDR 0xFFC01CA4 /* DMA Channel 14 Current Address Register */ |
| 226 | #define DMA14_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */ |
| 227 | #define DMA14_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */ |
| 228 | #define DMA14_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 14 Current X Count Register */ |
| 229 | #define DMA14_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */ |
| 230 | #define DMA15_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */ |
| 231 | #define DMA15_START_ADDR 0xFFC01CC4 /* DMA Channel 15 Start Address Register */ |
| 232 | #define DMA15_CONFIG 0xFFC01CC8 /* DMA Channel 15 Configuration Register */ |
| 233 | #define DMA15_X_COUNT 0xFFC01CD0 /* DMA Channel 15 X Count Register */ |
| 234 | #define DMA15_X_MODIFY 0xFFC01CD4 /* DMA Channel 15 X Modify Register */ |
| 235 | #define DMA15_Y_COUNT 0xFFC01CD8 /* DMA Channel 15 Y Count Register */ |
| 236 | #define DMA15_Y_MODIFY 0xFFC01CDC /* DMA Channel 15 Y Modify Register */ |
| 237 | #define DMA15_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */ |
| 238 | #define DMA15_CURR_ADDR 0xFFC01CE4 /* DMA Channel 15 Current Address Register */ |
| 239 | #define DMA15_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */ |
| 240 | #define DMA15_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */ |
| 241 | #define DMA15_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 15 Current X Count Register */ |
| 242 | #define DMA15_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */ |
| 243 | #define DMA16_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */ |
| 244 | #define DMA16_START_ADDR 0xFFC01D04 /* DMA Channel 16 Start Address Register */ |
| 245 | #define DMA16_CONFIG 0xFFC01D08 /* DMA Channel 16 Configuration Register */ |
| 246 | #define DMA16_X_COUNT 0xFFC01D10 /* DMA Channel 16 X Count Register */ |
| 247 | #define DMA16_X_MODIFY 0xFFC01D14 /* DMA Channel 16 X Modify Register */ |
| 248 | #define DMA16_Y_COUNT 0xFFC01D18 /* DMA Channel 16 Y Count Register */ |
| 249 | #define DMA16_Y_MODIFY 0xFFC01D1C /* DMA Channel 16 Y Modify Register */ |
| 250 | #define DMA16_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */ |
| 251 | #define DMA16_CURR_ADDR 0xFFC01D24 /* DMA Channel 16 Current Address Register */ |
| 252 | #define DMA16_IRQ_STATUS 0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */ |
| 253 | #define DMA16_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */ |
| 254 | #define DMA16_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 16 Current X Count Register */ |
| 255 | #define DMA16_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 16 Current Y Count Register */ |
| 256 | #define DMA17_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */ |
| 257 | #define DMA17_START_ADDR 0xFFC01D44 /* DMA Channel 17 Start Address Register */ |
| 258 | #define DMA17_CONFIG 0xFFC01D48 /* DMA Channel 17 Configuration Register */ |
| 259 | #define DMA17_X_COUNT 0xFFC01D50 /* DMA Channel 17 X Count Register */ |
| 260 | #define DMA17_X_MODIFY 0xFFC01D54 /* DMA Channel 17 X Modify Register */ |
| 261 | #define DMA17_Y_COUNT 0xFFC01D58 /* DMA Channel 17 Y Count Register */ |
| 262 | #define DMA17_Y_MODIFY 0xFFC01D5C /* DMA Channel 17 Y Modify Register */ |
| 263 | #define DMA17_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */ |
| 264 | #define DMA17_CURR_ADDR 0xFFC01D64 /* DMA Channel 17 Current Address Register */ |
| 265 | #define DMA17_IRQ_STATUS 0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */ |
| 266 | #define DMA17_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */ |
| 267 | #define DMA17_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 17 Current X Count Register */ |
| 268 | #define DMA17_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 17 Current Y Count Register */ |
| 269 | #define DMA18_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */ |
| 270 | #define DMA18_START_ADDR 0xFFC01D84 /* DMA Channel 18 Start Address Register */ |
| 271 | #define DMA18_CONFIG 0xFFC01D88 /* DMA Channel 18 Configuration Register */ |
| 272 | #define DMA18_X_COUNT 0xFFC01D90 /* DMA Channel 18 X Count Register */ |
| 273 | #define DMA18_X_MODIFY 0xFFC01D94 /* DMA Channel 18 X Modify Register */ |
| 274 | #define DMA18_Y_COUNT 0xFFC01D98 /* DMA Channel 18 Y Count Register */ |
| 275 | #define DMA18_Y_MODIFY 0xFFC01D9C /* DMA Channel 18 Y Modify Register */ |
| 276 | #define DMA18_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */ |
| 277 | #define DMA18_CURR_ADDR 0xFFC01DA4 /* DMA Channel 18 Current Address Register */ |
| 278 | #define DMA18_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */ |
| 279 | #define DMA18_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */ |
| 280 | #define DMA18_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 18 Current X Count Register */ |
| 281 | #define DMA18_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */ |
| 282 | #define DMA19_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */ |
| 283 | #define DMA19_START_ADDR 0xFFC01DC4 /* DMA Channel 19 Start Address Register */ |
| 284 | #define DMA19_CONFIG 0xFFC01DC8 /* DMA Channel 19 Configuration Register */ |
| 285 | #define DMA19_X_COUNT 0xFFC01DD0 /* DMA Channel 19 X Count Register */ |
| 286 | #define DMA19_X_MODIFY 0xFFC01DD4 /* DMA Channel 19 X Modify Register */ |
| 287 | #define DMA19_Y_COUNT 0xFFC01DD8 /* DMA Channel 19 Y Count Register */ |
| 288 | #define DMA19_Y_MODIFY 0xFFC01DDC /* DMA Channel 19 Y Modify Register */ |
| 289 | #define DMA19_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */ |
| 290 | #define DMA19_CURR_ADDR 0xFFC01DE4 /* DMA Channel 19 Current Address Register */ |
| 291 | #define DMA19_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */ |
| 292 | #define DMA19_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */ |
| 293 | #define DMA19_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 19 Current X Count Register */ |
| 294 | #define DMA19_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */ |
| 295 | #define DMA20_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */ |
| 296 | #define DMA20_START_ADDR 0xFFC01E04 /* DMA Channel 20 Start Address Register */ |
| 297 | #define DMA20_CONFIG 0xFFC01E08 /* DMA Channel 20 Configuration Register */ |
| 298 | #define DMA20_X_COUNT 0xFFC01E10 /* DMA Channel 20 X Count Register */ |
| 299 | #define DMA20_X_MODIFY 0xFFC01E14 /* DMA Channel 20 X Modify Register */ |
| 300 | #define DMA20_Y_COUNT 0xFFC01E18 /* DMA Channel 20 Y Count Register */ |
| 301 | #define DMA20_Y_MODIFY 0xFFC01E1C /* DMA Channel 20 Y Modify Register */ |
| 302 | #define DMA20_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */ |
| 303 | #define DMA20_CURR_ADDR 0xFFC01E24 /* DMA Channel 20 Current Address Register */ |
| 304 | #define DMA20_IRQ_STATUS 0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */ |
| 305 | #define DMA20_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */ |
| 306 | #define DMA20_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 20 Current X Count Register */ |
| 307 | #define DMA20_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 20 Current Y Count Register */ |
| 308 | #define DMA21_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */ |
| 309 | #define DMA21_START_ADDR 0xFFC01E44 /* DMA Channel 21 Start Address Register */ |
| 310 | #define DMA21_CONFIG 0xFFC01E48 /* DMA Channel 21 Configuration Register */ |
| 311 | #define DMA21_X_COUNT 0xFFC01E50 /* DMA Channel 21 X Count Register */ |
| 312 | #define DMA21_X_MODIFY 0xFFC01E54 /* DMA Channel 21 X Modify Register */ |
| 313 | #define DMA21_Y_COUNT 0xFFC01E58 /* DMA Channel 21 Y Count Register */ |
| 314 | #define DMA21_Y_MODIFY 0xFFC01E5C /* DMA Channel 21 Y Modify Register */ |
| 315 | #define DMA21_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */ |
| 316 | #define DMA21_CURR_ADDR 0xFFC01E64 /* DMA Channel 21 Current Address Register */ |
| 317 | #define DMA21_IRQ_STATUS 0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */ |
| 318 | #define DMA21_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */ |
| 319 | #define DMA21_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 21 Current X Count Register */ |
| 320 | #define DMA21_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 21 Current Y Count Register */ |
| 321 | #define DMA22_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */ |
| 322 | #define DMA22_START_ADDR 0xFFC01E84 /* DMA Channel 22 Start Address Register */ |
| 323 | #define DMA22_CONFIG 0xFFC01E88 /* DMA Channel 22 Configuration Register */ |
| 324 | #define DMA22_X_COUNT 0xFFC01E90 /* DMA Channel 22 X Count Register */ |
| 325 | #define DMA22_X_MODIFY 0xFFC01E94 /* DMA Channel 22 X Modify Register */ |
| 326 | #define DMA22_Y_COUNT 0xFFC01E98 /* DMA Channel 22 Y Count Register */ |
| 327 | #define DMA22_Y_MODIFY 0xFFC01E9C /* DMA Channel 22 Y Modify Register */ |
| 328 | #define DMA22_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */ |
| 329 | #define DMA22_CURR_ADDR 0xFFC01EA4 /* DMA Channel 22 Current Address Register */ |
| 330 | #define DMA22_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */ |
| 331 | #define DMA22_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */ |
| 332 | #define DMA22_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 22 Current X Count Register */ |
| 333 | #define DMA22_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */ |
| 334 | #define DMA23_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */ |
| 335 | #define DMA23_START_ADDR 0xFFC01EC4 /* DMA Channel 23 Start Address Register */ |
| 336 | #define DMA23_CONFIG 0xFFC01EC8 /* DMA Channel 23 Configuration Register */ |
| 337 | #define DMA23_X_COUNT 0xFFC01ED0 /* DMA Channel 23 X Count Register */ |
| 338 | #define DMA23_X_MODIFY 0xFFC01ED4 /* DMA Channel 23 X Modify Register */ |
| 339 | #define DMA23_Y_COUNT 0xFFC01ED8 /* DMA Channel 23 Y Count Register */ |
| 340 | #define DMA23_Y_MODIFY 0xFFC01EDC /* DMA Channel 23 Y Modify Register */ |
| 341 | #define DMA23_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */ |
| 342 | #define DMA23_CURR_ADDR 0xFFC01EE4 /* DMA Channel 23 Current Address Register */ |
| 343 | #define DMA23_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */ |
| 344 | #define DMA23_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */ |
| 345 | #define DMA23_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 23 Current X Count Register */ |
| 346 | #define DMA23_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */ |
| 347 | #define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */ |
| 348 | #define MDMA_D0_START_ADDR 0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */ |
| 349 | #define MDMA_D0_CONFIG 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */ |
| 350 | #define MDMA_D0_X_COUNT 0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */ |
| 351 | #define MDMA_D0_X_MODIFY 0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */ |
| 352 | #define MDMA_D0_Y_COUNT 0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */ |
| 353 | #define MDMA_D0_Y_MODIFY 0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */ |
| 354 | #define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ |
| 355 | #define MDMA_D0_CURR_ADDR 0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */ |
| 356 | #define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */ |
| 357 | #define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */ |
| 358 | #define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */ |
| 359 | #define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */ |
| 360 | #define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */ |
| 361 | #define MDMA_S0_START_ADDR 0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */ |
| 362 | #define MDMA_S0_CONFIG 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */ |
| 363 | #define MDMA_S0_X_COUNT 0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */ |
| 364 | #define MDMA_S0_X_MODIFY 0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */ |
| 365 | #define MDMA_S0_Y_COUNT 0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */ |
| 366 | #define MDMA_S0_Y_MODIFY 0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */ |
| 367 | #define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ |
| 368 | #define MDMA_S0_CURR_ADDR 0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */ |
| 369 | #define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */ |
| 370 | #define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */ |
| 371 | #define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */ |
| 372 | #define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */ |
| 373 | #define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */ |
| 374 | #define MDMA_D1_START_ADDR 0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */ |
| 375 | #define MDMA_D1_CONFIG 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */ |
| 376 | #define MDMA_D1_X_COUNT 0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */ |
| 377 | #define MDMA_D1_X_MODIFY 0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */ |
| 378 | #define MDMA_D1_Y_COUNT 0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */ |
| 379 | #define MDMA_D1_Y_MODIFY 0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */ |
| 380 | #define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ |
| 381 | #define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */ |
| 382 | #define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */ |
| 383 | #define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */ |
| 384 | #define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */ |
| 385 | #define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */ |
| 386 | #define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */ |
| 387 | #define MDMA_S1_START_ADDR 0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */ |
| 388 | #define MDMA_S1_CONFIG 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */ |
| 389 | #define MDMA_S1_X_COUNT 0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */ |
| 390 | #define MDMA_S1_X_MODIFY 0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */ |
| 391 | #define MDMA_S1_Y_COUNT 0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */ |
| 392 | #define MDMA_S1_Y_MODIFY 0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */ |
| 393 | #define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ |
| 394 | #define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */ |
| 395 | #define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */ |
| 396 | #define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */ |
| 397 | #define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */ |
| 398 | #define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */ |
| 399 | #define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */ |
| 400 | #define MDMA_D2_START_ADDR 0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */ |
| 401 | #define MDMA_D2_CONFIG 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */ |
| 402 | #define MDMA_D2_X_COUNT 0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */ |
| 403 | #define MDMA_D2_X_MODIFY 0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */ |
| 404 | #define MDMA_D2_Y_COUNT 0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */ |
| 405 | #define MDMA_D2_Y_MODIFY 0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */ |
| 406 | #define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ |
| 407 | #define MDMA_D2_CURR_ADDR 0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */ |
| 408 | #define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */ |
| 409 | #define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */ |
| 410 | #define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */ |
| 411 | #define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */ |
| 412 | #define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */ |
| 413 | #define MDMA_S2_START_ADDR 0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */ |
| 414 | #define MDMA_S2_CONFIG 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */ |
| 415 | #define MDMA_S2_X_COUNT 0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */ |
| 416 | #define MDMA_S2_X_MODIFY 0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */ |
| 417 | #define MDMA_S2_Y_COUNT 0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */ |
| 418 | #define MDMA_S2_Y_MODIFY 0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */ |
| 419 | #define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ |
| 420 | #define MDMA_S2_CURR_ADDR 0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */ |
| 421 | #define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */ |
| 422 | #define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */ |
| 423 | #define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */ |
| 424 | #define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */ |
| 425 | #define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */ |
| 426 | #define MDMA_D3_START_ADDR 0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */ |
| 427 | #define MDMA_D3_CONFIG 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */ |
| 428 | #define MDMA_D3_X_COUNT 0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */ |
| 429 | #define MDMA_D3_X_MODIFY 0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */ |
| 430 | #define MDMA_D3_Y_COUNT 0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */ |
| 431 | #define MDMA_D3_Y_MODIFY 0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */ |
| 432 | #define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ |
| 433 | #define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */ |
| 434 | #define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */ |
| 435 | #define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */ |
| 436 | #define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */ |
| 437 | #define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */ |
| 438 | #define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */ |
| 439 | #define MDMA_S3_START_ADDR 0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */ |
| 440 | #define MDMA_S3_CONFIG 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */ |
| 441 | #define MDMA_S3_X_COUNT 0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */ |
| 442 | #define MDMA_S3_X_MODIFY 0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */ |
| 443 | #define MDMA_S3_Y_COUNT 0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */ |
| 444 | #define MDMA_S3_Y_MODIFY 0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */ |
| 445 | #define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ |
| 446 | #define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */ |
| 447 | #define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */ |
| 448 | #define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */ |
| 449 | #define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */ |
| 450 | #define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */ |
| 451 | #define HMDMA0_CONTROL 0xFFC04500 /* Handshake MDMA0 Control Register */ |
| 452 | #define HMDMA0_ECINIT 0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */ |
| 453 | #define HMDMA0_BCINIT 0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */ |
| 454 | #define HMDMA0_ECOUNT 0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */ |
| 455 | #define HMDMA0_BCOUNT 0xFFC04518 /* Handshake MDMA0 Current Block Count Register */ |
| 456 | #define HMDMA0_ECURGENT 0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ |
| 457 | #define HMDMA0_ECOVERFLOW 0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ |
| 458 | #define HMDMA1_CONTROL 0xFFC04540 /* Handshake MDMA1 Control Register */ |
| 459 | #define HMDMA1_ECINIT 0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */ |
| 460 | #define HMDMA1_BCINIT 0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */ |
| 461 | #define HMDMA1_ECURGENT 0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ |
| 462 | #define HMDMA1_ECOVERFLOW 0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ |
| 463 | #define HMDMA1_ECOUNT 0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */ |
| 464 | #define HMDMA1_BCOUNT 0xFFC04558 /* Handshake MDMA1 Current Block Count Register */ |
| 465 | #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ |
| 466 | #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register */ |
| 467 | #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register */ |
| 468 | #define EBIU_MBSCTL 0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */ |
| 469 | #define EBIU_ARBSTAT 0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */ |
| 470 | #define EBIU_MODE 0xFFC00A14 /* Asynchronous Mode Control Register */ |
| 471 | #define EBIU_FCTL 0xFFC00A18 /* Asynchronous Memory Flash Control Register */ |
| 472 | #define EBIU_DDRCTL0 0xFFC00A20 /* DDR Memory Control 0 Register */ |
| 473 | #define EBIU_DDRCTL1 0xFFC00A24 /* DDR Memory Control 1 Register */ |
| 474 | #define EBIU_DDRCTL2 0xFFC00A28 /* DDR Memory Control 2 Register */ |
| 475 | #define EBIU_DDRCTL3 0xFFC00A2C /* DDR Memory Control 3 Register */ |
| 476 | #define EBIU_DDRQUE 0xFFC00A30 /* DDR Queue Configuration Register */ |
| 477 | #define EBIU_ERRADD 0xFFC00A34 /* DDR Error Address Register */ |
| 478 | #define EBIU_ERRMST 0xFFC00A38 /* DDR Error Master Register */ |
| 479 | #define EBIU_RSTCTL 0xFFC00A3C /* DDR Reset Control Register */ |
| 480 | #define EBIU_DDRBRC0 0xFFC00A60 /* DDR Bank0 Read Count Register */ |
| 481 | #define EBIU_DDRBRC1 0xFFC00A64 /* DDR Bank1 Read Count Register */ |
| 482 | #define EBIU_DDRBRC2 0xFFC00A68 /* DDR Bank2 Read Count Register */ |
| 483 | #define EBIU_DDRBRC3 0xFFC00A6C /* DDR Bank3 Read Count Register */ |
| 484 | #define EBIU_DDRBRC4 0xFFC00A70 /* DDR Bank4 Read Count Register */ |
| 485 | #define EBIU_DDRBRC5 0xFFC00A74 /* DDR Bank5 Read Count Register */ |
| 486 | #define EBIU_DDRBRC6 0xFFC00A78 /* DDR Bank6 Read Count Register */ |
| 487 | #define EBIU_DDRBRC7 0xFFC00A7C /* DDR Bank7 Read Count Register */ |
| 488 | #define EBIU_DDRBWC0 0xFFC00A80 /* DDR Bank0 Write Count Register */ |
| 489 | #define EBIU_DDRBWC1 0xFFC00A84 /* DDR Bank1 Write Count Register */ |
| 490 | #define EBIU_DDRBWC2 0xFFC00A88 /* DDR Bank2 Write Count Register */ |
| 491 | #define EBIU_DDRBWC3 0xFFC00A8C /* DDR Bank3 Write Count Register */ |
| 492 | #define EBIU_DDRBWC4 0xFFC00A90 /* DDR Bank4 Write Count Register */ |
| 493 | #define EBIU_DDRBWC5 0xFFC00A94 /* DDR Bank5 Write Count Register */ |
| 494 | #define EBIU_DDRBWC6 0xFFC00A98 /* DDR Bank6 Write Count Register */ |
| 495 | #define EBIU_DDRBWC7 0xFFC00A9C /* DDR Bank7 Write Count Register */ |
| 496 | #define EBIU_DDRACCT 0xFFC00AA0 /* DDR Activation Count Register */ |
| 497 | #define EBIU_DDRTACT 0xFFC00AA8 /* DDR Turn Around Count Register */ |
| 498 | #define EBIU_DDRARCT 0xFFC00AAC /* DDR Auto-refresh Count Register */ |
| 499 | #define EBIU_DDRGC0 0xFFC00AB0 /* DDR Grant Count 0 Register */ |
| 500 | #define EBIU_DDRGC1 0xFFC00AB4 /* DDR Grant Count 1 Register */ |
| 501 | #define EBIU_DDRGC2 0xFFC00AB8 /* DDR Grant Count 2 Register */ |
| 502 | #define EBIU_DDRGC3 0xFFC00ABC /* DDR Grant Count 3 Register */ |
| 503 | #define EBIU_DDRMCEN 0xFFC00AC0 /* DDR Metrics Counter Enable Register */ |
| 504 | #define EBIU_DDRMCCL 0xFFC00AC4 /* DDR Metrics Counter Clear Register */ |
| 505 | #define PORTA_FER 0xFFC014C0 /* Function Enable Register */ |
| 506 | #define PORTA 0xFFC014C4 /* GPIO Data Register */ |
| 507 | #define PORTA_SET 0xFFC014C8 /* GPIO Data Set Register */ |
| 508 | #define PORTA_CLEAR 0xFFC014CC /* GPIO Data Clear Register */ |
| 509 | #define PORTA_DIR_SET 0xFFC014D0 /* GPIO Direction Set Register */ |
| 510 | #define PORTA_DIR_CLEAR 0xFFC014D4 /* GPIO Direction Clear Register */ |
| 511 | #define PORTA_INEN 0xFFC014D8 /* GPIO Input Enable Register */ |
| 512 | #define PORTA_MUX 0xFFC014DC /* Multiplexer Control Register */ |
| 513 | #define PORTB_FER 0xFFC014E0 /* Function Enable Register */ |
| 514 | #define PORTB 0xFFC014E4 /* GPIO Data Register */ |
| 515 | #define PORTB_SET 0xFFC014E8 /* GPIO Data Set Register */ |
| 516 | #define PORTB_CLEAR 0xFFC014EC /* GPIO Data Clear Register */ |
| 517 | #define PORTB_DIR_SET 0xFFC014F0 /* GPIO Direction Set Register */ |
| 518 | #define PORTB_DIR_CLEAR 0xFFC014F4 /* GPIO Direction Clear Register */ |
| 519 | #define PORTB_INEN 0xFFC014F8 /* GPIO Input Enable Register */ |
| 520 | #define PORTB_MUX 0xFFC014FC /* Multiplexer Control Register */ |
| 521 | #define PORTC_FER 0xFFC01500 /* Function Enable Register */ |
| 522 | #define PORTC 0xFFC01504 /* GPIO Data Register */ |
| 523 | #define PORTC_SET 0xFFC01508 /* GPIO Data Set Register */ |
| 524 | #define PORTC_CLEAR 0xFFC0150C /* GPIO Data Clear Register */ |
| 525 | #define PORTC_DIR_SET 0xFFC01510 /* GPIO Direction Set Register */ |
| 526 | #define PORTC_DIR_CLEAR 0xFFC01514 /* GPIO Direction Clear Register */ |
| 527 | #define PORTC_INEN 0xFFC01518 /* GPIO Input Enable Register */ |
| 528 | #define PORTC_MUX 0xFFC0151C /* Multiplexer Control Register */ |
| 529 | #define PORTD_FER 0xFFC01520 /* Function Enable Register */ |
| 530 | #define PORTD 0xFFC01524 /* GPIO Data Register */ |
| 531 | #define PORTD_SET 0xFFC01528 /* GPIO Data Set Register */ |
| 532 | #define PORTD_CLEAR 0xFFC0152C /* GPIO Data Clear Register */ |
| 533 | #define PORTD_DIR_SET 0xFFC01530 /* GPIO Direction Set Register */ |
| 534 | #define PORTD_DIR_CLEAR 0xFFC01534 /* GPIO Direction Clear Register */ |
| 535 | #define PORTD_INEN 0xFFC01538 /* GPIO Input Enable Register */ |
| 536 | #define PORTD_MUX 0xFFC0153C /* Multiplexer Control Register */ |
| 537 | #define PORTE_FER 0xFFC01540 /* Function Enable Register */ |
| 538 | #define PORTE 0xFFC01544 /* GPIO Data Register */ |
| 539 | #define PORTE_SET 0xFFC01548 /* GPIO Data Set Register */ |
| 540 | #define PORTE_CLEAR 0xFFC0154C /* GPIO Data Clear Register */ |
| 541 | #define PORTE_DIR_SET 0xFFC01550 /* GPIO Direction Set Register */ |
| 542 | #define PORTE_DIR_CLEAR 0xFFC01554 /* GPIO Direction Clear Register */ |
| 543 | #define PORTE_INEN 0xFFC01558 /* GPIO Input Enable Register */ |
| 544 | #define PORTE_MUX 0xFFC0155C /* Multiplexer Control Register */ |
| 545 | #define PORTF_FER 0xFFC01560 /* Function Enable Register */ |
| 546 | #define PORTF 0xFFC01564 /* GPIO Data Register */ |
| 547 | #define PORTF_SET 0xFFC01568 /* GPIO Data Set Register */ |
| 548 | #define PORTF_CLEAR 0xFFC0156C /* GPIO Data Clear Register */ |
| 549 | #define PORTF_DIR_SET 0xFFC01570 /* GPIO Direction Set Register */ |
| 550 | #define PORTF_DIR_CLEAR 0xFFC01574 /* GPIO Direction Clear Register */ |
| 551 | #define PORTF_INEN 0xFFC01578 /* GPIO Input Enable Register */ |
| 552 | #define PORTF_MUX 0xFFC0157C /* Multiplexer Control Register */ |
| 553 | #define PORTG_FER 0xFFC01580 /* Function Enable Register */ |
| 554 | #define PORTG 0xFFC01584 /* GPIO Data Register */ |
| 555 | #define PORTG_SET 0xFFC01588 /* GPIO Data Set Register */ |
| 556 | #define PORTG_CLEAR 0xFFC0158C /* GPIO Data Clear Register */ |
| 557 | #define PORTG_DIR_SET 0xFFC01590 /* GPIO Direction Set Register */ |
| 558 | #define PORTG_DIR_CLEAR 0xFFC01594 /* GPIO Direction Clear Register */ |
| 559 | #define PORTG_INEN 0xFFC01598 /* GPIO Input Enable Register */ |
| 560 | #define PORTG_MUX 0xFFC0159C /* Multiplexer Control Register */ |
| 561 | #define PORTH_FER 0xFFC015A0 /* Function Enable Register */ |
| 562 | #define PORTH 0xFFC015A4 /* GPIO Data Register */ |
| 563 | #define PORTH_SET 0xFFC015A8 /* GPIO Data Set Register */ |
| 564 | #define PORTH_CLEAR 0xFFC015AC /* GPIO Data Clear Register */ |
| 565 | #define PORTH_DIR_SET 0xFFC015B0 /* GPIO Direction Set Register */ |
| 566 | #define PORTH_DIR_CLEAR 0xFFC015B4 /* GPIO Direction Clear Register */ |
| 567 | #define PORTH_INEN 0xFFC015B8 /* GPIO Input Enable Register */ |
| 568 | #define PORTH_MUX 0xFFC015BC /* Multiplexer Control Register */ |
| 569 | #define PORTI_FER 0xFFC015C0 /* Function Enable Register */ |
| 570 | #define PORTI 0xFFC015C4 /* GPIO Data Register */ |
| 571 | #define PORTI_SET 0xFFC015C8 /* GPIO Data Set Register */ |
| 572 | #define PORTI_CLEAR 0xFFC015CC /* GPIO Data Clear Register */ |
| 573 | #define PORTI_DIR_SET 0xFFC015D0 /* GPIO Direction Set Register */ |
| 574 | #define PORTI_DIR_CLEAR 0xFFC015D4 /* GPIO Direction Clear Register */ |
| 575 | #define PORTI_INEN 0xFFC015D8 /* GPIO Input Enable Register */ |
| 576 | #define PORTI_MUX 0xFFC015DC /* Multiplexer Control Register */ |
| 577 | #define PORTJ_FER 0xFFC015E0 /* Function Enable Register */ |
| 578 | #define PORTJ 0xFFC015E4 /* GPIO Data Register */ |
| 579 | #define PORTJ_SET 0xFFC015E8 /* GPIO Data Set Register */ |
| 580 | #define PORTJ_CLEAR 0xFFC015EC /* GPIO Data Clear Register */ |
| 581 | #define PORTJ_DIR_SET 0xFFC015F0 /* GPIO Direction Set Register */ |
| 582 | #define PORTJ_DIR_CLEAR 0xFFC015F4 /* GPIO Direction Clear Register */ |
| 583 | #define PORTJ_INEN 0xFFC015F8 /* GPIO Input Enable Register */ |
| 584 | #define PORTJ_MUX 0xFFC015FC /* Multiplexer Control Register */ |
| 585 | #define PINT0_MASK_SET 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */ |
| 586 | #define PINT0_MASK_CLEAR 0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */ |
| 587 | #define PINT0_IRQ 0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */ |
| 588 | #define PINT0_ASSIGN 0xFFC0140C /* Pin Interrupt 0 Port Assign Register */ |
| 589 | #define PINT0_EDGE_SET 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */ |
| 590 | #define PINT0_EDGE_CLEAR 0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */ |
| 591 | #define PINT0_INVERT_SET 0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */ |
| 592 | #define PINT0_INVERT_CLEAR 0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */ |
| 593 | #define PINT0_PINSTATE 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */ |
| 594 | #define PINT0_LATCH 0xFFC01424 /* Pin Interrupt 0 Latch Register */ |
| 595 | #define PINT1_MASK_SET 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */ |
| 596 | #define PINT1_MASK_CLEAR 0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */ |
| 597 | #define PINT1_IRQ 0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */ |
| 598 | #define PINT1_ASSIGN 0xFFC0143C /* Pin Interrupt 1 Port Assign Register */ |
| 599 | #define PINT1_EDGE_SET 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */ |
| 600 | #define PINT1_EDGE_CLEAR 0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */ |
| 601 | #define PINT1_INVERT_SET 0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */ |
| 602 | #define PINT1_INVERT_CLEAR 0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */ |
| 603 | #define PINT1_PINSTATE 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */ |
| 604 | #define PINT1_LATCH 0xFFC01454 /* Pin Interrupt 1 Latch Register */ |
| 605 | #define PINT2_MASK_SET 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */ |
| 606 | #define PINT2_MASK_CLEAR 0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */ |
| 607 | #define PINT2_IRQ 0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */ |
| 608 | #define PINT2_ASSIGN 0xFFC0146C /* Pin Interrupt 2 Port Assign Register */ |
| 609 | #define PINT2_EDGE_SET 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */ |
| 610 | #define PINT2_EDGE_CLEAR 0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */ |
| 611 | #define PINT2_INVERT_SET 0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */ |
| 612 | #define PINT2_INVERT_CLEAR 0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */ |
| 613 | #define PINT2_PINSTATE 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */ |
| 614 | #define PINT2_LATCH 0xFFC01484 /* Pin Interrupt 2 Latch Register */ |
| 615 | #define PINT3_MASK_SET 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */ |
| 616 | #define PINT3_MASK_CLEAR 0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */ |
| 617 | #define PINT3_IRQ 0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */ |
| 618 | #define PINT3_ASSIGN 0xFFC0149C /* Pin Interrupt 3 Port Assign Register */ |
| 619 | #define PINT3_EDGE_SET 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */ |
| 620 | #define PINT3_EDGE_CLEAR 0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */ |
| 621 | #define PINT3_INVERT_SET 0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */ |
| 622 | #define PINT3_INVERT_CLEAR 0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */ |
| 623 | #define PINT3_PINSTATE 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */ |
| 624 | #define PINT3_LATCH 0xFFC014B4 /* Pin Interrupt 3 Latch Register */ |
| 625 | #define TIMER0_CONFIG 0xFFC01600 /* Timer 0 Configuration Register */ |
| 626 | #define TIMER0_COUNTER 0xFFC01604 /* Timer 0 Counter Register */ |
| 627 | #define TIMER0_PERIOD 0xFFC01608 /* Timer 0 Period Register */ |
| 628 | #define TIMER0_WIDTH 0xFFC0160C /* Timer 0 Width Register */ |
| 629 | #define TIMER1_CONFIG 0xFFC01610 /* Timer 1 Configuration Register */ |
| 630 | #define TIMER1_COUNTER 0xFFC01614 /* Timer 1 Counter Register */ |
| 631 | #define TIMER1_PERIOD 0xFFC01618 /* Timer 1 Period Register */ |
| 632 | #define TIMER1_WIDTH 0xFFC0161C /* Timer 1 Width Register */ |
| 633 | #define TIMER2_CONFIG 0xFFC01620 /* Timer 2 Configuration Register */ |
| 634 | #define TIMER2_COUNTER 0xFFC01624 /* Timer 2 Counter Register */ |
| 635 | #define TIMER2_PERIOD 0xFFC01628 /* Timer 2 Period Register */ |
| 636 | #define TIMER2_WIDTH 0xFFC0162C /* Timer 2 Width Register */ |
| 637 | #define TIMER3_CONFIG 0xFFC01630 /* Timer 3 Configuration Register */ |
| 638 | #define TIMER3_COUNTER 0xFFC01634 /* Timer 3 Counter Register */ |
| 639 | #define TIMER3_PERIOD 0xFFC01638 /* Timer 3 Period Register */ |
| 640 | #define TIMER3_WIDTH 0xFFC0163C /* Timer 3 Width Register */ |
| 641 | #define TIMER4_CONFIG 0xFFC01640 /* Timer 4 Configuration Register */ |
| 642 | #define TIMER4_COUNTER 0xFFC01644 /* Timer 4 Counter Register */ |
| 643 | #define TIMER4_PERIOD 0xFFC01648 /* Timer 4 Period Register */ |
| 644 | #define TIMER4_WIDTH 0xFFC0164C /* Timer 4 Width Register */ |
| 645 | #define TIMER5_CONFIG 0xFFC01650 /* Timer 5 Configuration Register */ |
| 646 | #define TIMER5_COUNTER 0xFFC01654 /* Timer 5 Counter Register */ |
| 647 | #define TIMER5_PERIOD 0xFFC01658 /* Timer 5 Period Register */ |
| 648 | #define TIMER5_WIDTH 0xFFC0165C /* Timer 5 Width Register */ |
| 649 | #define TIMER6_CONFIG 0xFFC01660 /* Timer 6 Configuration Register */ |
| 650 | #define TIMER6_COUNTER 0xFFC01664 /* Timer 6 Counter Register */ |
| 651 | #define TIMER6_PERIOD 0xFFC01668 /* Timer 6 Period Register */ |
| 652 | #define TIMER6_WIDTH 0xFFC0166C /* Timer 6 Width Register */ |
| 653 | #define TIMER7_CONFIG 0xFFC01670 /* Timer 7 Configuration Register */ |
| 654 | #define TIMER7_COUNTER 0xFFC01674 /* Timer 7 Counter Register */ |
| 655 | #define TIMER7_PERIOD 0xFFC01678 /* Timer 7 Period Register */ |
| 656 | #define TIMER7_WIDTH 0xFFC0167C /* Timer 7 Width Register */ |
| 657 | #define TIMER_ENABLE0 0xFFC01680 /* Timer Group of 8 Enable Register */ |
| 658 | #define TIMER_DISABLE0 0xFFC01684 /* Timer Group of 8 Disable Register */ |
| 659 | #define TIMER_STATUS0 0xFFC01688 /* Timer Group of 8 Status Register */ |
| 660 | #define TCNTL 0xFFE03000 /* Core Timer Control Register */ |
| 661 | #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ |
| 662 | #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ |
| 663 | #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ |
| 664 | #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ |
| 665 | #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ |
| 666 | #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ |
| 667 | #define CNT_CONFIG 0xFFC04200 /* Configuration Register */ |
| 668 | #define CNT_IMASK 0xFFC04204 /* Interrupt Mask Register */ |
| 669 | #define CNT_STATUS 0xFFC04208 /* Status Register */ |
| 670 | #define CNT_COMMAND 0xFFC0420C /* Command Register */ |
| 671 | #define CNT_DEBOUNCE 0xFFC04210 /* Debounce Register */ |
| 672 | #define CNT_COUNTER 0xFFC04214 /* Counter Register */ |
| 673 | #define CNT_MAX 0xFFC04218 /* Maximal Count Register */ |
| 674 | #define CNT_MIN 0xFFC0421C /* Minimal Count Register */ |
| 675 | #define RTC_STAT 0xFFC00300 /* RTC Status Register */ |
| 676 | #define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ |
| 677 | #define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ |
| 678 | #define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ |
| 679 | #define RTC_ALARM 0xFFC00310 /* RTC Alarm Register */ |
| 680 | #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */ |
| 681 | #define OTP_CONTROL 0xFFC04300 /* OTP/Fuse Control Register */ |
| 682 | #define OTP_BEN 0xFFC04304 /* OTP/Fuse Byte Enable */ |
| 683 | #define OTP_STATUS 0xFFC04308 /* OTP/Fuse Status */ |
| 684 | #define OTP_TIMING 0xFFC0430C /* OTP/Fuse Access Timing */ |
| 685 | #define SECURE_SYSSWT 0xFFC04320 /* Secure System Switches */ |
| 686 | #define SECURE_CONTROL 0xFFC04324 /* Secure Control */ |
| 687 | #define SECURE_STATUS 0xFFC04328 /* Secure Status */ |
| 688 | #define OTP_DATA0 0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ |
| 689 | #define OTP_DATA1 0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ |
| 690 | #define OTP_DATA2 0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ |
| 691 | #define OTP_DATA3 0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ |
| 692 | #define PLL_CTL 0xFFC00000 /* PLL Control Register */ |
| 693 | #define PLL_DIV 0xFFC00004 /* PLL Divisor Register */ |
| 694 | #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ |
| 695 | #define PLL_STAT 0xFFC0000C /* PLL Status Register */ |
| 696 | #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ |
| 697 | #define KPAD_CTL 0xFFC04100 /* Controls keypad module enable and disable */ |
| 698 | #define KPAD_PRESCALE 0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */ |
| 699 | #define KPAD_MSEL 0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */ |
| 700 | #define KPAD_ROWCOL 0xFFC0410C /* Captures the row and column output values of the keys pressed */ |
| 701 | #define KPAD_STAT 0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */ |
| 702 | #define KPAD_SOFTEVAL 0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */ |
| 703 | #define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */ |
| 704 | #define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */ |
| 705 | #define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */ |
| 706 | #define SDH_COMMAND 0xFFC0390C /* SDH Command */ |
| 707 | #define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */ |
| 708 | #define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */ |
| 709 | #define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */ |
| 710 | #define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */ |
| 711 | #define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */ |
| 712 | #define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */ |
| 713 | #define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */ |
| 714 | #define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */ |
| 715 | #define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */ |
| 716 | #define SDH_STATUS 0xFFC03934 /* SDH Status */ |
| 717 | #define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */ |
| 718 | #define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */ |
| 719 | #define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */ |
| 720 | #define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */ |
| 721 | #define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */ |
| 722 | #define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */ |
| 723 | #define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */ |
| 724 | #define SDH_CFG 0xFFC039C8 /* SDH Configuration */ |
| 725 | #define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */ |
| 726 | #define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */ |
| 727 | #define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */ |
| 728 | #define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */ |
| 729 | #define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */ |
| 730 | #define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */ |
| 731 | #define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */ |
| 732 | #define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */ |
| 733 | #define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */ |
| 734 | #define ATAPI_CONTROL 0xFFC03800 /* ATAPI Control Register */ |
| 735 | #define ATAPI_STATUS 0xFFC03804 /* ATAPI Status Register */ |
| 736 | #define ATAPI_DEV_ADDR 0xFFC03808 /* ATAPI Device Register Address */ |
| 737 | #define ATAPI_DEV_TXBUF 0xFFC0380C /* ATAPI Device Register Write Data */ |
| 738 | #define ATAPI_DEV_RXBUF 0xFFC03810 /* ATAPI Device Register Read Data */ |
| 739 | #define ATAPI_INT_MASK 0xFFC03814 /* ATAPI Interrupt Mask Register */ |
| 740 | #define ATAPI_INT_STATUS 0xFFC03818 /* ATAPI Interrupt Status Register */ |
| 741 | #define ATAPI_XFER_LEN 0xFFC0381C /* ATAPI Length of Transfer */ |
| 742 | #define ATAPI_LINE_STATUS 0xFFC03820 /* ATAPI Line Status */ |
| 743 | #define ATAPI_SM_STATE 0xFFC03824 /* ATAPI State Machine Status */ |
| 744 | #define ATAPI_TERMINATE 0xFFC03828 /* ATAPI Host Terminate */ |
| 745 | #define ATAPI_PIO_TFRCNT 0xFFC0382C /* ATAPI PIO mode transfer count */ |
| 746 | #define ATAPI_DMA_TFRCNT 0xFFC03830 /* ATAPI DMA mode transfer count */ |
| 747 | #define ATAPI_UMAIN_TFRCNT 0xFFC03834 /* ATAPI UDMAIN transfer count */ |
| 748 | #define ATAPI_UDMAOUT_TFRCNT 0xFFC03838 /* ATAPI UDMAOUT transfer count */ |
| 749 | #define ATAPI_REG_TIM_0 0xFFC03840 /* ATAPI Register Transfer Timing 0 */ |
| 750 | #define ATAPI_PIO_TIM_0 0xFFC03844 /* ATAPI PIO Timing 0 Register */ |
| 751 | #define ATAPI_PIO_TIM_1 0xFFC03848 /* ATAPI PIO Timing 1 Register */ |
| 752 | #define ATAPI_MULTI_TIM_0 0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */ |
| 753 | #define ATAPI_MULTI_TIM_1 0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */ |
| 754 | #define ATAPI_MULTI_TIM_2 0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */ |
| 755 | #define ATAPI_ULTRA_TIM_0 0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */ |
| 756 | #define ATAPI_ULTRA_TIM_1 0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */ |
| 757 | #define ATAPI_ULTRA_TIM_2 0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */ |
| 758 | #define ATAPI_ULTRA_TIM_3 0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */ |
| 759 | #define NFC_CTL 0xFFC03B00 /* NAND Control Register */ |
| 760 | #define NFC_STAT 0xFFC03B04 /* NAND Status Register */ |
| 761 | #define NFC_IRQSTAT 0xFFC03B08 /* NAND Interrupt Status Register */ |
| 762 | #define NFC_IRQMASK 0xFFC03B0C /* NAND Interrupt Mask Register */ |
| 763 | #define NFC_ECC0 0xFFC03B10 /* NAND ECC Register 0 */ |
| 764 | #define NFC_ECC1 0xFFC03B14 /* NAND ECC Register 1 */ |
| 765 | #define NFC_ECC2 0xFFC03B18 /* NAND ECC Register 2 */ |
| 766 | #define NFC_ECC3 0xFFC03B1C /* NAND ECC Register 3 */ |
| 767 | #define NFC_COUNT 0xFFC03B20 /* NAND ECC Count Register */ |
| 768 | #define NFC_RST 0xFFC03B24 /* NAND ECC Reset Register */ |
| 769 | #define NFC_PGCTL 0xFFC03B28 /* NAND Page Control Register */ |
| 770 | #define NFC_READ 0xFFC03B2C /* NAND Read Data Register */ |
| 771 | #define NFC_ADDR 0xFFC03B40 /* NAND Address Register */ |
| 772 | #define NFC_CMD 0xFFC03B44 /* NAND Command Register */ |
| 773 | #define NFC_DATA_WR 0xFFC03B48 /* NAND Data Write Register */ |
| 774 | #define NFC_DATA_RD 0xFFC03B4C /* NAND Data Read Register */ |
| 775 | #define EPPI1_STATUS 0xFFC01300 /* EPPI1 Status Register */ |
| 776 | #define EPPI1_HCOUNT 0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */ |
| 777 | #define EPPI1_HDELAY 0xFFC01308 /* EPPI1 Horizontal Delay Count Register */ |
| 778 | #define EPPI1_VCOUNT 0xFFC0130C /* EPPI1 Vertical Transfer Count Register */ |
| 779 | #define EPPI1_VDELAY 0xFFC01310 /* EPPI1 Vertical Delay Count Register */ |
| 780 | #define EPPI1_FRAME 0xFFC01314 /* EPPI1 Lines per Frame Register */ |
| 781 | #define EPPI1_LINE 0xFFC01318 /* EPPI1 Samples per Line Register */ |
| 782 | #define EPPI1_CLKDIV 0xFFC0131C /* EPPI1 Clock Divide Register */ |
| 783 | #define EPPI1_CONTROL 0xFFC01320 /* EPPI1 Control Register */ |
| 784 | #define EPPI1_FS1W_HBL 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */ |
| 785 | #define EPPI1_FS1P_AVPL 0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */ |
| 786 | #define EPPI1_FS2W_LVB 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */ |
| 787 | #define EPPI1_FS2P_LAVF 0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */ |
| 788 | #define EPPI1_CLIP 0xFFC01334 /* EPPI1 Clipping Register */ |
| 789 | #define EPPI2_STATUS 0xFFC02900 /* EPPI2 Status Register */ |
| 790 | #define EPPI2_HCOUNT 0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */ |
| 791 | #define EPPI2_HDELAY 0xFFC02908 /* EPPI2 Horizontal Delay Count Register */ |
| 792 | #define EPPI2_VCOUNT 0xFFC0290C /* EPPI2 Vertical Transfer Count Register */ |
| 793 | #define EPPI2_VDELAY 0xFFC02910 /* EPPI2 Vertical Delay Count Register */ |
| 794 | #define EPPI2_FRAME 0xFFC02914 /* EPPI2 Lines per Frame Register */ |
| 795 | #define EPPI2_LINE 0xFFC02918 /* EPPI2 Samples per Line Register */ |
| 796 | #define EPPI2_CLKDIV 0xFFC0291C /* EPPI2 Clock Divide Register */ |
| 797 | #define EPPI2_CONTROL 0xFFC02920 /* EPPI2 Control Register */ |
| 798 | #define EPPI2_FS1W_HBL 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */ |
| 799 | #define EPPI2_FS1P_AVPL 0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */ |
| 800 | #define EPPI2_FS2W_LVB 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */ |
| 801 | #define EPPI2_FS2P_LAVF 0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */ |
| 802 | #define EPPI2_CLIP 0xFFC02934 /* EPPI2 Clipping Register */ |
| 803 | #define CAN0_MC1 0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */ |
| 804 | #define CAN0_MD1 0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */ |
| 805 | #define CAN0_TRS1 0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */ |
| 806 | #define CAN0_TRR1 0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */ |
| 807 | #define CAN0_TA1 0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */ |
| 808 | #define CAN0_AA1 0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */ |
| 809 | #define CAN0_RMP1 0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */ |
| 810 | #define CAN0_RML1 0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */ |
| 811 | #define CAN0_MBTIF1 0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */ |
| 812 | #define CAN0_MBRIF1 0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */ |
| 813 | #define CAN0_MBIM1 0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */ |
| 814 | #define CAN0_RFH1 0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */ |
| 815 | #define CAN0_OPSS1 0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */ |
| 816 | #define CAN0_MC2 0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */ |
| 817 | #define CAN0_MD2 0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */ |
| 818 | #define CAN0_TRS2 0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */ |
| 819 | #define CAN0_TRR2 0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */ |
| 820 | #define CAN0_TA2 0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */ |
| 821 | #define CAN0_AA2 0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */ |
| 822 | #define CAN0_RMP2 0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */ |
| 823 | #define CAN0_RML2 0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */ |
| 824 | #define CAN0_MBTIF2 0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */ |
| 825 | #define CAN0_MBRIF2 0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */ |
| 826 | #define CAN0_MBIM2 0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */ |
| 827 | #define CAN0_RFH2 0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */ |
| 828 | #define CAN0_OPSS2 0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */ |
| 829 | #define CAN0_CLOCK 0xFFC02A80 /* CAN Controller 0 Clock Register */ |
| 830 | #define CAN0_TIMING 0xFFC02A84 /* CAN Controller 0 Timing Register */ |
| 831 | #define CAN0_DEBUG 0xFFC02A88 /* CAN Controller 0 Debug Register */ |
| 832 | #define CAN0_STATUS 0xFFC02A8C /* CAN Controller 0 Global Status Register */ |
| 833 | #define CAN0_CEC 0xFFC02A90 /* CAN Controller 0 Error Counter Register */ |
| 834 | #define CAN0_GIS 0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */ |
| 835 | #define CAN0_GIM 0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */ |
| 836 | #define CAN0_GIF 0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */ |
| 837 | #define CAN0_CONTROL 0xFFC02AA0 /* CAN Controller 0 Master Control Register */ |
| 838 | #define CAN0_INTR 0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */ |
| 839 | #define CAN0_MBTD 0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */ |
| 840 | #define CAN0_EWR 0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */ |
| 841 | #define CAN0_ESR 0xFFC02AB4 /* CAN Controller 0 Error Status Register */ |
| 842 | #define CAN0_UCCNT 0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */ |
| 843 | #define CAN0_UCRC 0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */ |
| 844 | #define CAN0_UCCNF 0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */ |
| 845 | #define CAN0_AM00L 0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */ |
| 846 | #define CAN0_AM00H 0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */ |
| 847 | #define CAN0_AM01L 0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */ |
| 848 | #define CAN0_AM01H 0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */ |
| 849 | #define CAN0_AM02L 0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */ |
| 850 | #define CAN0_AM02H 0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */ |
| 851 | #define CAN0_AM03L 0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */ |
| 852 | #define CAN0_AM03H 0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */ |
| 853 | #define CAN0_AM04L 0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */ |
| 854 | #define CAN0_AM04H 0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */ |
| 855 | #define CAN0_AM05L 0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */ |
| 856 | #define CAN0_AM05H 0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */ |
| 857 | #define CAN0_AM06L 0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */ |
| 858 | #define CAN0_AM06H 0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */ |
| 859 | #define CAN0_AM07L 0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */ |
| 860 | #define CAN0_AM07H 0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */ |
| 861 | #define CAN0_AM08L 0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */ |
| 862 | #define CAN0_AM08H 0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */ |
| 863 | #define CAN0_AM09L 0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */ |
| 864 | #define CAN0_AM09H 0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */ |
| 865 | #define CAN0_AM10L 0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */ |
| 866 | #define CAN0_AM10H 0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */ |
| 867 | #define CAN0_AM11L 0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */ |
| 868 | #define CAN0_AM11H 0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */ |
| 869 | #define CAN0_AM12L 0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */ |
| 870 | #define CAN0_AM12H 0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */ |
| 871 | #define CAN0_AM13L 0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */ |
| 872 | #define CAN0_AM13H 0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */ |
| 873 | #define CAN0_AM14L 0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */ |
| 874 | #define CAN0_AM14H 0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */ |
| 875 | #define CAN0_AM15L 0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */ |
| 876 | #define CAN0_AM15H 0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */ |
| 877 | #define CAN0_AM16L 0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */ |
| 878 | #define CAN0_AM16H 0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */ |
| 879 | #define CAN0_AM17L 0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */ |
| 880 | #define CAN0_AM17H 0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */ |
| 881 | #define CAN0_AM18L 0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */ |
| 882 | #define CAN0_AM18H 0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */ |
| 883 | #define CAN0_AM19L 0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */ |
| 884 | #define CAN0_AM19H 0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */ |
| 885 | #define CAN0_AM20L 0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */ |
| 886 | #define CAN0_AM20H 0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */ |
| 887 | #define CAN0_AM21L 0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */ |
| 888 | #define CAN0_AM21H 0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */ |
| 889 | #define CAN0_AM22L 0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */ |
| 890 | #define CAN0_AM22H 0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */ |
| 891 | #define CAN0_AM23L 0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */ |
| 892 | #define CAN0_AM23H 0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */ |
| 893 | #define CAN0_AM24L 0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */ |
| 894 | #define CAN0_AM24H 0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */ |
| 895 | #define CAN0_AM25L 0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */ |
| 896 | #define CAN0_AM25H 0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */ |
| 897 | #define CAN0_AM26L 0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */ |
| 898 | #define CAN0_AM26H 0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */ |
| 899 | #define CAN0_AM27L 0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */ |
| 900 | #define CAN0_AM27H 0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */ |
| 901 | #define CAN0_AM28L 0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */ |
| 902 | #define CAN0_AM28H 0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */ |
| 903 | #define CAN0_AM29L 0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */ |
| 904 | #define CAN0_AM29H 0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */ |
| 905 | #define CAN0_AM30L 0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */ |
| 906 | #define CAN0_AM30H 0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */ |
| 907 | #define CAN0_AM31L 0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */ |
| 908 | #define CAN0_AM31H 0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */ |
| 909 | #define CAN0_MB00_DATA0 0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */ |
| 910 | #define CAN0_MB00_DATA1 0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */ |
| 911 | #define CAN0_MB00_DATA2 0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */ |
| 912 | #define CAN0_MB00_DATA3 0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */ |
| 913 | #define CAN0_MB00_LENGTH 0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */ |
| 914 | #define CAN0_MB00_TIMESTAMP 0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */ |
| 915 | #define CAN0_MB00_ID0 0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */ |
| 916 | #define CAN0_MB00_ID1 0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */ |
| 917 | #define CAN0_MB01_DATA0 0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */ |
| 918 | #define CAN0_MB01_DATA1 0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */ |
| 919 | #define CAN0_MB01_DATA2 0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */ |
| 920 | #define CAN0_MB01_DATA3 0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */ |
| 921 | #define CAN0_MB01_LENGTH 0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */ |
| 922 | #define CAN0_MB01_TIMESTAMP 0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */ |
| 923 | #define CAN0_MB01_ID0 0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */ |
| 924 | #define CAN0_MB01_ID1 0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */ |
| 925 | #define CAN0_MB02_DATA0 0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */ |
| 926 | #define CAN0_MB02_DATA1 0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */ |
| 927 | #define CAN0_MB02_DATA2 0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */ |
| 928 | #define CAN0_MB02_DATA3 0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */ |
| 929 | #define CAN0_MB02_LENGTH 0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */ |
| 930 | #define CAN0_MB02_TIMESTAMP 0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */ |
| 931 | #define CAN0_MB02_ID0 0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */ |
| 932 | #define CAN0_MB02_ID1 0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */ |
| 933 | #define CAN0_MB03_DATA0 0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */ |
| 934 | #define CAN0_MB03_DATA1 0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */ |
| 935 | #define CAN0_MB03_DATA2 0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */ |
| 936 | #define CAN0_MB03_DATA3 0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */ |
| 937 | #define CAN0_MB03_LENGTH 0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */ |
| 938 | #define CAN0_MB03_TIMESTAMP 0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */ |
| 939 | #define CAN0_MB03_ID0 0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */ |
| 940 | #define CAN0_MB03_ID1 0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */ |
| 941 | #define CAN0_MB04_DATA0 0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */ |
| 942 | #define CAN0_MB04_DATA1 0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */ |
| 943 | #define CAN0_MB04_DATA2 0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */ |
| 944 | #define CAN0_MB04_DATA3 0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */ |
| 945 | #define CAN0_MB04_LENGTH 0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */ |
| 946 | #define CAN0_MB04_TIMESTAMP 0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */ |
| 947 | #define CAN0_MB04_ID0 0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */ |
| 948 | #define CAN0_MB04_ID1 0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */ |
| 949 | #define CAN0_MB05_DATA0 0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */ |
| 950 | #define CAN0_MB05_DATA1 0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */ |
| 951 | #define CAN0_MB05_DATA2 0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */ |
| 952 | #define CAN0_MB05_DATA3 0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */ |
| 953 | #define CAN0_MB05_LENGTH 0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */ |
| 954 | #define CAN0_MB05_TIMESTAMP 0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */ |
| 955 | #define CAN0_MB05_ID0 0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */ |
| 956 | #define CAN0_MB05_ID1 0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */ |
| 957 | #define CAN0_MB06_DATA0 0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */ |
| 958 | #define CAN0_MB06_DATA1 0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */ |
| 959 | #define CAN0_MB06_DATA2 0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */ |
| 960 | #define CAN0_MB06_DATA3 0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */ |
| 961 | #define CAN0_MB06_LENGTH 0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */ |
| 962 | #define CAN0_MB06_TIMESTAMP 0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */ |
| 963 | #define CAN0_MB06_ID0 0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */ |
| 964 | #define CAN0_MB06_ID1 0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */ |
| 965 | #define CAN0_MB07_DATA0 0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */ |
| 966 | #define CAN0_MB07_DATA1 0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */ |
| 967 | #define CAN0_MB07_DATA2 0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */ |
| 968 | #define CAN0_MB07_DATA3 0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */ |
| 969 | #define CAN0_MB07_LENGTH 0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */ |
| 970 | #define CAN0_MB07_TIMESTAMP 0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */ |
| 971 | #define CAN0_MB07_ID0 0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */ |
| 972 | #define CAN0_MB07_ID1 0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */ |
| 973 | #define CAN0_MB08_DATA0 0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */ |
| 974 | #define CAN0_MB08_DATA1 0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */ |
| 975 | #define CAN0_MB08_DATA2 0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */ |
| 976 | #define CAN0_MB08_DATA3 0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */ |
| 977 | #define CAN0_MB08_LENGTH 0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */ |
| 978 | #define CAN0_MB08_TIMESTAMP 0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */ |
| 979 | #define CAN0_MB08_ID0 0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */ |
| 980 | #define CAN0_MB08_ID1 0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */ |
| 981 | #define CAN0_MB09_DATA0 0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */ |
| 982 | #define CAN0_MB09_DATA1 0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */ |
| 983 | #define CAN0_MB09_DATA2 0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */ |
| 984 | #define CAN0_MB09_DATA3 0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */ |
| 985 | #define CAN0_MB09_LENGTH 0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */ |
| 986 | #define CAN0_MB09_TIMESTAMP 0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */ |
| 987 | #define CAN0_MB09_ID0 0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */ |
| 988 | #define CAN0_MB09_ID1 0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */ |
| 989 | #define CAN0_MB10_DATA0 0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */ |
| 990 | #define CAN0_MB10_DATA1 0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */ |
| 991 | #define CAN0_MB10_DATA2 0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */ |
| 992 | #define CAN0_MB10_DATA3 0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */ |
| 993 | #define CAN0_MB10_LENGTH 0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */ |
| 994 | #define CAN0_MB10_TIMESTAMP 0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */ |
| 995 | #define CAN0_MB10_ID0 0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */ |
| 996 | #define CAN0_MB10_ID1 0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */ |
| 997 | #define CAN0_MB11_DATA0 0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */ |
| 998 | #define CAN0_MB11_DATA1 0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */ |
| 999 | #define CAN0_MB11_DATA2 0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */ |
| 1000 | #define CAN0_MB11_DATA3 0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */ |
| 1001 | #define CAN0_MB11_LENGTH 0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */ |
| 1002 | #define CAN0_MB11_TIMESTAMP 0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */ |
| 1003 | #define CAN0_MB11_ID0 0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */ |
| 1004 | #define CAN0_MB11_ID1 0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */ |
| 1005 | #define CAN0_MB12_DATA0 0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */ |
| 1006 | #define CAN0_MB12_DATA1 0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */ |
| 1007 | #define CAN0_MB12_DATA2 0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */ |
| 1008 | #define CAN0_MB12_DATA3 0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */ |
| 1009 | #define CAN0_MB12_LENGTH 0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */ |
| 1010 | #define CAN0_MB12_TIMESTAMP 0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */ |
| 1011 | #define CAN0_MB12_ID0 0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */ |
| 1012 | #define CAN0_MB12_ID1 0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */ |
| 1013 | #define CAN0_MB13_DATA0 0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */ |
| 1014 | #define CAN0_MB13_DATA1 0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */ |
| 1015 | #define CAN0_MB13_DATA2 0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */ |
| 1016 | #define CAN0_MB13_DATA3 0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */ |
| 1017 | #define CAN0_MB13_LENGTH 0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */ |
| 1018 | #define CAN0_MB13_TIMESTAMP 0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */ |
| 1019 | #define CAN0_MB13_ID0 0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */ |
| 1020 | #define CAN0_MB13_ID1 0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */ |
| 1021 | #define CAN0_MB14_DATA0 0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */ |
| 1022 | #define CAN0_MB14_DATA1 0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */ |
| 1023 | #define CAN0_MB14_DATA2 0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */ |
| 1024 | #define CAN0_MB14_DATA3 0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */ |
| 1025 | #define CAN0_MB14_LENGTH 0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */ |
| 1026 | #define CAN0_MB14_TIMESTAMP 0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */ |
| 1027 | #define CAN0_MB14_ID0 0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */ |
| 1028 | #define CAN0_MB14_ID1 0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */ |
| 1029 | #define CAN0_MB15_DATA0 0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */ |
| 1030 | #define CAN0_MB15_DATA1 0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */ |
| 1031 | #define CAN0_MB15_DATA2 0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */ |
| 1032 | #define CAN0_MB15_DATA3 0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */ |
| 1033 | #define CAN0_MB15_LENGTH 0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */ |
| 1034 | #define CAN0_MB15_TIMESTAMP 0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */ |
| 1035 | #define CAN0_MB15_ID0 0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */ |
| 1036 | #define CAN0_MB15_ID1 0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */ |
| 1037 | #define CAN0_MB16_DATA0 0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */ |
| 1038 | #define CAN0_MB16_DATA1 0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */ |
| 1039 | #define CAN0_MB16_DATA2 0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */ |
| 1040 | #define CAN0_MB16_DATA3 0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */ |
| 1041 | #define CAN0_MB16_LENGTH 0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */ |
| 1042 | #define CAN0_MB16_TIMESTAMP 0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */ |
| 1043 | #define CAN0_MB16_ID0 0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */ |
| 1044 | #define CAN0_MB16_ID1 0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */ |
| 1045 | #define CAN0_MB17_DATA0 0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */ |
| 1046 | #define CAN0_MB17_DATA1 0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */ |
| 1047 | #define CAN0_MB17_DATA2 0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */ |
| 1048 | #define CAN0_MB17_DATA3 0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */ |
| 1049 | #define CAN0_MB17_LENGTH 0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */ |
| 1050 | #define CAN0_MB17_TIMESTAMP 0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */ |
| 1051 | #define CAN0_MB17_ID0 0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */ |
| 1052 | #define CAN0_MB17_ID1 0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */ |
| 1053 | #define CAN0_MB18_DATA0 0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */ |
| 1054 | #define CAN0_MB18_DATA1 0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */ |
| 1055 | #define CAN0_MB18_DATA2 0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */ |
| 1056 | #define CAN0_MB18_DATA3 0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */ |
| 1057 | #define CAN0_MB18_LENGTH 0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */ |
| 1058 | #define CAN0_MB18_TIMESTAMP 0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */ |
| 1059 | #define CAN0_MB18_ID0 0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */ |
| 1060 | #define CAN0_MB18_ID1 0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */ |
| 1061 | #define CAN0_MB19_DATA0 0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */ |
| 1062 | #define CAN0_MB19_DATA1 0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */ |
| 1063 | #define CAN0_MB19_DATA2 0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */ |
| 1064 | #define CAN0_MB19_DATA3 0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */ |
| 1065 | #define CAN0_MB19_LENGTH 0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */ |
| 1066 | #define CAN0_MB19_TIMESTAMP 0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */ |
| 1067 | #define CAN0_MB19_ID0 0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */ |
| 1068 | #define CAN0_MB19_ID1 0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */ |
| 1069 | #define CAN0_MB20_DATA0 0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */ |
| 1070 | #define CAN0_MB20_DATA1 0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */ |
| 1071 | #define CAN0_MB20_DATA2 0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */ |
| 1072 | #define CAN0_MB20_DATA3 0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */ |
| 1073 | #define CAN0_MB20_LENGTH 0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */ |
| 1074 | #define CAN0_MB20_TIMESTAMP 0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */ |
| 1075 | #define CAN0_MB20_ID0 0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */ |
| 1076 | #define CAN0_MB20_ID1 0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */ |
| 1077 | #define CAN0_MB21_DATA0 0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */ |
| 1078 | #define CAN0_MB21_DATA1 0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */ |
| 1079 | #define CAN0_MB21_DATA2 0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */ |
| 1080 | #define CAN0_MB21_DATA3 0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */ |
| 1081 | #define CAN0_MB21_LENGTH 0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */ |
| 1082 | #define CAN0_MB21_TIMESTAMP 0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */ |
| 1083 | #define CAN0_MB21_ID0 0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */ |
| 1084 | #define CAN0_MB21_ID1 0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */ |
| 1085 | #define CAN0_MB22_DATA0 0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */ |
| 1086 | #define CAN0_MB22_DATA1 0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */ |
| 1087 | #define CAN0_MB22_DATA2 0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */ |
| 1088 | #define CAN0_MB22_DATA3 0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */ |
| 1089 | #define CAN0_MB22_LENGTH 0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */ |
| 1090 | #define CAN0_MB22_TIMESTAMP 0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */ |
| 1091 | #define CAN0_MB22_ID0 0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */ |
| 1092 | #define CAN0_MB22_ID1 0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */ |
| 1093 | #define CAN0_MB23_DATA0 0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */ |
| 1094 | #define CAN0_MB23_DATA1 0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */ |
| 1095 | #define CAN0_MB23_DATA2 0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */ |
| 1096 | #define CAN0_MB23_DATA3 0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */ |
| 1097 | #define CAN0_MB23_LENGTH 0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */ |
| 1098 | #define CAN0_MB23_TIMESTAMP 0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */ |
| 1099 | #define CAN0_MB23_ID0 0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */ |
| 1100 | #define CAN0_MB23_ID1 0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */ |
| 1101 | #define CAN0_MB24_DATA0 0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */ |
| 1102 | #define CAN0_MB24_DATA1 0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */ |
| 1103 | #define CAN0_MB24_DATA2 0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */ |
| 1104 | #define CAN0_MB24_DATA3 0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */ |
| 1105 | #define CAN0_MB24_LENGTH 0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */ |
| 1106 | #define CAN0_MB24_TIMESTAMP 0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */ |
| 1107 | #define CAN0_MB24_ID0 0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */ |
| 1108 | #define CAN0_MB24_ID1 0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */ |
| 1109 | #define CAN0_MB25_DATA0 0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */ |
| 1110 | #define CAN0_MB25_DATA1 0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */ |
| 1111 | #define CAN0_MB25_DATA2 0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */ |
| 1112 | #define CAN0_MB25_DATA3 0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */ |
| 1113 | #define CAN0_MB25_LENGTH 0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */ |
| 1114 | #define CAN0_MB25_TIMESTAMP 0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */ |
| 1115 | #define CAN0_MB25_ID0 0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */ |
| 1116 | #define CAN0_MB25_ID1 0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */ |
| 1117 | #define CAN0_MB26_DATA0 0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */ |
| 1118 | #define CAN0_MB26_DATA1 0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */ |
| 1119 | #define CAN0_MB26_DATA2 0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */ |
| 1120 | #define CAN0_MB26_DATA3 0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */ |
| 1121 | #define CAN0_MB26_LENGTH 0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */ |
| 1122 | #define CAN0_MB26_TIMESTAMP 0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */ |
| 1123 | #define CAN0_MB26_ID0 0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */ |
| 1124 | #define CAN0_MB26_ID1 0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */ |
| 1125 | #define CAN0_MB27_DATA0 0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */ |
| 1126 | #define CAN0_MB27_DATA1 0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */ |
| 1127 | #define CAN0_MB27_DATA2 0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */ |
| 1128 | #define CAN0_MB27_DATA3 0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */ |
| 1129 | #define CAN0_MB27_LENGTH 0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */ |
| 1130 | #define CAN0_MB27_TIMESTAMP 0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */ |
| 1131 | #define CAN0_MB27_ID0 0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */ |
| 1132 | #define CAN0_MB27_ID1 0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */ |
| 1133 | #define CAN0_MB28_DATA0 0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */ |
| 1134 | #define CAN0_MB28_DATA1 0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */ |
| 1135 | #define CAN0_MB28_DATA2 0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */ |
| 1136 | #define CAN0_MB28_DATA3 0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */ |
| 1137 | #define CAN0_MB28_LENGTH 0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */ |
| 1138 | #define CAN0_MB28_TIMESTAMP 0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */ |
| 1139 | #define CAN0_MB28_ID0 0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */ |
| 1140 | #define CAN0_MB28_ID1 0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */ |
| 1141 | #define CAN0_MB29_DATA0 0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */ |
| 1142 | #define CAN0_MB29_DATA1 0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */ |
| 1143 | #define CAN0_MB29_DATA2 0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */ |
| 1144 | #define CAN0_MB29_DATA3 0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */ |
| 1145 | #define CAN0_MB29_LENGTH 0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */ |
| 1146 | #define CAN0_MB29_TIMESTAMP 0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */ |
| 1147 | #define CAN0_MB29_ID0 0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */ |
| 1148 | #define CAN0_MB29_ID1 0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */ |
| 1149 | #define CAN0_MB30_DATA0 0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */ |
| 1150 | #define CAN0_MB30_DATA1 0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */ |
| 1151 | #define CAN0_MB30_DATA2 0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */ |
| 1152 | #define CAN0_MB30_DATA3 0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */ |
| 1153 | #define CAN0_MB30_LENGTH 0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */ |
| 1154 | #define CAN0_MB30_TIMESTAMP 0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */ |
| 1155 | #define CAN0_MB30_ID0 0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */ |
| 1156 | #define CAN0_MB30_ID1 0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */ |
| 1157 | #define CAN0_MB31_DATA0 0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */ |
| 1158 | #define CAN0_MB31_DATA1 0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */ |
| 1159 | #define CAN0_MB31_DATA2 0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */ |
| 1160 | #define CAN0_MB31_DATA3 0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */ |
| 1161 | #define CAN0_MB31_LENGTH 0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */ |
| 1162 | #define CAN0_MB31_TIMESTAMP 0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */ |
| 1163 | #define CAN0_MB31_ID0 0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */ |
| 1164 | #define CAN0_MB31_ID1 0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */ |
| 1165 | #define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */ |
| 1166 | #define SPI0_FLG 0xFFC00504 /* SPI0 Flag Register */ |
| 1167 | #define SPI0_STAT 0xFFC00508 /* SPI0 Status Register */ |
| 1168 | #define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */ |
| 1169 | #define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */ |
| 1170 | #define SPI0_BAUD 0xFFC00514 /* SPI0 Baud Rate Register */ |
| 1171 | #define SPI0_SHADOW 0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */ |
| 1172 | #define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */ |
| 1173 | #define SPI1_FLG 0xFFC02304 /* SPI1 Flag Register */ |
| 1174 | #define SPI1_STAT 0xFFC02308 /* SPI1 Status Register */ |
| 1175 | #define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */ |
| 1176 | #define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */ |
| 1177 | #define SPI1_BAUD 0xFFC02314 /* SPI1 Baud Rate Register */ |
| 1178 | #define SPI1_SHADOW 0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */ |
| 1179 | #define TWI0_CLKDIV 0xFFC00700 /* Clock Divider Register */ |
| 1180 | #define TWI0_CONTROL 0xFFC00704 /* TWI Control Register */ |
| 1181 | #define TWI0_SLAVE_CTL 0xFFC00708 /* TWI Slave Mode Control Register */ |
| 1182 | #define TWI0_SLAVE_STAT 0xFFC0070C /* TWI Slave Mode Status Register */ |
| 1183 | #define TWI0_SLAVE_ADDR 0xFFC00710 /* TWI Slave Mode Address Register */ |
| 1184 | #define TWI0_MASTER_CTL 0xFFC00714 /* TWI Master Mode Control Register */ |
| 1185 | #define TWI0_MASTER_STAT 0xFFC00718 /* TWI Master Mode Status Register */ |
| 1186 | #define TWI0_MASTER_ADDR 0xFFC0071C /* TWI Master Mode Address Register */ |
| 1187 | #define TWI0_INT_STAT 0xFFC00720 /* TWI Interrupt Status Register */ |
| 1188 | #define TWI0_INT_MASK 0xFFC00724 /* TWI Interrupt Mask Register */ |
| 1189 | #define TWI0_FIFO_CTL 0xFFC00728 /* TWI FIFO Control Register */ |
| 1190 | #define TWI0_FIFO_STAT 0xFFC0072C /* TWI FIFO Status Register */ |
| 1191 | #define TWI0_XMT_DATA8 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */ |
| 1192 | #define TWI0_XMT_DATA16 0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */ |
| 1193 | #define TWI0_RCV_DATA8 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */ |
| 1194 | #define TWI0_RCV_DATA16 0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */ |
| 1195 | #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ |
| 1196 | #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ |
| 1197 | #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */ |
| 1198 | #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */ |
| 1199 | #define SPORT1_TX 0xFFC00910 /* SPORT1 Transmit Data Register */ |
| 1200 | #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Receive Configuration 1 Register */ |
| 1201 | #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Receive Configuration 2 Register */ |
| 1202 | #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */ |
| 1203 | #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */ |
| 1204 | #define SPORT1_RX 0xFFC00918 /* SPORT1 Receive Data Register */ |
| 1205 | #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ |
| 1206 | #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */ |
| 1207 | #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */ |
| 1208 | #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ |
| 1209 | #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */ |
| 1210 | #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */ |
| 1211 | #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */ |
| 1212 | #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */ |
| 1213 | #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */ |
| 1214 | #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */ |
| 1215 | #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */ |
| 1216 | #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */ |
| 1217 | #define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */ |
| 1218 | #define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */ |
| 1219 | #define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */ |
| 1220 | #define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */ |
| 1221 | #define SPORT2_TX 0xFFC02510 /* SPORT2 Transmit Data Register */ |
| 1222 | #define SPORT2_RCR1 0xFFC02520 /* SPORT2 Receive Configuration 1 Register */ |
| 1223 | #define SPORT2_RCR2 0xFFC02524 /* SPORT2 Receive Configuration 2 Register */ |
| 1224 | #define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */ |
| 1225 | #define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */ |
| 1226 | #define SPORT2_RX 0xFFC02518 /* SPORT2 Receive Data Register */ |
| 1227 | #define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */ |
| 1228 | #define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */ |
| 1229 | #define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */ |
| 1230 | #define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */ |
| 1231 | #define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */ |
| 1232 | #define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */ |
| 1233 | #define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */ |
| 1234 | #define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */ |
| 1235 | #define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */ |
| 1236 | #define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */ |
| 1237 | #define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */ |
| 1238 | #define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */ |
| 1239 | #define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */ |
| 1240 | #define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */ |
| 1241 | #define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */ |
| 1242 | #define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */ |
| 1243 | #define SPORT3_TX 0xFFC02610 /* SPORT3 Transmit Data Register */ |
| 1244 | #define SPORT3_RCR1 0xFFC02620 /* SPORT3 Receive Configuration 1 Register */ |
| 1245 | #define SPORT3_RCR2 0xFFC02624 /* SPORT3 Receive Configuration 2 Register */ |
| 1246 | #define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */ |
| 1247 | #define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */ |
| 1248 | #define SPORT3_RX 0xFFC02618 /* SPORT3 Receive Data Register */ |
| 1249 | #define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */ |
| 1250 | #define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */ |
| 1251 | #define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */ |
| 1252 | #define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */ |
| 1253 | #define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */ |
| 1254 | #define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */ |
| 1255 | #define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */ |
| 1256 | #define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */ |
| 1257 | #define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */ |
| 1258 | #define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */ |
| 1259 | #define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */ |
| 1260 | #define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */ |
| 1261 | #define UART0_DLL 0xFFC00400 /* Divisor Latch Low Byte */ |
| 1262 | #define UART0_DLH 0xFFC00404 /* Divisor Latch High Byte */ |
| 1263 | #define UART0_GCTL 0xFFC00408 /* Global Control Register */ |
| 1264 | #define UART0_LCR 0xFFC0040C /* Line Control Register */ |
| 1265 | #define UART0_MCR 0xFFC00410 /* Modem Control Register */ |
| 1266 | #define UART0_LSR 0xFFC00414 /* Line Status Register */ |
| 1267 | #define UART0_MSR 0xFFC00418 /* Modem Status Register */ |
| 1268 | #define UART0_SCR 0xFFC0041C /* Scratch Register */ |
| 1269 | #define UART0_IER_SET 0xFFC00420 /* Interrupt Enable Register Set */ |
| 1270 | #define UART0_IER_CLEAR 0xFFC00424 /* Interrupt Enable Register Clear */ |
| 1271 | #define UART0_THR 0xFFC00428 /* Transmit Hold Register */ |
| 1272 | #define UART0_RBR 0xFFC0042C /* Receive Buffer Register */ |
| 1273 | #define UART1_DLL 0xFFC02000 /* Divisor Latch Low Byte */ |
| 1274 | #define UART1_DLH 0xFFC02004 /* Divisor Latch High Byte */ |
| 1275 | #define UART1_GCTL 0xFFC02008 /* Global Control Register */ |
| 1276 | #define UART1_LCR 0xFFC0200C /* Line Control Register */ |
| 1277 | #define UART1_MCR 0xFFC02010 /* Modem Control Register */ |
| 1278 | #define UART1_LSR 0xFFC02014 /* Line Status Register */ |
| 1279 | #define UART1_MSR 0xFFC02018 /* Modem Status Register */ |
| 1280 | #define UART1_SCR 0xFFC0201C /* Scratch Register */ |
| 1281 | #define UART1_IER_SET 0xFFC02020 /* Interrupt Enable Register Set */ |
| 1282 | #define UART1_IER_CLEAR 0xFFC02024 /* Interrupt Enable Register Clear */ |
| 1283 | #define UART1_THR 0xFFC02028 /* Transmit Hold Register */ |
| 1284 | #define UART1_RBR 0xFFC0202C /* Receive Buffer Register */ |
| 1285 | #define UART3_DLL 0xFFC03100 /* Divisor Latch Low Byte */ |
| 1286 | #define UART3_DLH 0xFFC03104 /* Divisor Latch High Byte */ |
| 1287 | #define UART3_GCTL 0xFFC03108 /* Global Control Register */ |
| 1288 | #define UART3_LCR 0xFFC0310C /* Line Control Register */ |
| 1289 | #define UART3_MCR 0xFFC03110 /* Modem Control Register */ |
| 1290 | #define UART3_LSR 0xFFC03114 /* Line Status Register */ |
| 1291 | #define UART3_MSR 0xFFC03118 /* Modem Status Register */ |
| 1292 | #define UART3_SCR 0xFFC0311C /* Scratch Register */ |
| 1293 | #define UART3_IER_SET 0xFFC03120 /* Interrupt Enable Register Set */ |
| 1294 | #define UART3_IER_CLEAR 0xFFC03124 /* Interrupt Enable Register Clear */ |
| 1295 | #define UART3_THR 0xFFC03128 /* Transmit Hold Register */ |
| 1296 | #define UART3_RBR 0xFFC0312C /* Receive Buffer Register */ |
| 1297 | #define USB_FADDR 0xFFC03C00 /* Function address register */ |
| 1298 | #define USB_POWER 0xFFC03C04 /* Power management register */ |
| 1299 | #define USB_INTRTX 0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ |
| 1300 | #define USB_INTRRX 0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */ |
| 1301 | #define USB_INTRTXE 0xFFC03C10 /* Interrupt enable register for IntrTx */ |
| 1302 | #define USB_INTRRXE 0xFFC03C14 /* Interrupt enable register for IntrRx */ |
| 1303 | #define USB_INTRUSB 0xFFC03C18 /* Interrupt register for common USB interrupts */ |
| 1304 | #define USB_INTRUSBE 0xFFC03C1C /* Interrupt enable register for IntrUSB */ |
| 1305 | #define USB_FRAME 0xFFC03C20 /* USB frame number */ |
| 1306 | #define USB_INDEX 0xFFC03C24 /* Index register for selecting the indexed endpoint registers */ |
| 1307 | #define USB_TESTMODE 0xFFC03C28 /* Enabled USB 20 test modes */ |
| 1308 | #define USB_GLOBINTR 0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */ |
| 1309 | #define USB_GLOBAL_CTL 0xFFC03C30 /* Global Clock Control for the core */ |
| 1310 | #define USB_TX_MAX_PACKET 0xFFC03C40 /* Maximum packet size for Host Tx endpoint */ |
| 1311 | #define USB_CSR0 0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ |
| 1312 | #define USB_TXCSR 0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ |
| 1313 | #define USB_RX_MAX_PACKET 0xFFC03C48 /* Maximum packet size for Host Rx endpoint */ |
| 1314 | #define USB_RXCSR 0xFFC03C4C /* Control Status register for Host Rx endpoint */ |
| 1315 | #define USB_COUNT0 0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ |
| 1316 | #define USB_RXCOUNT 0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ |
| 1317 | #define USB_TXTYPE 0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ |
| 1318 | #define USB_NAKLIMIT0 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ |
| 1319 | #define USB_TXINTERVAL 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ |
| 1320 | #define USB_RXTYPE 0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ |
| 1321 | #define USB_RXINTERVAL 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ |
| 1322 | #define USB_TXCOUNT 0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ |
| 1323 | #define USB_EP0_FIFO 0xFFC03C80 /* Endpoint 0 FIFO */ |
| 1324 | #define USB_EP1_FIFO 0xFFC03C88 /* Endpoint 1 FIFO */ |
| 1325 | #define USB_EP2_FIFO 0xFFC03C90 /* Endpoint 2 FIFO */ |
| 1326 | #define USB_EP3_FIFO 0xFFC03C98 /* Endpoint 3 FIFO */ |
| 1327 | #define USB_EP4_FIFO 0xFFC03CA0 /* Endpoint 4 FIFO */ |
| 1328 | #define USB_EP5_FIFO 0xFFC03CA8 /* Endpoint 5 FIFO */ |
| 1329 | #define USB_EP6_FIFO 0xFFC03CB0 /* Endpoint 6 FIFO */ |
| 1330 | #define USB_EP7_FIFO 0xFFC03CB8 /* Endpoint 7 FIFO */ |
| 1331 | #define USB_OTG_DEV_CTL 0xFFC03D00 /* OTG Device Control Register */ |
| 1332 | #define USB_OTG_VBUS_IRQ 0xFFC03D04 /* OTG VBUS Control Interrupts */ |
| 1333 | #define USB_OTG_VBUS_MASK 0xFFC03D08 /* VBUS Control Interrupt Enable */ |
| 1334 | #define USB_LINKINFO 0xFFC03D48 /* Enables programming of some PHY-side delays */ |
| 1335 | #define USB_VPLEN 0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */ |
| 1336 | #define USB_HS_EOF1 0xFFC03D50 /* Time buffer for High-Speed transactions */ |
| 1337 | #define USB_FS_EOF1 0xFFC03D54 /* Time buffer for Full-Speed transactions */ |
| 1338 | #define USB_LS_EOF1 0xFFC03D58 /* Time buffer for Low-Speed transactions */ |
| 1339 | #define USB_APHY_CNTRL 0xFFC03DE0 /* Register that increases visibility of Analog PHY */ |
| 1340 | #define USB_APHY_CALIB 0xFFC03DE4 /* Register used to set some calibration values */ |
| 1341 | #define USB_APHY_CNTRL2 0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ |
| 1342 | #define USB_PHY_TEST 0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */ |
| 1343 | #define USB_PLLOSC_CTRL 0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */ |
| 1344 | #define USB_SRP_CLKDIV 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ |
| 1345 | #define USB_EP_NI0_TXMAXP 0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */ |
| 1346 | #define USB_EP_NI0_TXCSR 0xFFC03E04 /* Control Status register for endpoint 0 */ |
| 1347 | #define USB_EP_NI0_RXMAXP 0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */ |
| 1348 | #define USB_EP_NI0_RXCSR 0xFFC03E0C /* Control Status register for Host Rx endpoint0 */ |
| 1349 | #define USB_EP_NI0_RXCOUNT 0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */ |
| 1350 | #define USB_EP_NI0_TXTYPE 0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ |
| 1351 | #define USB_EP_NI0_TXINTERVAL 0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */ |
| 1352 | #define USB_EP_NI0_RXTYPE 0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ |
| 1353 | #define USB_EP_NI0_RXINTERVAL 0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ |
| 1354 | #define USB_EP_NI0_TXCOUNT 0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ |
| 1355 | #define USB_EP_NI1_TXMAXP 0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */ |
| 1356 | #define USB_EP_NI1_TXCSR 0xFFC03E44 /* Control Status register for endpoint1 */ |
| 1357 | #define USB_EP_NI1_RXMAXP 0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */ |
| 1358 | #define USB_EP_NI1_RXCSR 0xFFC03E4C /* Control Status register for Host Rx endpoint1 */ |
| 1359 | #define USB_EP_NI1_RXCOUNT 0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */ |
| 1360 | #define USB_EP_NI1_TXTYPE 0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ |
| 1361 | #define USB_EP_NI1_TXINTERVAL 0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */ |
| 1362 | #define USB_EP_NI1_RXTYPE 0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ |
| 1363 | #define USB_EP_NI1_RXINTERVAL 0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ |
| 1364 | #define USB_EP_NI1_TXCOUNT 0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ |
| 1365 | #define USB_EP_NI2_TXMAXP 0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */ |
| 1366 | #define USB_EP_NI2_TXCSR 0xFFC03E84 /* Control Status register for endpoint2 */ |
| 1367 | #define USB_EP_NI2_RXMAXP 0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */ |
| 1368 | #define USB_EP_NI2_RXCSR 0xFFC03E8C /* Control Status register for Host Rx endpoint2 */ |
| 1369 | #define USB_EP_NI2_RXCOUNT 0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */ |
| 1370 | #define USB_EP_NI2_TXTYPE 0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ |
| 1371 | #define USB_EP_NI2_TXINTERVAL 0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */ |
| 1372 | #define USB_EP_NI2_RXTYPE 0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ |
| 1373 | #define USB_EP_NI2_RXINTERVAL 0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ |
| 1374 | #define USB_EP_NI2_TXCOUNT 0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ |
| 1375 | #define USB_EP_NI3_TXMAXP 0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */ |
| 1376 | #define USB_EP_NI3_TXCSR 0xFFC03EC4 /* Control Status register for endpoint3 */ |
| 1377 | #define USB_EP_NI3_RXMAXP 0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */ |
| 1378 | #define USB_EP_NI3_RXCSR 0xFFC03ECC /* Control Status register for Host Rx endpoint3 */ |
| 1379 | #define USB_EP_NI3_RXCOUNT 0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */ |
| 1380 | #define USB_EP_NI3_TXTYPE 0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ |
| 1381 | #define USB_EP_NI3_TXINTERVAL 0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */ |
| 1382 | #define USB_EP_NI3_RXTYPE 0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ |
| 1383 | #define USB_EP_NI3_RXINTERVAL 0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ |
| 1384 | #define USB_EP_NI3_TXCOUNT 0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ |
| 1385 | #define USB_EP_NI4_TXMAXP 0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */ |
| 1386 | #define USB_EP_NI4_TXCSR 0xFFC03F04 /* Control Status register for endpoint4 */ |
| 1387 | #define USB_EP_NI4_RXMAXP 0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */ |
| 1388 | #define USB_EP_NI4_RXCSR 0xFFC03F0C /* Control Status register for Host Rx endpoint4 */ |
| 1389 | #define USB_EP_NI4_RXCOUNT 0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */ |
| 1390 | #define USB_EP_NI4_TXTYPE 0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ |
| 1391 | #define USB_EP_NI4_TXINTERVAL 0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */ |
| 1392 | #define USB_EP_NI4_RXTYPE 0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ |
| 1393 | #define USB_EP_NI4_RXINTERVAL 0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ |
| 1394 | #define USB_EP_NI4_TXCOUNT 0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ |
| 1395 | #define USB_EP_NI5_TXMAXP 0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */ |
| 1396 | #define USB_EP_NI5_TXCSR 0xFFC03F44 /* Control Status register for endpoint5 */ |
| 1397 | #define USB_EP_NI5_RXMAXP 0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */ |
| 1398 | #define USB_EP_NI5_RXCSR 0xFFC03F4C /* Control Status register for Host Rx endpoint5 */ |
| 1399 | #define USB_EP_NI5_RXCOUNT 0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */ |
| 1400 | #define USB_EP_NI5_TXTYPE 0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ |
| 1401 | #define USB_EP_NI5_TXINTERVAL 0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */ |
| 1402 | #define USB_EP_NI5_RXTYPE 0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ |
| 1403 | #define USB_EP_NI5_RXINTERVAL 0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ |
| 1404 | #define USB_EP_NI5_TXCOUNT 0xFFC03F68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ |
| 1405 | #define USB_EP_NI6_TXMAXP 0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */ |
| 1406 | #define USB_EP_NI6_TXCSR 0xFFC03F84 /* Control Status register for endpoint6 */ |
| 1407 | #define USB_EP_NI6_RXMAXP 0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */ |
| 1408 | #define USB_EP_NI6_RXCSR 0xFFC03F8C /* Control Status register for Host Rx endpoint6 */ |
| 1409 | #define USB_EP_NI6_RXCOUNT 0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */ |
| 1410 | #define USB_EP_NI6_TXTYPE 0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ |
| 1411 | #define USB_EP_NI6_TXINTERVAL 0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */ |
| 1412 | #define USB_EP_NI6_RXTYPE 0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ |
| 1413 | #define USB_EP_NI6_RXINTERVAL 0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ |
| 1414 | #define USB_EP_NI6_TXCOUNT 0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ |
| 1415 | #define USB_EP_NI7_TXMAXP 0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */ |
| 1416 | #define USB_EP_NI7_TXCSR 0xFFC03FC4 /* Control Status register for endpoint7 */ |
| 1417 | #define USB_EP_NI7_RXMAXP 0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */ |
| 1418 | #define USB_EP_NI7_RXCSR 0xFFC03FCC /* Control Status register for Host Rx endpoint7 */ |
| 1419 | #define USB_EP_NI7_RXCOUNT 0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */ |
| 1420 | #define USB_EP_NI7_TXTYPE 0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ |
| 1421 | #define USB_EP_NI7_TXINTERVAL 0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */ |
| 1422 | #define USB_EP_NI7_RXTYPE 0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ |
| 1423 | #define USB_EP_NI7_RXINTERVAL 0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ |
| 1424 | #define USB_EP_NI7_TXCOUNT 0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ |
| 1425 | #define USB_DMA_INTERRUPT 0xFFC04000 /* Indicates pending interrupts for the DMA channels */ |
| 1426 | #define USB_DMA0_CONTROL 0xFFC04004 /* DMA master channel 0 configuration */ |
| 1427 | #define USB_DMA0_ADDRLOW 0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ |
| 1428 | #define USB_DMA0_ADDRHIGH 0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ |
| 1429 | #define USB_DMA0_COUNTLOW 0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ |
| 1430 | #define USB_DMA0_COUNTHIGH 0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ |
| 1431 | #define USB_DMA1_CONTROL 0xFFC04024 /* DMA master channel 1 configuration */ |
| 1432 | #define USB_DMA1_ADDRLOW 0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ |
| 1433 | #define USB_DMA1_ADDRHIGH 0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ |
| 1434 | #define USB_DMA1_COUNTLOW 0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ |
| 1435 | #define USB_DMA1_COUNTHIGH 0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ |
| 1436 | #define USB_DMA2_CONTROL 0xFFC04044 /* DMA master channel 2 configuration */ |
| 1437 | #define USB_DMA2_ADDRLOW 0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ |
| 1438 | #define USB_DMA2_ADDRHIGH 0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ |
| 1439 | #define USB_DMA2_COUNTLOW 0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ |
| 1440 | #define USB_DMA2_COUNTHIGH 0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ |
| 1441 | #define USB_DMA3_CONTROL 0xFFC04064 /* DMA master channel 3 configuration */ |
| 1442 | #define USB_DMA3_ADDRLOW 0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ |
| 1443 | #define USB_DMA3_ADDRHIGH 0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ |
| 1444 | #define USB_DMA3_COUNTLOW 0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ |
| 1445 | #define USB_DMA3_COUNTHIGH 0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ |
| 1446 | #define USB_DMA4_CONTROL 0xFFC04084 /* DMA master channel 4 configuration */ |
| 1447 | #define USB_DMA4_ADDRLOW 0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ |
| 1448 | #define USB_DMA4_ADDRHIGH 0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ |
| 1449 | #define USB_DMA4_COUNTLOW 0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ |
| 1450 | #define USB_DMA4_COUNTHIGH 0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ |
| 1451 | #define USB_DMA5_CONTROL 0xFFC040A4 /* DMA master channel 5 configuration */ |
| 1452 | #define USB_DMA5_ADDRLOW 0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ |
| 1453 | #define USB_DMA5_ADDRHIGH 0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ |
| 1454 | #define USB_DMA5_COUNTLOW 0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ |
| 1455 | #define USB_DMA5_COUNTHIGH 0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ |
| 1456 | #define USB_DMA6_CONTROL 0xFFC040C4 /* DMA master channel 6 configuration */ |
| 1457 | #define USB_DMA6_ADDRLOW 0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ |
| 1458 | #define USB_DMA6_ADDRHIGH 0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ |
| 1459 | #define USB_DMA6_COUNTLOW 0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ |
| 1460 | #define USB_DMA6_COUNTHIGH 0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ |
| 1461 | #define USB_DMA7_CONTROL 0xFFC040E4 /* DMA master channel 7 configuration */ |
| 1462 | #define USB_DMA7_ADDRLOW 0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ |
| 1463 | #define USB_DMA7_ADDRHIGH 0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ |
| 1464 | #define USB_DMA7_COUNTLOW 0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ |
| 1465 | #define USB_DMA7_COUNTHIGH 0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ |
| 1466 | |
| 1467 | #endif /* __BFIN_DEF_ADSP_EDN_BF542_extended__ */ |